A pseudocode delayed replica generation system and method for generating a pseudocode delayed replica

Abstract

This invention provides a pseudo-code delay copy generation system, including a code NCO, a code generator, and a code delay copy generator. The code NCO generates a code clock signal, the code generator outputs a code stream, and the code delay copy generator outputs pseudo-code delay copies. The code delay copy generator includes M-level code delay lines, multiple phase comparators, and multiple output selectors, with each output selector connected to a phase comparator. In the digital domain, multiple pseudo-code delay copies can be generated simultaneously using only one code NCO and one code generator, meeting the requirements for a large delay range and high-precision delay control. The delay range of the pseudo-code, the number of output copies, and the delay resolution can be flexibly set according to specific needs, and the delay amount is easily dynamically adjusted.

Description

Technical Field

[0001] This invention relates to the field of spread spectrum communication and navigation technology, and in particular to a pseudo-code delayed copy generation system. Background Technology

[0002] In spread spectrum communication applications, such as ranging signals in satellite navigation systems, pseudo-random sequence codes are used to spread the spectrum. At the receiving end, the same reproduced pseudo-code is used for despreading. Demodulation of spread spectrum signals often employs Delayed-Locked Loop (DLL) technology. This involves locally generating two (early) and three (early, mid-night, late) pseudo-code signals, which are correlated and accumulated with the input signal. The accumulated values ​​from these multiple signals represent the sampled values ​​at different positions of the autocorrelation peak, and the tracking error of the pseudo-code can be calculated, thus enabling signal acquisition and continuous tracking. The "early" and "late" or "early, mid-night, late" pseudo-code signals are copies of the same pseudo-code sequence generated with different delays. During signal acquisition and tracking, or when employing different signal processing techniques such as parallel acquisition with multiple correlators, narrow correlation, MEDLL (Multipath Estimating Delay Locked Loop), or signal quality monitoring, it is necessary to sample the correlation peak at different intervals, simultaneously generating multiple pseudo-code copies with different delays.

[0003] Furthermore, in spread spectrum signal simulation sources, especially GNSS satellite navigation simulators, there is often a need to simulate multipath signal propagation. Multipath signals are actually delayed direct signals. In the simulation source, in addition to the pseudocode of the direct signal, it is also necessary to generate one or more pseudocodes of multipath signals with a certain delay relative to the direct signal. In order to simulate the continuous changes of multipath signals, the delay amount can be any value between 0 and 1.0 chips, requiring the generation of one or more continuously changing delay replicas.

[0004] In digital circuits, pseudocode is generated by a digitally controlled oscillator (NCO) to drive the code generator's output code stream. Different replica signals are then obtained after a delay. The controllable delay is typically achieved using a global operating clock. For example, if the global clock frequency is f0 = 50MHz and the pseudocode rate is f... code =1.023MHz, then the delay of one clock cycle is approximately To generate a 1.0-chip delay, 50 ticks are required.

[0005] The main drawbacks of using a global clock to implement delay are twofold: the delay accuracy (resolution) is limited by the frequency of the global clock, which cannot fully meet the requirements for flexible selection of different sampling intervals of correlation peaks or accurate delay of multipath signal simulation propagation; delays of multiple clock cycles will consume more register or RAM resources, especially for low-rate pseudocode.

[0006] To obtain a precise delay, two independent code NCOs can be used. The delay between the two output code clocks is determined by controlling the phase relationship between the two NCOs. Then, the leading clock of the two code clocks drives the code generator, and the lagging clock samples the output code stream of the code generator. Alternatively, the code clocks output by the two NCOs can drive two independent code generators. Or, only one code NCO can be used, and the phase value of the NCO can be compared with a desired phase delay as the code clock for the delay. All of these methods can yield two pseudocodes with a precise delay relationship.

[0007] However, using multiple code NCOs or multiple code generators significantly increases the consumption of digital circuit resources when multiple delayed copies need to be generated, and is also not conducive to achieving large-scale delay control. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a pseudocode delayed copy generation system. This system solves the problems of increased digital circuit resource consumption and difficulty in achieving wide-range delay control when multiple delayed copies are needed. It can simultaneously generate multiple pseudocode copies with different delays in the digital domain, achieving a large delay range and precise delay control, while consuming fewer digital circuit resources.

[0009] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0010] A pseudo-code delayed copy generation system includes a code NCO, a code generator, and a code delayed copy generator; the code NCO is used to generate a code clock signal, the code generator is used to output a code stream, and the code delayed copy generator is used to output a pseudo-code delayed copy; wherein, the code delayed copy generator includes an M-level code delay line, multiple phase comparators, and multiple output selectors, and each output selector is connected to a phase comparator.

[0011] The present invention is further configured such that: the output selector has a two-level structure, including a first-level selector and a second-level selector; the first-level selector has a structure of (M+1) inputs and 2 outputs, and the second-level selector has a structure of 2 inputs and 1 output, and the output terminal of the first-level selector is connected to the input terminal of the second-level selector.

[0012] The present invention is further configured such that: the code delay line generates M copies of C(t) with a delay of 1 to M integer chips under the control of the code clock signal, and the M copies of the pseudo-code delay are input together with C(t) into the first-level selector.

[0013] The present invention also provides a method for generating pseudocode delayed copies using a pseudocode delayed copy generation system, comprising:

[0014] Delay the target copy C(t-τ) d The delay τ in ) d Expressed as: τ d =(K+λ)τ c τ includes the integer part K and the fractional part λ. c It is the chip time width, K∈[0,M],0≤λ<1;

[0015] Convert the decimal part λ to the same unit λ as the NCO phase word. nco , that is, λ nco =λ·2 N N is the word length of NCO;

[0016] λ nco The input comparator is compared with the NCO phase word nco_phase to generate the selection signal S of the second-stage selector. When the phase represented by the NCO phase word nco_phase reaches λ... nco If the condition is met, the Kth delayed replica is selected for output; otherwise, the (K+1)th delayed replica is output. The phase comparator and the second-stage selector work together to control the delay amount, specifically the fractional part λ. The output of the second-stage selector is the desired target delayed replica C(t-τ). d ).

[0017] The present invention is further configured such that: when the integer part K of the delay is fixed, the first-level selector can be omitted, and the Kth and K+1th fixed integer chip delay copies are directly input into the second-level selector.

[0018] The present invention is further configured such that: when the resolution requirement for delay control is There are N chips, where q is an integer and 1 ≤ q < N, meaning the fractional part of the delay is represented as... p is an integer, 1 ≤ p < 2 q Then only the highest q bit of the NCO phase word and λ are needed. nco Comparison, λ nco It is also calculated in q bits, i.e., λ nco =λ·2 q =p.

[0019] The present invention has the following advantages:

[0020] 1. In the digital domain, using a code NCO and a code generator, generate multiple delayed copies of pseudocode simultaneously;

[0021] 2. Meets the requirements for large delay range and high-precision delay control;

[0022] 3. The delay range, number of output copies, and delay resolution of the pseudocode can be flexibly set according to specific needs, and the delay amount can be dynamically adjusted. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating multiple generation methods for pseudocode delay, where... Figure 1 (a) is a scheme with two independent NCOs and one code generator. Figure 1 (b) is a scheme with two independent NCOs and two independent code generators. Figure 1 (c) is a scheme with one NCO and two independent code generators;

[0024] Figure 2 This is a schematic diagram illustrating the relationship between the various functional modules of the present invention;

[0025] Figure 3 This is a detailed block diagram illustrating the principle of the delayed copy generator implementation of the present invention.

[0026] Figure 4 The timing relationship diagram for the fractional part chip delay waveform signal of this invention;

[0027] Figure 5 A schematic diagram of parallel capture by multiple correlators;

[0028] Figure 6 This is a schematic diagram illustrating the application of the present invention to the related peak sampling of the multipath MEDLL technology. Detailed Implementation

[0029] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] like Figure 1 As shown, this demonstrates a method for implementing pseudocode delay using multiple code NCOs or multiple code generators. Figure 1 (a) is a scheme with two independent NCOs and one code generator. Figure 1 (b) is a scheme with two independent NCOs and two independent code generators. Figure 1 (c) is a scheme with one NCO and two independent code generators. When there is a need for multiple pseudocode delayed copies, the corresponding NCO or code generator also needs to be increased, which will inevitably consume more resources.

[0031] This invention aims to generate multiple controllable delayed copies of pseudocode simultaneously with minimal resource consumption, such as... Figure 2 The diagram shown illustrates the functional module relationships of this invention, primarily comprising three functional modules: a code NCO, a code generator, and a code delay replica generator. The code NCO is used to generate the code clock signal, the code generator is used to output the code stream, and the code delay replica generator is used to output a pseudo-code delay replica.

[0032] The code NCO generates a code clock signal (code_clk) driven by the global clock clk. The frequency control word F0 determines the output frequency of the code NCO. Assuming the code NCO word length is N, then... The global clock frequency f0 and the code rate f are required. code The condition f0 > 2f is satisfied between them. code The phase word nco_phase, which is continuously accumulated by the code NCO, reflects the code phase value and generates a code clock signal when the accumulation overflows. The code generator can be a linear feedback shift register or RAM (Random Access Memory). Driven by each code clock signal, it outputs a continuous code stream C(t). The code stream enters the code delay copy generator to generate pseudo-code copies with different delays. The delay control value can be fixed or can be changed at any time.

[0033] The code delay copy generator includes an M-level code delay line, multiple phase comparators, and multiple output selectors. Each output selector is connected to a phase comparator and outputs a delayed pseudo-code copy. Figure 3 Simultaneously generate n delayed replicas C(t-τ) d1 ), C(t-τ) d2 ...C(t-τ) dn ).

[0034] The code delay line is structurally an M-stage cascaded shift register. The code stream C(t) output from the code generator enters the first stage of the shift register. Subsequently, the output of the previous stage becomes the input of the next stage. The entire shift register is driven by the global clock clk and enabled and controlled by the code clock signal code_clk. There is a one-chip delay between the output and input of each stage, generating a total of M integer chip delay replicas C(t-τ). c ), C(t-2τ c ...C(t-Mτ) c The number of shift register stages M determines the maximum supported delay range τ. d ∈[0, Mτ c ].

[0035] The output selector has a two-stage structure, including a first-stage selector and a second-stage selector. The first-stage selector has (M+1) inputs and two outputs. The inputs are C(t) and M integer delay copies C(t-τ). c ), C(t-2τc ...C(t-Mτ) c The second-stage selector has a structure with 2 inputs and 1 output, and the output of the first-stage selector is connected to the input of the second-stage selector. Under the control of the code clock signal, the code delay line generates M copies of C(t) with a delay of 1 to M integer chips. The M pseudo-code delay copies are input to the first-stage selector together with C(t).

[0036] A target delayed replica C(t-τ) d The delay τ d It is expressed as two parts: τ d =(K+λ)τ c Let K be the integer part and λ be the fractional part, where K ∈ [0, M], and 0 ≤ λ < 1. The value of the integer part K determines the output of the first-level selector: C(t - Kτ). c ), C(t-(K+1)τ c This refers to the Kth and (K+1)th delayed replicas. The fractional part λ determines the output of the second-stage selector: the phase word nco_phase, which is continuously accumulated by the NCO, is compared with λ in the comparator to generate the selection signal S. During the comparison, λ needs to be converted to the phase word unit λ. nco If the code NCO word length is N, then λ nco =λ·2 N When nco_phase≥λ nco The output S signal level is high, and C(t-Kτ) is selected. c Output, nco_phase<λ nco When the S signal level is low, select C(t-(K+1)τ c Output. When there is a need for multiple delayed replicas, each group (K, λ) nco The parameters control the corresponding output selector and phase comparator, such as... Figure 3 Delay τ d1 τ d2 ...τ dn It is expressed as n groups (K1, λ) nco1 (K2, λ) nco2 ...(K) n , λ ncon The parameters, the first-level selector outputs {C(t-K1τ)} respectively. c ), C(t-(K1+1)τ c )}、{C(t-K2τ c ), C(t-(K2+1)τ c )}...{C(tK n τ c ), C(t-(K) n +1)τ c)}, nco_phase and λ respectively nco1 , λ nco2 ...λ ncon The comparison generates selection signals S1, S2...S n This controls the output of the second-stage selector.

[0037] The combined function of the phase comparator and the second-stage selector is to control the delay amount that generates the fractional part λ, such as... Figure 4 The diagram illustrates the waveform relationship generated by the chip delay in the fractional part, with the high and low levels of the selection signal S controlled within C(t-Kτ). c ), C(t-(K+1)τ c Switching back and forth between the two waveforms for output, nco_phase≥λ nco The waveform is switched to C(t-Kτ) c However, when a new chip is updated, nco_phase < λ nco At that time, it is necessary to switch to C(t-(K+1)τ) c ), with lag λτ c Then switch to a new chip at a certain time.

[0038] The following explanation will be based on specific application scenarios.

[0039] In multi-correlator parallel capture applications, multiple parallel correlators are used to search simultaneously to achieve fast capture. For example... Figure 5 The diagram shows a fast acquisition module with a correlator group size of 100. `bb_s` is the carrier-stripped I / Q baseband signal, which is correlated and accumulated with pseudocode copies of different delays. During acquisition, the sampling interval for BPSK modulated signals can be set to 0.5 chips, while a sampling interval of 0.25 chips is more suitable for BOC signals. The design considers both 0.5-chip and 0.25-chip sampling intervals. Based on a 0.5-chip sampling interval, the maximum required delay is 49.5 chips, allowing for a delay line number of M = 50.

[0040] When the sampling interval is 0.5 chips, the delay between the integer and fractional parts is expressed as follows:

[0041]

[0042]

[0043] Since the sampling interval is fixed, based on the 0.25-chip requirement for higher resolution, only a 2-bit word length is needed for representation. The highest 2 bits of the NCO are then combined with 2… nco Comparison, λ nco Also calculated using 2 bits:

[0044]

[0045] When the sampling interval is 0.25 chips, the delay between the integer and fractional parts is expressed as follows:

[0046]

[0047]

[0048] In the formula, m is an integer, and 0 ≤ m ≤ 24. When calculating λ... nco At that time, it is still necessary to consider a 2-bit word length:

[0049]

[0050] Parallel acquisition using multiple correlators is a typical application requiring a large range of delays. In some applications, the delay range is not wide, but multiple pseudocode copies with precise control over the delay are needed. For example, in multipath suppression (MEDLL) technology or signal quality monitoring, the entire correlation peak needs to be sampled at certain intervals to obtain the shape of the entire correlation peak. Figure 6 As shown, the sampling interval is 0.1 chip, and there are 21 sampling points, p1, p2...p21, with a delay of τ corresponding to each of the 21 points. dk =0.1τ c Given (k-1), k = 1, 2...21, the maximum delay is 2 chips, so the number of code delay lines M = 2. Further expressing the delay as an integer and a fractional part, we have:

[0051]

[0052]

[0053] Assuming the word length of code NCO is N = 32, then:

[0054]

[0055] To further conserve resources, in practical applications, the pseudocode corresponding to points p1, p11, and p21 can be directly output from the integer delay copy on the code delay line. The remaining sampling points are divided into two groups: (p2, p3...p10) and (p12, p13...p20). The integer part K value is fixed, so the first selector can be omitted. The second-level selector corresponding to (p2, p3...p10) has fixed inputs C(t) and C(t-τ). c The second-stage selector corresponding to (p12, p13...p20) has a fixed input C(t-τ). c ), C(t-2τ c ).

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for generating a pseudo-code delayed replica by a pseudo-code delayed replica generation system, the method comprising: The pseudo-code delayed copy generation system includes a code NCO, a code generator, and a code delayed copy generator; the code NCO is used to generate a code clock signal, the code generator is used to output a code stream, and the code delayed copy generator is used to output a pseudo-code delayed copy; wherein, the code delayed copy generator includes an M-level code delay line, multiple phase comparators, and multiple output selectors, and each output selector is connected to a phase comparator. The output selector has a two-stage structure, including a first-stage selector and a second-stage selector; the first-stage selector has an M+1 input and 2 outputs, and the second-stage selector has a 2-input and 1-output structure, with the output terminal of the first-stage selector connected to the input terminal of the second-stage selector; The code delay line, under the control of the code clock signal, generates M codes with a delay of 1 to M integer chips. The M copies of the pseudocode with delayed replication are... Enter the first-level selector together; The method for generating delayed copies of pseudocode includes: Delay the target copy Delay in Expressed as: Including the integer part and decimal part , It is the chip time width. ; decimal part Converted to the same unit as the NCO phase word ,Right now , The word length is NCO; Phase word with NCO The input comparator performs a comparison, generating a selection signal for the second-stage selector. When NCO phase word The phase represented reaches When choosing the first Output the delayed copy; otherwise, output the first delayed copy. A delayed copy, wherein the combined function of the phase comparator and the second-level selector is to produce the fractional part. The delay amount control, the output of the second-level selector is the required target delay replica. .

2. The method for generating a pseudocode delayed copy using a pseudocode delayed copy generation system as described in claim 1, characterized in that: When the integer part of the delay The value is fixed; the first-level selector can be omitted, and the value can be directly entered in the second-level selector. The and the first A fixed integer number of chip delay copies.

3. The method for generating a pseudocode delayed copy using a pseudocode delayed copy generation system as described in claim 2, characterized in that: When the resolution requirement for delay control is One chip, It is an integer, and That is, the fractional part of the delay is expressed as , It is an integer. Then only the highest NCO phase word is needed. Bit and Compare, Also in accordance with Calculated using bits, i.e. .

Images