A method for fabricating a full-gate device having four ports

Abstract

The application patent relates to the technical field of integrated circuit technology, and particularly relates to a manufacturing method of a full-gate device with four ports. The manufacturing method comprises the following steps: S1, epitaxial growth: firstly, N-epitaxial layer and P+ epitaxial layer, intrinsic silicon layer are grown on N+ substrate in sequence through epitaxial growth technology; S2, etching: the N-epitaxial layer, P+ epitaxial layer and intrinsic silicon layer are etched to remove the excess part; S3, thermal oxidation: the etched part is grown with SiO2 layer through thermal oxidation process; S4, ion implantation: N- region is doped to form N-source region through ion implantation process on the intrinsic silicon layer, and N+ region is doped to form N+ source region on the N-source region; S5, re-etching: etching is performed on the region of SiO2 layer to obtain a ring-shaped groove, a rectangular groove and a cylindrical groove; S6, metal deposition: metal is deposited in the ring-shaped groove, the rectangular groove and the cylindrical groove. The method can enhance the anti-TID effect of the device, and different potentials can be applied to the source and the substrate according to the actual circuit condition.

Description

Technical Field

[0001] This invention patent relates to the field of integrated circuit technology, and in particular to a method for fabricating a four-port fully enclosed gate device. Background Technology

[0002] The total dose effect, strictly speaking, is called the "total ionizing dose effect" (TID). This occurs when a large number of radiation particles enter the interior of a semiconductor device material, ionizing the electrons outside the atomic nuclei and generating additional charges. These charges accumulate in the oxide layer within the device or induce interface states at the Si / SiO2 interface, leading to a gradual degradation of device performance and even eventual loss of function. The TID effect causes numerous adverse phenomena in transistor devices, such as threshold voltage drift, increased leakage current, and decreased mobility, resulting in chip performance degradation and malfunction.

[0003] The substrate bias effect is the effect of the potential difference V between the substrate and the source. BS When the value is not zero, it is a collective term for various effects. Generally speaking, substrate bias effects can complicate circuit design. For example, in traditional CMOS processes using P-type substrates, NMOS typically has a common substrate and is subject to substrate bias effects; while PMOS typically has an independent substrate and is not subject to substrate bias effects. Summary of the Invention

[0004] (I) Problems to be solved

[0005] It is mainly used to solve the influence of TID effect, and can apply different potentials to the source and substrate according to the actual circuit conditions, providing a method for fabricating a four-port fully enclosed gate device.

[0006] (II) Technical Solution

[0007] This invention discloses a method for fabricating a four-port fully enclosed gate device, the method comprising the following steps:

[0008] S1 epitaxial growth: First, an N- epitaxial layer and a P+ epitaxial layer are grown sequentially on an N+ substrate using epitaxial growth technology, and then an intrinsic silicon layer is grown on the P+ epitaxial layer.

[0009] S2 etching: The excess parts of the N-epitaxy layer, P+ epitaxial layer and intrinsic silicon layer are etched away, and the remaining parts are used as the N-drain region and P+ channel region.

[0010] S3 thermal oxidation: The etched portion is then subjected to a thermal oxidation process to grow a SiO2 layer;

[0011] S4 Ion Implantation: The N-source region is formed by doping the N- region on the remaining intrinsic silicon layer after etching using an ion implantation process. Then, the N-source region is doped with the N+ region to form the N+ source region.

[0012] S5 re-etching: Etching is performed in the region of the SiO2 layer to obtain annular grooves, rectangular grooves and cylindrical grooves.

[0013] S6 metal deposition: Metal is deposited in annular, rectangular, and cylindrical grooves.

[0014] As a preferred technical solution, the N-drain region, P+ channel region, N-source region, and N+ source region together constitute the active region.

[0015] As a preferred technical solution, in step S4, the doping of the N+ region is mainly carried out on the upper half of the N-source region.

[0016] As a preferred technical solution, in step S5, the first step is to etch an annular groove centered on the unetched epitaxial layer. The annular groove contains the unetched epitaxial layer portion and the SiO2 gate oxide layer, with a portion of the SiO2 isolation layer retained at the bottom. The second step is to etch a rectangular groove to the right of the annular groove, extending above the N+ substrate, completely etching away the SiO2 layer within the rectangular groove. The third step is to etch a cylindrical groove at the center of the active region. The cylindrical groove is etched up to the P+ epitaxial layer, completely etching away the SiO2 layer within the cylindrical groove.

[0017] (III) Beneficial Effects

[0018] The beneficial effects of this invention are as follows:

[0019] 1. The four-port fully enclosed gate device structure can separate the channel from the STI. After irradiation, it is only affected by the fixed holes in the gate oxide layer, thus effectively improving the resistance to TID effect.

[0020] 2. Because the channel of a four-port fully enclosed gate device is heavily doped, it can effectively suppress the attraction of fixed holes to electrons within the gate oxide layer and at the interface, thereby suppressing the threshold voltage V. T Drift and turn-off current I off The increase in [something] suppressed the TID effect.

[0021] 3. The source and substrate potentials of the structure of the present invention are controllable, and different potentials can be applied to the source and substrate according to the actual circuit conditions. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the manufacturing method of the present invention;

[0024] Figure 2 The bias effect in this invention affects the NMOS threshold voltage V. T Affects the circuit diagram;

[0025] Figure 3 The bias effect in this invention affects the PMOS threshold voltage V. T Affects the circuit diagram;

[0026] Figure 4 This is a circuit diagram showing the substrate bias effect of the load transistor in the common-source simulation circuit of this invention;

[0027] Figure 5 This is a simulation diagram of the substrate bias effect of the load transistor in the common-source simulation circuit of this invention;

[0028] Figure 6 This is a comparison of the common-source simulation circuit of this invention, in which the load transistor does not exhibit substrate bias effect;

[0029] Figure 7 This is a simulation diagram showing that the load transistor in the common-source simulation circuit of this invention does not have a substrate bias effect;

[0030] Figure 8 This is a circuit diagram showing the substrate bias effect of the input transistor in the common-gate simulation circuit of this invention;

[0031] Figure 9 This is a simulation diagram of the substrate bias effect of the input transistor in the common gate simulation circuit of this invention;

[0032] Figure 10 This is a comparison of the circuit diagram in the common-gate simulation circuit of this invention where the input transistor does not have a substrate bias effect;

[0033] Figure 11 This is a comparison of the circuit diagram in the common-gate simulation circuit of this invention where the input transistor does not have a substrate bias effect;

[0034] Figure 12 This is a transmission gate circuit diagram of the substrate bias effect in this invention.

[0035] 1-N+ substrate; 2-N- epitaxial layer; 3-P+ epitaxial layer; 4-intrinsic silicon layer; 5-N-drain region; 6-P+ channel region; 7-SiO2 layer; 8-N-source region; 9-N+ source region; 10-ring groove; 11-rectangular groove; 12-cylindrical groove; 13-active region; 14-SiO2 isolation layer; 15-SiO2 gate oxide layer. Detailed Implementation

[0036] The following description, in conjunction with the accompanying drawings, further illustrates a method for fabricating a four-port fully enclosed gate device according to the present invention.

[0037] The attached figure shows a method for fabricating a four-port fully enclosed gate device, including the following steps:

[0038] S1 Epitaxial Growth: First, an N- epitaxial layer 2 and a P+ epitaxial layer 3 are grown sequentially on an N+ substrate 1 using epitaxial growth technology, and then an intrinsic silicon layer 4 is grown on the P+ epitaxial layer 3.

[0039] S2 etching: The excess parts of N-epitaxy layer 2, P+ epitaxial layer 3 and intrinsic silicon layer 4 are etched away, and the remaining parts are used as N-drain region 5 and P+ channel region 6.

[0040] S3 thermal oxidation: The etched portion is grown with a SiO2 layer 7 through a thermal oxidation process;

[0041] S4 Ion Implantation: The N- region is doped to form the N- source region 8 on the remaining intrinsic silicon layer 4 after etching by ion implantation process, and then the N- source region 8 is doped to form the N+ source region 9.

[0042] S5 re-etching: Etching is performed in the region of SiO2 layer 7 to obtain annular groove 10, rectangular groove 11 and cylindrical groove 12.

[0043] S6 Metal Deposition: Metal is deposited in annular groove 10, rectangular groove 11 and cylindrical groove 12.

[0044] Furthermore, the N-drain region 5, the P+ channel region 6, the N-source region 8, and the N+ source region 9 together constitute the active region 13.

[0045] Furthermore, in step S4, the doping of the N+ region is mainly carried out on the upper half of the N-source region 8.

[0046] Further, in step S5, the first step is to etch an annular groove 10 centered on the unetched epitaxial layer. The annular groove 10 contains the unetched epitaxial layer portion and the SiO2 gate oxide layer 15, with a portion of the SiO2 isolation layer 14 retained at the bottom. The second step is to etch a rectangular groove 11 to the right of the annular groove 10, extending above the N+ substrate 1, completely etching the SiO2 layer 7 within the rectangular groove 11. The third step is to etch a cylindrical groove 12 at the center of the active region 13. The cylindrical groove 12 is etched up to the P+ epitaxial layer 3, and the SiO2 layer 7 within the cylindrical groove 12 is completely etched.

[0047] The present invention aims to enhance the device’s resistance to TID effect, while the structure makes the source and substrate potentials controllable, allowing different potentials to be applied to the source and substrate according to the actual circuit conditions.

[0048] To better demonstrate the advantages of this invention, please refer to the following simulation data:

[0049] 1. Substrate bias effect on threshold voltage V T The impact

[0050] a. For NMOS, an mn18 NMOS transistor is used, with a channel length of 180nm and a channel width of 1µm; V is set for the transistor. DS =0.5V,V GS =0.8V DC bias; give V BS Let x be the variable, and simulate the threshold voltage V of the NMOS transistor when x is -1V, -0.75V, -0.5V, -0.25V, and 0V. T The value of V. (To ensure that the source PN junction is not forward biased, for an N-channel MOSFET, V...) BS <0), detailed circuit diagram attached. Figure 2 .

[0051] The simulation results are as follows:

[0052]

[0053]

[0054] The simulation results show that, for NMOS, as |V BS As the value of | increases, |V T |Increase.

[0055] b. For PMOS, an mp18 NMOS transistor is used, with a channel length of 180nm and a channel width of 1µm; V is set for the transistor. DS =-0.5V,V GS = -0.8V DC bias; give VBS Let x be the variable, and simulate the threshold voltage V of the NMOS transistor when x is 0V, 0.25V, 0.5V, 0.75V, and 1V. T The value of V. (To ensure that the source PN junction is not forward biased, for a P-channel MOSFET, V...) BS >0), detailed circuit diagram attached. Figure 3 .

[0056] The simulation results are as follows:

[0057] sweep region <![CDATA[V BS ]]> <![CDATA[V T ]]> 0V 2 0V -501.44mV 250mV 2 250mV -572.567mV 500mV 2 500mV -636.796mV 750mV 2 750mV -695.988mV 1V 2 1V -751.353mV

[0058] The simulation results show that, for PMOS, as |V BS As the value of | increases, |V T |Increase.

[0059] 2. The impact of substrate bias effect on analog circuit simulation

[0060] a. In the simulation of the common-source circuit, the input transistor is an NMOS transistor and the load transistor is an NMOS transistor connected by a diode. Simulate the low-frequency gain of the load transistor with and without substrate bias effect under the same device parameters and DC bias conditions.

[0061] 1) When the load transistor exhibits substrate bias effect: The input transistor is an MN18 NMOS transistor with a channel length of 1µm and a channel width of 20µm. The signal source at the gate and source is set to a DC voltage of 530mV and an AC Magnitude of 1V. The drain is connected to the source of the load transistor and the output of the circuit, and both the substrate and source are grounded. Alternatively, the load transistor is an MN18 NMOS transistor connected as a diode, with a channel length of 180nm and a channel width of 1µm. The drain and gate are connected to a 1.8V power supply, the source is connected to the drain of the input transistor and the output of the circuit, and the substrate is grounded. Perform AC simulation on the circuit shown in the diagram below and observe the voltage gain change as the simulation frequency scans from 1Hz to 1GHz. Refer to the attached circuit diagram. Figure 4 Simulation results are attached. Figure 5 The simulation results show that the gain is approximately 3.8 times at low frequencies.

[0062] 2) When the load transistor has no substrate bias effect: The input transistor is an MN18 NMOS transistor with a channel length of 1µm and a channel width of 20µm. The signal source at the gate and source terminals is set to DC voltage = 530mV and AC Magnitude = 1V. Both the substrate and source terminals are grounded. The load transistor is an MN18 NMOS transistor connected as a diode, with a channel length of 180nm and a channel width of 1µm. The drain and gate terminals are connected to a 1.8V power supply. The source and substrate terminals are connected to the output terminals of the circuit. Perform AC simulation on the circuit built in the figure below and observe the voltage gain change when the simulation frequency scans from 1Hz to 1GHz. Refer to the attached circuit diagram. Figure 6 Simulation results are attached. Figure 7 The simulation results show that the gain is approximately 4.5 times at low frequencies.

[0063] Comparing the two simulation results, we can see that in the simulation of the common source circuit, if the device parameters and DC bias are consistent, the input transistor is an NMOS transistor and the load transistor is an NMOS transistor connected by a diode. The low-frequency gain of the load transistor with substrate bias effect is less than that without substrate bias effect.

[0064] b. In the simulation of the common gate circuit, the input transistor is an NMOS transistor and the load is a resistor. Simulate the low-frequency gain when the input transistor has a substrate bias effect and when it does not have a substrate bias effect, under the same device parameters and DC bias conditions.

[0065] 1) When the input transistor exhibits substrate bias effect: The input transistor is an MN18 NMOS transistor with a channel length of 1µm and a channel width of 10µm. The signal source at the gate is set to a DC bias of 500mV, and the signal source at the source is set to a small AC signal with an AC Magnitude of 1V. The substrate is grounded, and the drain is connected to one end of a resistor and the output of the circuit. The load is a 100K resistor. Perform an AC simulation on the following diagram and observe the voltage gain change as the simulation frequency scans from 1Hz to 1GHz. Refer to the attached circuit diagram. Figure 8 Simulation results are attached. Figure 9 .

[0066] The simulation results show that the gain is approximately 25 times at low frequencies.

[0067] 2) When there is no substrate bias effect at the input transistor: The input transistor is an MN18 NMOS transistor, with a channel length of 1µm and a channel width of 10µm. The signal source at the gate is set to a DC bias of 500mV, and the signal source at the source is set to a small AC signal of 1V Magnitude. The substrate is connected to the source, and the drain is connected to one end of a resistor and the output of the circuit. The load is a 100K resistor. Perform an AC simulation on the following diagram and observe the change in voltage gain as the simulation frequency scans from 1Hz to 1GHz. Refer to the attached circuit diagram. Figure 10 Simulation results are attached. Figure 11 .

[0068] The simulation results show that the gain is approximately 19 times at low frequencies.

[0069] Comparing the two simulation results, we can see that in the simulation of the common gate circuit, if the device parameters and DC bias are consistent, and the input transistor is an NMOS transistor with a resistor as the load, the low-frequency gain when the input transistor has a substrate bias effect is greater than the low-frequency gain when there is no substrate bias effect.

[0070] 3. The impact of substrate bias effect on digital circuit simulation

[0071] Please refer to the attached document. Figure 12 Taking transmission gate circuits as an example:

[0072] In transmission gate circuits, the source and substrate of PMOS and NMOS transistors are not connected together for two reasons: First, the turn-on condition of a MOS transistor is the generation of an electric field between the gate and the substrate, connecting the active region. If the substrate is connected to the source, the substrate bias effect is overcome, and V... T Minimum. When the transmission gate voltage approaches the gate voltage, the MOSFET may enter the subthreshold region, causing transmission gate leakage. Therefore, the substrate is connected to V. DD or V SS This facilitates the correct opening of the transmission gate.

[0073] Secondly, in terms of layout, only DNW NMOS devices can connect the substrate and source together. PMOS devices with different potentials cannot directly connect the substrate to the source, so a separate N-well is needed for this PMOS. Therefore, if the substrate is connected to the source, the layout becomes more complex.

[0074] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the concept and scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the design concept of the present invention should fall within the protection scope of the present invention. The technical content for which protection is sought in the present invention has been fully described in the claims.

Claims

1. A method for fabricating a four-port fully enclosed gate device, characterized in that: The manufacturing method includes the following steps: S1 Epitaxial growth: First, an N- epitaxial layer (2) and a P+ epitaxial layer (3) are grown sequentially on an N+ substrate (1) by epitaxial growth technology, and then an intrinsic silicon layer (4) is grown on the P+ epitaxial layer (3). S2 etching: The excess parts of the N-epitaxy layer (2), P+epitaxy layer (3) and intrinsic silicon layer (4) are etched away, and the remaining parts are used as N-drain region (5) and P+ channel region (6). S3 thermal oxidation: The etched portion is grown with a SiO2 layer through a thermal oxidation process (7). S4 Ion Implantation: The N- region is doped to form an N- source region (8) on the remaining intrinsic silicon layer (4) after etching by ion implantation process, and then the N- source region (8) is doped to form an N+ source region (9). S5 re-etching: Etching is performed in the region of the SiO2 layer (7) to obtain annular groove (10), rectangular groove (11) and cylindrical groove (12); S6 Deposit metal: Deposit metal in the annular groove (10), rectangular groove (11) and cylindrical groove (12).

2. The method for fabricating a four-port fully enclosed gate device according to claim 1, characterized in that: The N-drain region (5), P+ channel region (6), N-source region (8), and N+ source region (9) together constitute the active region (13).

3. The method for fabricating a four-port fully enclosed gate device according to claim 1, characterized in that: In step S4, the doping of the N+ region is mainly carried out on the upper half of the N-source region (8).

4. The method for fabricating a four-port fully enclosed gate device according to claim 2, characterized in that: In step S5, the first step is to etch an annular groove (10) centered on the unetched epitaxial layer. The annular groove (10) contains an unetched epitaxial layer portion and a SiO2 gate oxide layer (15), and a portion of the SiO2 isolation layer (14) is retained at the bottom. The second step is to etch a rectangular groove (11) on the right side of the annular groove (10). The rectangular groove (11) needs to be etched to the position above the N+ substrate (1) to clean the SiO2 layer (7) in the rectangular groove (11). The third step is to etch a cylindrical groove (12) in the center of the active region (13). The cylindrical groove (12) is etched up to the P+ epitaxial layer (3) and the SiO2 layer (7) in the cylindrical groove (12) is completely etched.

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