Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes a substrate. A first display area is provided with a power signal line and a first conductive layer. The power signal line is disposed on the substrate. The first conductive layer is disposed on the side of the power signal line away from the substrate and is connected in parallel with the power signal line. A second display area is provided with a first driving circuit, a second conductive layer, and a first light-emitting pixel. The first driving circuit is disposed on the substrate. The second conductive layer is disposed on the side of the first driving circuit away from the substrate. The first light-emitting pixel is disposed on the side of the second conductive layer away from the substrate. The second conductive layer is electrically connected to both the first driving circuit and the first light-emitting pixel, and the second conductive layer is disposed on the same layer as the first conductive layer. This application reduces the resistance of the power signal line, reduces current loss through the power signal line, and minimizes the voltage drop (IR-drop) of the power signal line, thereby improving the display uniformity of the display panel and reducing the power consumption of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active light-emitting devices with advantages such as high contrast, wide viewing angle, low power consumption, and thinner profile.

[0003] OLEDs can be broadly categorized into two types based on their driving method: passive driving and active driving, namely direct addressing and thin-film transistor (TFT) matrix addressing. Active driving refers to an active matrix (AM) type where each light-emitting unit is independently controlled by TFT addressing. The pixel structure, composed of the light-emitting units and TFT addressing circuits, requires a DC power supply voltage signal to be applied through the power supply (VDD) line. However, when current flows through the VDD line, the voltage drop (IR-drop) caused by the VDD line's own resistance reduces the display uniformity of the panel. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device that can improve display uniformity in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display panel having adjacent first and second display areas. The display panel includes a substrate.

[0006] The first display area includes a power signal line and a first conductive layer. The power signal line is disposed on the substrate. The first conductive layer is disposed on the side of the power signal line away from the substrate and is connected in parallel with the power signal line.

[0007] The second display area includes a first driving circuit, a second conductive layer, and a first light-emitting pixel. The first driving circuit is disposed on the substrate. The second conductive layer is disposed on the side of the first driving circuit away from the substrate. The first light-emitting pixel is disposed on the side of the second conductive layer away from the substrate.

[0008] The second conductive layer is electrically connected to the first driving circuit and the first light-emitting pixel, and the second conductive layer is disposed in the same layer as the first conductive layer.

[0009] The aforementioned display panel increases the current conduction cross-sectional area by connecting the first conductive layer and the power signal line in parallel, thereby reducing the resistance of the power signal line, reducing current loss through the power signal line, and minimizing the voltage drop (IR-drop) of the power signal line. This improves the display uniformity and reduces the power consumption of the display panel. Furthermore, by placing the first and second conductive layers in the same layer, the film structure of the original film layer (the second conductive layer) can be utilized, eliminating the need for additional film layers in the display panel. This simplifies the design and reduces manufacturing costs, while also avoiding increasing the thickness of the display panel, thus contributing to a thinner and lighter design.

[0010] In one embodiment, the first conductive layer is configured as a mesh structure.

[0011] Specifically, both the first conductive layer and the second conductive layer are transparent conductive film layers.

[0012] Specifically, the second display area includes an adjacent transition area and a transparent display area, the transition area connecting the first display area and the transparent display area. The first driving circuit is located in the transition area. The first emitting pixel is located in the transparent display area.

[0013] In this way, the light transmittance of the display panel can be improved on the one hand, and the amount of material used in the first conductive layer can be reduced to the greatest extent, thereby reducing the manufacturing cost of the display panel.

[0014] In one embodiment, the first conductive layer includes a plurality of first conductive lines and a plurality of second conductive lines, wherein the plurality of first conductive lines are spaced apart along a first direction, the plurality of second conductive lines are spaced apart along a second direction, and the plurality of first conductive lines and the plurality of second conductive lines together constitute the mesh structure.

[0015] Specifically, both the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

[0016] Specifically, the plurality of first conductive lines are uniformly arranged along the first direction, and the plurality of second conductive lines are uniformly arranged along the second direction.

[0017] In this way, on the one hand, the light transmittance of the first display area can be more uniform, and on the other hand, the display uniformity of the display panel can be improved.

[0018] In one embodiment, the second conductive layer includes a plurality of third conductive lines spaced apart along the first direction.

[0019] Specifically, the plurality of third conductive lines are evenly arranged along the first direction.

[0020] Specifically, the ratio of the upper surface area of ​​the first conductive layer to the area of ​​the first display area is a first value, and the ratio of the upper surface area of ​​the second conductive layer to the area of ​​the second display area is a second value, with the ratio of the first value to the second value being between 0.85 and 1.15.

[0021] In this way, the bonding force between the film structure of the first conductive layer and the second conductive layer and other film layers can be more uniform in the first display area and the transparent display area. This avoids the uneven bonding force between the film structure and other film layers after the display panel is subjected to stress, which could lead to the separation of the first conductive layer (or the second conductive layer) from other film layers.

[0022] In one embodiment, there are multiple power signal lines, which are spaced apart along the first direction.

[0023] The first display area further comprises a gate metal layer and a plurality of metal lines spaced apart along the second direction, wherein the metal lines are located between the substrate and the power signal lines, and the metal lines are electrically connected to the power signal lines. The gate metal layer is located between the metal lines and the substrate. The orthographic projection of the metal lines on the substrate covers at least a portion of the orthographic projection of the gate metal layer on the substrate.

[0024] This can further reduce the resistance of the power signal line, thereby further improving the display uniformity of the display panel and reducing the power consumption of the display panel.

[0025] In one embodiment, the orthographic projection of the first conductive line on the substrate covers at least a portion of the orthographic projection of the metal line on the substrate.

[0026] In one embodiment, the orthographic projection of the second conductive line on the substrate covers at least a portion of the orthographic projection of the power signal line on the substrate.

[0027] In this way, the first conductive layer can overlap with the metal layer (metal lines and power signal lines), minimizing the impact of the first conductive layer on the light transmittance of the first display area.

[0028] In one embodiment, the first conductive layer has mesh holes. The orthographic projection of the mesh holes onto the substrate covers the orthographic projection of the gate metal layer onto the substrate.

[0029] Specifically, a conductive block is disposed within the mesh, and the conductive block is electrically connected to the power signal line. The orthographic projection of the conductive block on the substrate covers the orthographic projection of the gate metal layer on the substrate.

[0030] In this way, while reducing the resistance of the power signal line, the shielding effect of the gate metal layer can also be improved.

[0031] In one embodiment, a planarization layer is provided between the power signal line and the first conductive layer, and a via is provided on the planarization layer, through which the first conductive layer and the power signal line are electrically connected.

[0032] In this way, on the one hand, it is convenient to form the first conductive layer on the side of the power signal line away from the substrate, and on the other hand, the electrical connection between the first conductive layer and the power signal line can be realized through vias.

[0033] In one embodiment, the first conductive layer includes a first portion and a second portion that are disconnected from each other.

[0034] The first portion is electrically connected to the power signal line. The second portion is configured as an antenna for the display panel.

[0035] In this way, a portion of the first conductive layer can be reused as an antenna, eliminating the need for additional film layers in the display panel, which not only reduces costs but also simplifies the design.

[0036] Secondly, this application also provides a display device, which includes the display panel described in the first aspect.

[0037] The aforementioned display device increases the current conduction cross-sectional area by connecting the first conductive layer and the power signal line in parallel, thereby reducing the resistance of the power signal line, reducing current loss through the power signal line, and minimizing the voltage drop (IR-drop) of the power signal line. This improves the display uniformity and reduces the power consumption of the display device. Furthermore, by placing the first and second conductive layers in the same layer, the film structure of the original film layer (the second conductive layer) can be utilized, eliminating the need to add an additional film layer to the display panel. This simplifies the design and reduces manufacturing costs, while also avoiding increasing the thickness of the display panel, thus contributing to a thinner and lighter display device. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating the operation of the VDD line in an OLED display panel in related technologies.

[0040] Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0041] Figure 3 for Figure 2 A cross-sectional schematic diagram of the first display area of ​​the display panel shown;

[0042] Figure 4 for Figure 2 A plan view of the second display area of ​​the display panel shown;

[0043] Figure 5 A partial structural schematic diagram of a display panel provided in another embodiment of this application;

[0044] Figure 6 for Figure 5 Schematic diagram of AA section;

[0045] Figure 7 A partial structural schematic diagram of a display panel provided in another embodiment of this application;

[0046] Figure 8 for Figure 7 Schematic diagram of the BB cross section;

[0047] Figure 9 This is a schematic diagram of the structure of the first conductive layer of a display panel provided in another embodiment of this application.

[0048] Explanation of reference numerals in the attached figures:

[0049] 100 - Display panel; 101 - First display area; 102 - Second display area; 102a - Transition area; 102b - Transparent display area; 110 - Substrate; 120 - Power signal line; 130 - First conductive layer; 130a - First portion; 130b - Second portion; 131 - First conductive line; 132 - Second conductive line; 133 - Mesh; 134 - Conductive block; 140 - First driving circuit; 150 - Second conductive layer; 151 - Third conductive line; 160 - First light-emitting pixel; 170 - Metal line; 180 - Gate metal layer; 190 - Planarization layer; 191 - Via; 200 - OLED display panel; 210 - VDD line. Detailed Implementation

[0050] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more light-emitting units present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more light-emitting units present.

[0053] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0054] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0055] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0056] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0057] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0058] As described in the background section, the OLED display panel in related technology 1 suffers from poor display uniformity. The inventors have discovered that this problem arises because: firstly, as the size of the OLED display panel increases, the resistance of the VDD line continuously increases; secondly, as the pixel density continuously increases, the linewidth of the VDD line decreases, further increasing its resistance. The combination of these factors results in a significant voltage drop across the VDD line.

[0059] Specific reference Figure 1 As shown, when the OLED display panel 200 is working, the power signal is transmitted from the beginning to the end of the VDD line 210. Due to the high resistance of the VDD line 210, the power signal attenuates during transmission. Specifically, the voltage at the beginning of the VDD line 210 is V2, and the voltage at the end of the VDD line 210 is V1, with a significant difference between V2 and V1. This results in an IR drop due to the voltage division caused by the resistance of the VDD line 210, thereby reducing the display uniformity of the OLED display panel 200.

[0060] To address this, related technology two provides a solution by increasing the power supply voltage of the VDD line, enabling all luminous pixels of the display panel to reach the saturation region, thereby avoiding the impact of the VDD line's power supply voltage drop on the display panel's display uniformity. However, this method increases the power consumption of the display panel.

[0061] For the above reasons, the present invention provides a display panel and a display device. By setting the first conductive layer and the power signal line in parallel, the conduction cross-sectional area of ​​the current is increased, thereby reducing the resistance of the power signal line, reducing the loss of current flowing through the power signal line, and minimizing the voltage drop (IR-drop) of the power signal line. This, in turn, improves the display uniformity of the display panel and reduces the power consumption of the display panel. Furthermore, by setting the first conductive layer and the second conductive layer in the same layer, the film structure of the original film layer (the second conductive layer) can be utilized, thus eliminating the need to add an additional film layer to the display panel. On the one hand, this simplifies the design and reduces manufacturing costs; on the other hand, it avoids increasing the thickness of the display panel, which is beneficial for making the display device thinner and lighter.

[0062] In a first aspect, embodiments of this application provide a display panel, which may include a flexible display panel with only display function, or a flexible display panel with touch function. The flexible display panel may, for example, be a flexible OLED (Organic Light-Emitting Diode) display panel, a flexible liquid crystal display (LCD) panel, or other types of flexible display panels.

[0063] Specifically, refer to Figure 2 , Figure 3 and Figure 4 As shown, the display panel 100 has a first display area 101 and a second display area 102 adjacent to each other. The first display area 101 may be the main display area of ​​the display panel 100, and the second display area 102 may be the sub-display area of ​​the display panel 100.

[0064] It is understood that the first display area 101 can be circular or rectangular. In one example, the first display area 101 can surround the second display area 102. In another example, the first display area 101 can surround part of the outer perimeter of the second display area 102, and the remaining side edges can be adjacent to the border of the display panel 100. This application embodiment does not limit the specific arrangement of the first display area 101 and the second display area 102.

[0065] The display panel 100 includes a substrate 110, which can be flexible polyimide (PI), rigid glass, or a thin metal sheet, etc. This embodiment will not discuss substrates 110 made of other materials in detail; those skilled in the art can select different types of materials according to actual needs.

[0066] The first display area 101 is provided with a power signal line 120 and a first conductive layer 130. The power signal line 120 is disposed on the substrate 110 and is used to transmit VDD signals. The first conductive layer 130 is disposed on the side of the power signal line 120 away from the substrate 110 and is connected in parallel with the power signal line 120.

[0067] Understandably, in one example, the first conductive layer 130 may be a planar structure that covers the first display area 101 in one whole layer. In another example, the first conductive layer 130 may include multiple conductive lines, which are spaced apart along a first direction a, or multiple conductive lines are spaced apart along a second direction b.

[0068] The second display area 102 includes a first driving circuit 140, a second conductive layer 150, and a first light-emitting pixel 160. The first driving circuit 140 is disposed on a substrate 110. The second conductive layer 150 is disposed on the side of the first driving circuit 140 away from the substrate 110. The first light-emitting pixel 160 is disposed on the side of the second conductive layer 150 away from the substrate 110. The second conductive layer 150 is electrically connected to both the first driving circuit 140 and the first light-emitting pixel 160, and is disposed on the same layer as the first conductive layer 130. Here, "disposed on the same layer" means that the first conductive layer 130 and the second conductive layer 150 are obtained by patterning the same metal layer.

[0069] The aforementioned display panel 100 increases the current conduction cross-sectional area by connecting the first conductive layer 130 and the power signal line 120 in parallel, thereby reducing the resistance of the power signal line 120, reducing current loss through the power signal line 120, and minimizing the voltage drop (IR-drop) of the power signal line 120. This improves the display uniformity of the display panel 100 and reduces its power consumption. Furthermore, by placing the first conductive layer 130 and the second conductive layer 150 in the same layer, the metal film structure of the original film layer (the second conductive layer 150) can be utilized, eliminating the need to add an additional film layer to the display panel 100. This simplifies the design and reduces manufacturing costs, while also avoiding increasing the thickness of the display panel 100, thus contributing to its thinner and lighter design.

[0070] It is understood that the first display area 101 also includes a second light-emitting pixel (not shown) and a second driving circuit (not shown), and the power signal line 120 is electrically connected to the second driving circuit.

[0071] In one embodiment, reference Figure 2 As shown, the first conductive layer 130 is constructed as a mesh structure. In this way, on the one hand, the influence of the first conductive layer 130 on the light transmittance of the display panel 100 can be reduced, thereby improving the light transmittance of the display panel 100; on the other hand, the amount of material used in the first conductive layer 130 can be reduced to the minimum, thereby reducing the manufacturing cost of the display panel 100.

[0072] It is understood that the mesh structure can be a relatively regular structure, for example, the mesh openings of the mesh structure are square, and the strips surrounding the mesh openings are all of equal width. The mesh structure can also be an irregular structure, for example, adjacent mesh openings in the mesh structure have different sizes and / or shapes. This application does not limit the specific structure of the mesh structure.

[0073] Specifically, both the first conductive layer 130 and the second conductive layer 150 are transparent conductive film layers. This minimizes the impact of the first conductive layer 130 on the light transmittance of the display panel 100, thereby improving the light transmittance of the display panel 100. For example, the transparent conductive film layer can be made of at least one of tin oxide, zinc oxide, cadmium oxide, indium oxide, indium tin oxide, zinc indium oxide, zinc gallium oxide, zinc aluminum oxide, tantalum titanium oxide, fluorine-doped tin oxide with titanium nitride, polyethyl bis(ether)thiophene, and polyethyl bis(ether)thiophene-polysulfonated styrene.

[0074] Specifically, refer to Figure 2 and Figure 4As shown, the second display area 102 includes an adjacent transition area 102a and a transparent display area 102b, with the transition area 102a connecting the first display area 101 and the transparent display area 102b. For example, the transition area 102a may surround the transparent display area 102b. A first driving circuit 140 is located in the transition area 102a. A first light-emitting pixel 160 is located in the transparent display area 102b. By placing the first driving circuit 140 in the transition area 102a, the first driving circuit 140 is avoided from being placed in the transparent display area 102b, which helps to improve the light transmittance of the transparent display area 102b.

[0075] It should be noted that the light transmittance of the transparent display area 102b is greater than that of the first display area 101 and the transition area 102a. An under-display functional device can be disposed in the transparent display area 102b of the display panel 100; this under-display functional device can be an under-display fingerprint recognition device or an under-display camera. In this embodiment, the transition area 102a is annular in shape, and the transparent display area 102b is circular in shape.

[0076] It is understandable that the transition area 102a and the transparent display area 102b can also be rectangular. In this case, there can be two transition areas 102a, which can be located on either side of the transparent display area 102b along the second direction b. It is also understandable that the transition area 102a may or may not have a display function.

[0077] In one embodiment, reference Figure 5 As shown, the first conductive layer 130 includes multiple first conductive lines 131 and multiple second conductive lines 132. The multiple first conductive lines 131 are arranged at intervals along a first direction a, and the multiple second conductive lines 132 are arranged at intervals along a second direction b. The multiple first conductive lines 131 and multiple second conductive lines 132 together form a mesh structure. In one example, both the first direction a and the second direction b are perpendicular to the thickness direction of the substrate 110, and the first direction a and the second direction b are perpendicular to each other.

[0078] In this way, on the one hand, the influence of the first conductive layer 130 on the light transmittance of the display panel 100 can be reduced, and the light transmittance of the display panel 100 can be improved; on the other hand, the amount of material used in the first conductive layer 130 can be reduced to the greatest extent, thereby reducing the manufacturing cost of the display panel 100.

[0079] Specifically, multiple first conductive lines 131 are evenly arranged along a first direction a, and multiple second conductive lines 132 are evenly arranged along a second direction b. Taking the first conductive line 131 as an example, "evenly arranged" means that the distance between any two adjacent first conductive lines 131 is equal. This arrangement can avoid uneven arrangement of the first conductive lines 131 and the second conductive lines 132. On the one hand, it can make the light transmittance of the first display area 101 more uniform, and on the other hand, it can make the resistance of different power signal lines 120 as consistent as possible, thereby improving the display uniformity of the display panel 100.

[0080] It is understandable that the line width of each first conductive line 131 can be the same, and the line width of each second conductive line 132 can also be the same, so that the grid-like first conductive layer 130 is arranged more evenly.

[0081] Furthermore, the line width of the first conductive line 131 and the line width of the second conductive line 132 can also be the same. The distance between two adjacent first conductive lines 131 can also be equal to the distance between two adjacent second conductive lines 132. This application embodiment does not limit the specific arrangement of the first conductive lines 131 and the second conductive lines 132.

[0082] In one embodiment, the second conductive layer 150 includes a plurality of third conductive lines 151 spaced apart along a first direction a. Specifically, the plurality of third conductive lines 151 are uniformly arranged along the first direction a.

[0083] It should be noted that, referring to Figure 4 As shown in this embodiment, the second conductive layer 150 may include two sets of third conductive lines 151, which are arranged at intervals along the second direction b. Each set of third conductive lines 151 includes multiple third conductive lines 151 arranged along the first direction a. Each set of third conductive lines 151 corresponds to a first driving circuit 140 on one side of the transparent display area 102b along the second direction b, and is used to electrically connect the first driving circuit 140 on that side to the corresponding first light-emitting pixel 160 in the transparent display area 102b. It can be understood that the third conductive lines 151 may also be evenly arranged along the second direction b, in which case the first driving circuit 140 is located on at least one side of the transparent display area 102b along the first direction a.

[0084] Specifically, the ratio of the upper surface area of ​​the first conductive layer 130 to the area of ​​the first display area 101 is a first value, and the ratio of the upper surface area of ​​the second conductive layer 150 to the area of ​​the second display area 102 is a second value. The ratio of the first value to the second value is between 0.85 and 1.15. Taking the first conductive layer 130 as an example, the upper surface area of ​​the first conductive layer 130 refers to the area of ​​the surface of the first conductive layer 130 away from the substrate 110. It should be noted that the ratio of the first value to the second value can be 0.85, 0.9, 0.95, 1, 1.1, or 1.15, etc.

[0085] In this way, the bonding force between the film structure of the first conductive layer 130 and the second conductive layer 150 and other film layers can be more uniform in the first display area 101 and the transparent display area 102b. This avoids the uneven bonding force between the film structure and other film layers after the display panel 100 is subjected to stress, which could lead to the separation of the first conductive layer 130 (or the second conductive layer 150) from other film layers and thus affect the stability of the film structure of the display panel 100.

[0086] In a preferred embodiment, the first value is equal to the second value. This ensures that the bonding force between the film structure of the first conductive layer 130 and the second conductive layer 150 and other film layers is approximately equal in the first display area 101 and the transparent display area 102b, thereby ensuring a more uniform bonding force between the film structure and other film layers and improving the stability of the film structure of the display panel 100.

[0087] In one embodiment, there are multiple power signal lines 120, which are arranged at intervals along a first direction a.

[0088] The first display area 101 also includes a gate metal layer 180 and a plurality of metal lines 170 spaced apart along the second direction b. The metal lines 170 are located between the substrate 110 and the power signal lines 120, and are electrically connected to the power signal lines 120. The gate metal layer 180 is located between the metal lines 170 and the substrate 110. The orthographic projection of the metal lines 170 onto the substrate 110 covers at least a portion of the orthographic projection of the gate metal layer 180 onto the substrate 110. Here, all the metal lines 170 are located in the same layer, and all the metal lines 170 constitute a metal line film layer. Therefore, "the metal lines 170 are located between the substrate 110 and the power signal lines 120" can be understood as: the metal line film layer is located between the substrate 110 and the power signal lines 120. Similarly, "the gate metal layer 180 is located between the metal lines 170 and the substrate 110" can be understood as: the gate metal layer 180 is located between the metal line film layer and the substrate 110. Here, "orthographic projection" refers to the projection along the thickness direction of the substrate 110.

[0089] It should be noted that the metal line 170 and the gate metal layer 180 can form a capacitor, with the metal line 170 acting as the upper plate and the gate metal layer 180 acting as the lower plate. By electrically connecting the metal line 170 to the power signal line 120, the upper plate of the capacitor can always be connected to a high voltage, allowing the power signal line 120 to input positive charge into the capacitor.

[0090] It is understandable that the metal wire 170 is electrically connected to the power signal line 120, which is equivalent to connecting the metal wire 170 and the power signal line 120 in parallel. This can further reduce the resistance of the power signal line 120, thereby further improving the display uniformity of the display panel 100 and reducing the power consumption of the display panel 100.

[0091] In one embodiment, the orthographic projection of the second conductive line 132 onto the substrate 110 covers at least a portion of the orthographic projection of the power signal line 120 onto the substrate 110. It is understood that the area covered by the power signal line 120 has lower light transmittance along the thickness direction of the substrate 110 (compared to an area without the power signal line 120). By aligning the second conductive line 132 with the power signal line 120 along the thickness direction of the substrate 110, the impact of the first conductive layer 130 on the light transmittance of the first display area 101 can be minimized.

[0092] In one embodiment, the orthographic projection of the first conductive line 131 onto the substrate 110 covers at least a portion of the orthographic projection of the metal line 170 onto the substrate 110. It is understood that the area covered by the metal line 170 has lower light transmittance (compared to the area without the metal line 170) along the thickness direction of the substrate 110. By aligning the first conductive line 131 and the metal line 170 along the thickness direction of the substrate 110, the impact of the first conductive layer 130 on the light transmittance of the first display area 101 can be minimized.

[0093] In one embodiment, reference Figure 7 and Figure 8 As shown, the first conductive layer 130 has mesh holes 133. The orthographic projection of the mesh holes 133 onto the substrate 110 covers the orthographic projection of the gate metal layer 180 onto the substrate 110. Specifically, a conductive block 134 is disposed within the mesh hole 133, and a gap exists between the conductive block 134 and the first conductive layer 130. The conductive block 134 is electrically connected to the power signal line 120. The orthographic projection of the conductive block 134 onto the substrate 110 covers the orthographic projection of the gate metal layer 180 onto the substrate 110.

[0094] This structure can reduce the resistance of the power signal line 120 on the one hand; on the other hand, the conductive block 134 can shield the gate metal layer 180, making the shielding effect of the gate metal layer 180 better.

[0095] It is understandable that the conductive block 134 and the first conductive layer 130 are located on the same layer, and the material of the conductive block 134 is the same as that of the first conductive layer 130.

[0096] In one embodiment, reference Figure 3 As shown, a planarization layer 190 is disposed between the power signal line 120 and the first conductive layer 130. A via 191 is disposed on the planarization layer 190, and the first conductive layer 130 and the power signal line 120 are electrically connected through the via 191. Here, all power signal lines 120 are located on the same layer, and all power signal lines 120 constitute a power signal line film layer. The phrase "a planarization layer 190 is disposed between the power signal line 120 and the first conductive layer 130" can be understood as: a planarization layer 190 is disposed between the power signal line film layer and the first conductive layer 130.

[0097] In this way, on the one hand, it is convenient to form the first conductive layer 130 on the side of the power signal line 120 away from the substrate 110, and on the other hand, the electrical connection between the first conductive layer 130 and the power signal line 120 can be realized through the via 191.

[0098] In one embodiment, reference Figure 9 As shown, the first conductive layer 130 includes a first portion 130a and a second portion 130b that are disconnected from each other. Specifically, there may be a gap between the first portion 130a and the second portion 130b, that is, the first portion 130a and the second portion 130b are separated by a gap. The first portion 130a is electrically connected to the power signal line 120. The second portion 130b is configured as an antenna for the display panel 100. In this way, a portion of the first conductive layer 130 can be reused as an antenna, thereby eliminating the need for an additional film layer in the display panel 100, reducing costs and simplifying the design.

[0099] It is understood that the shape of the antenna can be ring, rectangle, etc., and the embodiments of this application do not limit the shape and number of antennas.

[0100] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel 100 in the above embodiments.

[0101] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0102] The aforementioned display device increases the current conduction cross-sectional area by connecting the first conductive layer 130 and the power signal line 120 in parallel, thereby reducing the resistance of the power signal line 120, reducing current loss through the power signal line 120, and minimizing the voltage drop (IR-drop) of the power signal line 120. This improves the display uniformity and reduces the power consumption of the display device. Furthermore, by placing the first conductive layer 130 and the second conductive layer 150 in the same layer, the film structure of the original film layer (the second conductive layer 150) can be utilized, eliminating the need to add an additional film layer to the display panel 100 of the display device, thus reducing costs and simplifying the design.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel has an adjacent first display area and a second display area; the display panel includes a substrate; The first display area is provided with: Power signal lines are provided on the substrate; and A first conductive layer is disposed on the side of the power signal line away from the substrate and is connected in parallel with the power signal line; The second display area is provided with: A first driving circuit is disposed on the substrate; A second conductive layer is disposed on the side of the first driving circuit away from the substrate; and The first light-emitting pixel is disposed on the side of the second conductive layer away from the substrate; The second conductive layer is electrically connected to the first driving circuit and the first light-emitting pixel, and the second conductive layer is disposed on the same layer as the first conductive layer. The number of power signal lines is multiple, and the multiple power signal lines are arranged at intervals along the first direction; The first display area also includes: Multiple metal lines are spaced apart along a second direction and located between the substrate and the power signal line; the metal lines are electrically connected to the power signal line; both the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other; A gate metal layer is located between the metal line and the substrate; the orthogonal projection of the metal line on the substrate covers at least a portion of the orthogonal projection of the gate metal layer on the substrate. The first conductive layer has mesh holes; the orthographic projection of the mesh holes on the substrate covers the orthographic projection of the gate metal layer on the substrate. A conductive block is disposed within the mesh, and the conductive block is electrically connected to the power signal line; the orthogonal projection of the conductive block on the substrate covers the orthogonal projection of the gate metal layer on the substrate. The conductive block and the first conductive layer are both located on the same layer, and the material of the conductive block is the same as that of the first conductive layer.

2. The display panel according to claim 1, characterized in that, The first conductive layer is constructed as a mesh structure.

3. The display panel according to claim 2, characterized in that, Both the first conductive layer and the second conductive layer are transparent conductive film layers.

4. The display panel according to claim 2, characterized in that, The second display area includes an adjacent transition area and a transparent display area, the transition area connecting the first display area and the transparent display area; the first driving circuit is located in the transition area; and the first light-emitting pixel is located in the transparent display area.

5. The display panel according to claim 2, characterized in that, The first conductive layer includes multiple first conductive lines and multiple second conductive lines, wherein the multiple first conductive lines are arranged at intervals along the first direction, and the multiple second conductive lines are arranged at intervals along the second direction, and the multiple first conductive lines and the multiple second conductive lines together constitute the mesh structure.

6. The display panel according to claim 5, characterized in that, The plurality of first conductive lines are evenly arranged along the first direction, and the plurality of second conductive lines are evenly arranged along the second direction.

7. The display panel according to claim 5, characterized in that, The second conductive layer includes multiple third conductive lines spaced apart along the first direction.

8. The display panel according to claim 7, characterized in that, The plurality of third conductive lines are evenly arranged along the first direction.

9. The display panel according to claim 7, characterized in that, The ratio of the upper surface area of ​​the first conductive layer to the area of ​​the first display area is a first value, and the ratio of the upper surface area of ​​the second conductive layer to the area of ​​the second display area is a second value. The ratio of the first value to the second value is between 0.85 and 1.

15.

10. The display panel according to claim 5, characterized in that, The orthographic projection of the first conductive line on the substrate covers at least a portion of the orthographic projection of the metal line on the substrate. And / or, the orthographic projection of the second conductive line on the substrate covers at least a portion of the orthographic projection of the power signal line on the substrate.

11. The display panel according to any one of claims 1-10, characterized in that, A planarization layer is provided between the power signal line and the first conductive layer, and a via is provided on the planarization layer. The first conductive layer and the power signal line are electrically connected through the via.

12. The display panel according to any one of claims 1-10, characterized in that, The first conductive layer includes a first portion and a second portion that are disconnected from each other; The first part is electrically connected to the power signal line; the second part is configured as the antenna of the display panel.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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