Electronic device
By setting up electrostatic discharge buses and discharge protection components between multiple dies, the complexity of electrostatic discharge protection for input/output interfaces on the package is solved, achieving the effects of simplifying the packaging process and improving yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUI DING INT PTE LTD
- Filing Date
- 2021-05-13
- Publication Date
- 2026-05-01
AI Technical Summary
In existing technologies, the electrostatic discharge protection of input and output interfaces on electronic devices that are co-packaged with multiple chips is complex, which increases the difficulty of the packaging process and reduces the yield.
By setting up electrostatic discharge busbars and electrostatic discharge protection components between dissimilar grains, multiple electrostatic discharge paths are formed, simplifying the packaging process and improving the protection effect.
The input/output interfaces on the package provide effective electrostatic discharge protection, simplify the packaging process, and improve the yield and performance of electronic devices.
Smart Images

Figure CN115623874B_ABST
Abstract
Description
Technical Field
[0001] This application relates to an electronic device, and more particularly to an electronic device capable of electrostatic discharge protection for input / output interfaces on a package. Background Technology
[0002] Electrostatic discharge (ESD) refers to the phenomenon where positive and negative charges appear on both sides of an insulating medium, and as the charges gradually accumulate, the voltage across the insulating medium is raised to a level that exceeds the dielectric's capacity, resulting in electrical breakdown in the insulating medium and allowing current to pass through.
[0003] As chips become increasingly smaller, their tolerance to electrostatic discharge (ESD) is also decreasing. To prevent damage to the chip's circuitry during ESD, ESD protection devices are typically installed at the chip's input / output interfaces to provide a discharge path. Furthermore, with advancements in packaging technology, multiple chips can now be co-packaged. This means a single packaged chip may contain multiple chips, which may be stacked or placed side-by-side on a common substrate. Since ESD can also occur during the interconnection of the input / output interfaces between chips, ESD protection devices must be installed at these interfaces—the on-package input / output (OPIO) interfaces. However, this complicates the packaging process and may even reduce overall yield. Therefore, effectively protecting the on-package input / output interfaces from ESD has become a problem that needs to be solved. Summary of the Invention
[0004] One of the purposes of this application is to disclose an electronic device capable of electrostatic discharge protection for input / output interfaces on a package, in order to solve the above-mentioned problems.
[0005] Embodiments of the present invention provide an electronic device. The electronic device includes a first die, a second die, and a packaging structure. The first die includes a first voltage terminal, a first circuit, a second voltage terminal, a second circuit, a first electrostatic discharge bus, and a first electrostatic discharge protection device. The first voltage terminal is used to provide a first voltage. The first circuit is used to perform a first operation based on at least the first voltage. The second voltage terminal is used to provide a second voltage. The second circuit is used to perform a second operation based on at least the second voltage. The first electrostatic discharge bus is coupled to the first voltage terminal and the second voltage terminal. The first electrostatic discharge protection device is coupled between the first voltage terminal and the first electrostatic discharge bus. The second die includes a third voltage terminal, a fourth voltage terminal, a third circuit, a fourth circuit, a second electrostatic discharge bus, and a second electrostatic discharge protection device. The third voltage terminal is used to provide a third voltage. The fourth voltage terminal is used to provide a fourth voltage. The third circuit is used to perform a third operation based on at least the third voltage. The fourth circuit is used to perform a fourth operation based on at least the fourth voltage. The second electrostatic discharge bus is coupled to the third voltage terminal and the fourth voltage terminal. The second electrostatic discharge protection device is coupled between the third voltage terminal and the second electrostatic discharge bus. A packaging structure is used to encapsulate the first die and the second die, and the packaging structure includes multiple electrical contacts. The first electrostatic discharge bus and the second electrostatic discharge bus are located inside the packaging structure and are coupled to each other through a first connection structure between the first die and the second die.
[0006] The electronic device of this application can couple the electrostatic discharge bus in different chips through the connection structure between chips, thereby providing an electrostatic discharge path between multiple voltage terminals of different chips, thus enabling electrostatic discharge protection for the input and output interfaces on the package. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of the internal package of the electronic device of the present invention.
[0008] Figure 2 This is another internal schematic diagram of the electronic device of the present invention.
[0009] Figure 3 This is another internal schematic diagram of the electronic device of the present invention.
[0010] Figure 4 yes Figure 1 Circuit diagrams of the first and second chips of an electronic device.
[0011] Figure 5 This is a circuit diagram of an electronic device according to another embodiment of the present invention.
[0012] Figure 6 This is a circuit diagram of an electronic device according to another embodiment of the present invention.
[0013] Figure 7 This is a circuit diagram of an electronic device according to another embodiment of the present invention. Detailed Implementation
[0014] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of components and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or over a second feature may include, in some embodiments, the first and second features being in direct contact with each other; and may also include, in some embodiments, additional components being formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, component symbols and / or reference numerals may be reused in multiple embodiments of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.
[0015] Furthermore, the use of spatially relative terms, such as "below," "below," "lower than," "above," "above," and similar terms, may be for the convenience of describing the relationship between one component or feature depicted in the figure and one or more other components or features. These spatially relative terms, in addition to the orientation shown in the figure, also encompass various different orientations of the device during use or operation. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and these spatially relative descriptive terms should be interpreted accordingly.
[0016] While the numerical ranges and parameters used to define the broader scope of this application are approximate values, the relevant values in the specific embodiments have been presented as precisely as possible. However, any numerical value inevitably contains standard deviations due to individual test methods. Here, "approximately" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "approximately" may mean that the actual value falls within the acceptable standard error of the average, as determined by those skilled in the art to which this application pertains. It is understood that, except for experimental examples, or unless explicitly stated otherwise, all ranges, quantities, values, and percentages used herein (e.g., to describe material usage, duration, temperature, operating conditions, quantity ratios, and the like) are modified with "approximately". Therefore, unless otherwise stated, the numerical parameters disclosed in this specification and the accompanying claims are approximate values and are subject to change as needed. At a minimum, these numerical parameters should be understood as the indicated significant digits and values obtained by applying general rounding. In this context, a range of values is expressed as a distance from one endpoint to the other or between the two endpoints; unless otherwise stated, all ranges of values herein include the endpoints.
[0017] Figure 1 This is a schematic diagram of the internal package of an electronic device 100 according to an embodiment of the present invention. The electronic device 100 includes a first die 110, a second die 120, and a package structure 130A. Figure 1 In this embodiment, the electronic device 100 can be packaged using a Chip on Wafer on Substrate (CoWoS) packaging method. For example, a first die 110 and a second die 120 can be disposed side-by-side on a substrate S1. The substrate S1 has conductive lines TL, which are correspondingly coupled to microbumps MB beneath the first die 110 and the second die 120. Therefore, the first die 110 and the second die 120 can be mutually coupled through the microbumps MB and the lines TL in the substrate S1 to transmit signals. Furthermore, the package structure 130A may include multiple electrical contacts EP, so the electronic device 100 can be coupled to external circuits through the electrical contacts EP on the package structure 130A. Figure 1 The electrical contact EP may be, for example, a solder ball; however, the invention is not limited thereto. In some other embodiments, the electrical contact EP may be, for example, but not limited to, a metal pin or a metal pad.
[0018] Figure 2 This is a schematic diagram of the interior of another package of the electronic device 100. Figure 2In this package, the electronic device 100 can be packaged using a vertically stacked die method. For example, a first die 110 can be stacked on top of a second die 120, and the first die 110 can be coupled to the through-silicon vias (TSVs) in the second die 120 via microbumps (MB) below it, so that the circuits in the first die 110 and the second die 120 can transmit signals to each other within the package structure 130B.
[0019] Figure 3 This is a schematic diagram of the interior of another package of the electronic device 100. Figure 2 In this embodiment, the electronic device 100 can be packaged using a die bonding method. For example, a first die 110 can be bonded to a second die 120, and the first die 110 and the second die 120 can be coupled together by a wafer hybrid bonding (HB) structure, so that the circuits in the first die 110 and the second die 120 can transmit signals to each other.
[0020] This invention does not limit the electronic device 100 to be... Figure 1 , Figure 2 and Figure 3 In some embodiments, the electronic device 100 may also utilize other wafer-level packaging technologies to encapsulate the first die 110 and the second die 120 in the packaging structure 130C, and the first die 110 and the second die 120 may also be connected to each other through other suitable connection structures.
[0021] Figure 4 This is the circuit diagram of the first die 110 and the second die 120. In Figure 4 In this configuration, the first die 110 may include circuit 112, voltage terminals NVDDA and NVSSA, while the second die 120 may include circuit 122, voltage terminals NVDDB and NVSSB. Figure 4 In this circuit, voltage terminals NVDDA and NVSSA provide the power required for circuit 112 to operate, while voltage terminals NVDDB and NVSSB provide the power required for circuit 122 to operate. Furthermore, circuit 122 can receive the signal SIG1 generated by circuit 112 through the connection structure CS1 between the first die 110 and the second die 120. The connection structure CS1 may include, for example, but is not limited to, […]. Figure 1 Microbumps MB and lines TL in Figure 2 Microbumps (MB) and through-silicon vias (TSV) or Figure 3 The wafer mixed bonds and structure HB.
[0022] In addition, Figure 4In this configuration, voltage terminals NVDDA, NVSSA, NVDDB, and NVSSB can be coupled to corresponding electrical contacts EP1, EP2, EP3, and EP4 on package structure 130 to receive external voltage. In this case, to prevent electrostatic discharge current from flowing through circuit 112 or 122 and causing damage to circuit 112 or 122 in the event of an electrostatic discharge event at voltage terminals NVDDA, NVSSA, NVDDB, and NVSSB, the first die 110 may include electrostatic discharge protection elements ESD1, ESD2, ESD3, and ESD4 to provide a discharge path for the electrostatic discharge.
[0023] For example, voltage terminal NVDDA can be coupled to voltage terminal NVDDB through electrostatic discharge protection device ESD1 and connection structure CS2, and can be coupled to voltage terminal NVSSB through electrostatic discharge protection device ESD2 and connection structure CS3. Similarly, voltage terminal NVSSA can be coupled to voltage terminal NVDDB through electrostatic discharge protection device ESD3 and connection structure CS4, and can be coupled to voltage terminal NVSSB through electrostatic discharge protection device ESD4 and connection structure CS5. In this way, when an abnormally high voltage is generated on voltage terminal NVDDA, the electrostatic charge can be discharged to voltage terminal NVDDB through the discharge path formed by electrostatic discharge protection device ESD1 and connection structure CS2, or to voltage terminal NVSSB through the discharge path formed by electrostatic discharge protection device ESD2 and connection structure CS3.
[0024] However, in Figure 4 In this process, each electrostatic discharge (ESD) path between the first die 110 and the second die 120 must pass through the corresponding connection structures CS2 to CS5 between the first die 110 and the second die 120. In this case, if the first die 110 and the second die 120 also include more circuits and voltage terminals, more connection structures are needed to provide ESD paths, increasing the complexity of the packaging process and thus reducing the yield of the electronic device 100 or affecting its performance.
[0025] Figure 5 This is a circuit diagram of an electronic device 200 according to another embodiment of the present invention. The electronic device 200 includes a first die 210, a second die 220, and a package structure 230. In some embodiments, the first die 210 and the second die 220 may, for example, be... Figure 1 , Figure 2 , Figure 3 Other wafer-level packaging technologies can be used to co-package the components within the same package structure. It should be noted that this section is primarily intended to help the reader understand the internal circuitry and component connections of the electronic device 200; therefore, in... Figure 5The document does not specifically depict the actual circuit layer routing within the package structure; however, those skilled in the art should be able to determine the correct routing based on the provided information. Figure 5 The content is implemented in the corresponding circuit connection relationship within the adopted packaging structure.
[0026] exist Figure 5 In the first die 210, there may be a first voltage terminal NV1, a second voltage terminal NV2, a first circuit 212, a second circuit 214, a first electrostatic discharge bus B1, and a first electrostatic discharge protection device ESD1.
[0027] A first voltage terminal NV1 can provide a first voltage V1, and a first circuit 212 can perform a first operation based on at least the first voltage V1. A second voltage terminal NV2 can provide a second voltage V2, and a second circuit 214 can perform a second operation based on at least the second voltage V2. A first electrostatic discharge bus B1 can be coupled to the first voltage terminal NV1 and the second voltage terminal NV2, and a first electrostatic discharge protection device ESD1 can be coupled between the first voltage terminal NV1 and the first electrostatic discharge bus B1.
[0028] The second die 220 may include a third voltage terminal NV3, a fourth voltage terminal NV4, a third circuit 222, a fourth circuit 224, a second electrostatic discharge bus B2, and a second electrostatic discharge protection device ESD2.
[0029] The third voltage terminal NV3 can provide a third voltage V3, and the fourth voltage terminal NV4 can provide a fourth voltage V4. The third circuit 222 can perform a third operation based on at least the third voltage V3, and the fourth circuit 224 can perform a fourth operation based on at least the fourth voltage V4. The second electrostatic discharge bus B2 can be coupled to the third voltage terminal NV3 and the fourth voltage terminal NV4, and the second electrostatic discharge protection device ESD2 can be coupled between the third voltage terminal NV3 and the second electrostatic discharge bus B2.
[0030] In addition, in this embodiment, the first die 210 may also include a third electrostatic discharge protection device ESD3, which may be coupled between the second voltage terminal NV2 and the first electrostatic discharge bus B1, and the second die 220 may also include a fourth electrostatic discharge protection device ESD4, which may be coupled between the fourth voltage terminal NV4 and the second electrostatic discharge bus B2.
[0031] exist Figure 5In the package structure 230, the first electrostatic discharge bus B1 and the second electrostatic discharge bus B2 are coupled together via a first connection structure CS1 between the first die 210 and the second die 220, depending on the packaging method used. The first connection structure CS1 may include at least one of microbumps, through-silicon vias, and wafer hybrid bonding structures. Furthermore, the first circuit 212 and the third circuit 222 are coupled together via a second connection structure CS2 between the first die 210 and the second die 220, and the first circuit 212 and the third circuit 222 can transmit signals through the second connection structure CS2. The second circuit 214 and the fourth circuit 224 are coupled together via a third connection structure CS3 between the first die 210 and the second die 220, and the second circuit 214 and the fourth circuit 224 can transmit signals through the third connection structure CS3.
[0032] In this embodiment, the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 can be coupled to the electrical contacts EP1, EP2, EP3, and EP4 of the package structure 230 to receive external voltage or to an external ground terminal. In this case, if electrostatic charge accumulates on the electrical contacts due to the package structure 230 contacting an object or due to other conditions, an electrostatic discharge event may occur on the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4. At this time, since the electrostatic discharge protection devices ESD1, ESD2, ESD3, and ESD4, and the electrostatic discharge buses B1 and B2 can provide multiple discharge paths between the first voltage terminal NV1 and the second voltage terminal NV2 of the first die 210 and the third voltage terminal NV3 and the fourth voltage terminal NV4 of the second die 220, the electrostatic discharge current on the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 can be reduced or avoided from passing through the first circuit 212, the second circuit 214, the third circuit 222, and the fourth circuit 224, thereby protecting the first circuit 212, the second circuit 214, the third circuit 222, and the fourth circuit 224. In this way, electrostatic discharge protection can be provided at the input / output interface between the first die 210 and the second die 220, that is, at the on-package input / output (OPIO) interface.
[0033] Furthermore, since the electronic device 200 can couple the first voltage terminal NV1 and the second voltage terminal NV2 to the first electrostatic discharge bus B1 through the electrostatic discharge protection devices ESD1 and ESD3 respectively, and can couple the third voltage terminal NV3 and the fourth voltage terminal NV4 to the second electrostatic discharge bus B2 through the electrostatic discharge protection devices ESD2 and ESD4 respectively, multiple discharge paths can be provided only through the first connection structure CS1, without the need to set multiple connection structures between the first die 210 and the second die 220, thereby simplifying the packaging process and helping to improve the yield of the electronic device 200.
[0034] In some embodiments, the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 can provide different operating voltages greater than ground. In this case, the electrostatic discharge protection devices ESD1, ESD2, ESD3, and ESD4 may include at least one of a diode, an N-type metal-oxide-semiconductor (MOSFET), a P-type MOSFET, a bipolar junction transistor (BJT), and a silicon controlled rectifier (SCR). For example, if the first electrostatic discharge protection device ESD1 is implemented using a diode, the anode of the diode can be coupled to the first voltage terminal NV1, and the cathode of the diode can be coupled to the first electrostatic discharge bus B1. In this way, under normal circumstances, no current will flow from the first electrostatic discharge bus B1 to the first voltage terminal NV1. However, when an electrostatic discharge event occurs, and when the voltage of the first electrostatic discharge bus B1 is greater than the first voltage V1 and exceeds the breakdown voltage of the diode, the first electrostatic discharge protection device ESD1 will conduct, thus forming a discharge path between the first electrostatic discharge bus B1 and the first voltage terminal NV1. Similarly, in some embodiments, when using N-type metal-oxide-semiconductor transistors, P-type metal-oxide-semiconductor transistors, or bipolar junction transistors to implement electrostatic discharge protection devices, the N-type metal-oxide-semiconductor transistors, P-type metal-oxide-semiconductor transistors, or bipolar junction transistors can be connected, for example, in the form of diodes (diode-connected transistors).
[0035] Furthermore, in some other embodiments, the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 may be different ground terminals. In this case, the electrostatic discharge protection devices ESD1, ESD2, ESD3, and ESD4 may include at least one of two back-to-back diodes, an N-type metal-oxide-semiconductor transistor, a P-type metal-oxide-semiconductor transistor, a bipolar junction transistor, and a silicon controlled rectifier. The N-type metal-oxide-semiconductor transistor, the P-type metal-oxide-semiconductor transistor, and the bipolar junction transistor may be connected, for example, as two back-to-back diodes.
[0036] Furthermore, generally speaking, circuits 212, 214, 222, and 224 can each receive at least one set of operating voltage and ground voltage. Therefore, other voltage terminals can also be included in the first chip 210 and the second chip 220. The electronic device 200 can also be coupled to different voltage terminals through an electrostatic discharge bus in a similar manner, and the electrostatic discharge buses in the first chip 210 and the second chip 220 can be coupled together through the connection structure between the first chip 210 and the second chip 220 to provide more discharge discharge paths and achieve a more complete protection effect.
[0037] Figure 6 This is a schematic diagram of an electronic device 300 according to another embodiment of the present invention. Electronic device 300 has a similar structure to electronic device 200 and can operate based on similar principles. However, in electronic device 300, the first chip 310 may further include a fifth voltage terminal NV5, a sixth voltage terminal NV6, a third electrostatic discharge bus B3, and electrostatic discharge protection devices ESD5, ESD7, SD9, ESD10, and ESD11. The second chip 320 may further include a seventh voltage terminal NV7, an eighth voltage terminal NV8, a fourth electrostatic discharge bus B4, and electrostatic discharge protection devices ESD6, ESD8, ESD12, ESD13, and ESD14.
[0038] In the first die 310, the fifth voltage terminal NV5 can provide the fifth voltage V5 to the first circuit 312, while the sixth voltage terminal NV6 can provide the sixth voltage V6 to the second circuit 314. The third electrostatic discharge bus B3 can be coupled to the fifth voltage terminal NV5 and the sixth voltage terminal NV6. The fifth electrostatic discharge protection device ESD5 can be coupled between the fifth voltage terminal NV5 and the third electrostatic discharge bus B3, while the seventh electrostatic discharge protection device ESD7 can be coupled between the first voltage terminal NV1 and the fifth voltage terminal NV5. The ninth electrostatic discharge protection device ESD9 can be coupled between the sixth voltage terminal NV6 and the third electrostatic discharge bus B3, while the tenth electrostatic discharge protection device ESD10 can be coupled between the second voltage terminal NV2 and the sixth voltage terminal NV6. Furthermore, the eleventh electrostatic discharge protection device ESD11 can be coupled between the first electrostatic discharge bus B1 and the third electrostatic discharge bus B3.
[0039] In the second die 320, the seventh voltage terminal NV7 can provide the seventh voltage V7 to the third circuit 322, while the eighth voltage terminal NV8 can provide the eighth voltage V8 to the fourth circuit 324. The fourth electrostatic discharge bus B4 can be coupled to the seventh voltage terminal NV7 and the eighth voltage terminal NV8. The sixth electrostatic discharge protection device ESD6 can be coupled between the seventh voltage terminal NV7 and the fourth electrostatic discharge bus B4, while the eighth electrostatic discharge protection device ESD8 can be coupled between the third voltage terminal NV3 and the seventh voltage terminal NV7. Furthermore, the twelfth electrostatic discharge protection device ESD12 can be coupled between the second electrostatic discharge bus B2 and the fourth electrostatic discharge bus B4. The thirteenth electrostatic discharge protection device ESD13 can be coupled between the eighth voltage terminal NV8 and the fourth electrostatic discharge bus B4, while the fourteenth electrostatic discharge protection device ESD14 can be coupled between the fourth voltage terminal NV4 and the eighth voltage terminal NV8.
[0040] In this embodiment, the third electrostatic discharge bus B3 and the fourth electrostatic discharge bus B4 are coupled within the packaging structure of the electronic device 300 via a fourth connection structure CS4 between the first die 310 and the second die 320. Furthermore, in Figure 5 In this configuration, the fifth voltage terminal NV5, the sixth voltage terminal NV6, the seventh voltage terminal NV7, and the eighth voltage terminal NV8 can be different ground terminals, while the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 can be operating voltage terminals. That is to say, the first voltage V1 can be greater than the fifth voltage V5, the second voltage V2 can be greater than the sixth voltage V6, the third voltage V3 can be greater than the seventh voltage V7, and the fourth voltage V4 can be greater than the eighth voltage V8.
[0041] exist Figure 6 In this circuit, the electrostatic discharge buses B1, B2, B3, and B4, along with the electrostatic discharge protection devices ESD1 to ESD14, provide a discharge path between any two of the eight voltage terminals NV1 to NV8, thereby providing more comprehensive protection for the first circuit 312, the second circuit 314, the third circuit 322, and the fourth circuit 324. For example, when a significant voltage difference occurs between the second voltage terminal NV2 and the eighth voltage terminal NV8, the electrostatic discharge protection devices ESD3, ESD12, and ESD13 will conduct. Therefore, the electrostatic discharge current can flow from the second voltage terminal NV2 through the third electrostatic discharge protection device ESD3, and then through the first connection structure CS1 into the second die 320, and through the twelfth and thirteenth electrostatic discharge protection devices ESD12 and ESD13 into the eighth voltage terminal NV8. This prevents the electrostatic discharge current from passing through the second circuit 314 and the fourth circuit 324, thus avoiding damage to these circuits.
[0042] In this embodiment, the eleventh electrostatic discharge (ESD) protection device ESD11 and the twelfth ESD protection device ESD12 may include N-type metal-oxide-semiconductor (MOSFET), P-type MOSFET, or bipolar junction transistor (BJT). Furthermore, since the eleventh ESD protection device ESD11 is located between the electrostatic discharge bus BS1 and BS3, and the twelfth ESD protection device ESD12 is located between the electrostatic discharge bus BS2 and BS4, the probability of the eleventh ESD protection device ESD11 and the twelfth ESD protection device ESD12 being turned on is relatively high. Therefore, in some embodiments, the eleventh ESD protection device ESD11 and the twelfth ESD protection device ESD12 may include active ESD clamps with faster response speeds for ESD protection. The active ESD clamp may include a detection circuit and a transistor. The detection circuit may detect voltage, for example, using components such as resistors and capacitors. When the voltage exceeds a predetermined value, the transistor will be turned on immediately, thus quickly forming a discharge path for ESD.
[0043] In addition, Figure 6 In one embodiment, the first voltage terminal NV1 and the second voltage terminal NV2 can be used to provide different voltages, and therefore will be coupled to different electrical contacts on the package structure 330 to receive the corresponding power supply. However, in some embodiments, if the first voltage terminal NV1 and the second voltage terminal NV2 are used to provide the same voltage, then the first voltage terminal NV1 and the second voltage terminal NV2 can also be coupled to the same electrical contact on the package structure 330. In this case, the first voltage terminal NV1 and the second voltage terminal NV2 will actually have the same potential, so one of the electrostatic discharge protection devices ESD1 and ESD3 can be omitted. In this case, the first voltage terminal NV1 and the second voltage terminal NV2 can be coupled to the electrostatic discharge bus B1 through the same electrostatic discharge protection device. Similarly, if the third voltage terminal NV3 and the fourth voltage terminal NV4 are used to provide the same voltage and are coupled to the same electrical contact, then one of the electrostatic discharge protection components ESD2 and ESD4 can be omitted; and if the fifth voltage terminal NV5 and the sixth voltage terminal NV6 are coupled to the same electrical contact to share the same ground terminal, then one of the electrostatic discharge protection components ESD5 and ESD9 can be omitted, and so on.
[0044] Furthermore, in Figure 6In some embodiments, when no electrostatic discharge (ESD) event occurs, the first ESD bus B1, the second ESD bus B2, the third ESD bus B3, and the fourth ESD bus B4 can be in a floating state. However, in some embodiments, the ESD buses B1, B2, B3, and B4 can also be coupled to the same electrical contacts on the package structure along with some of the voltage terminals NV1 to NV8. This simplifies the design of the first die 310 and the second die 320 and further improves the ESD discharge speed inside the electronic device.
[0045] Figure 7 This is a schematic diagram of an electronic device 400 according to another embodiment of the present invention. Electronic device 400 has a similar structure to electronic device 300 and can operate based on similar principles. In electronic device 400, the first voltage terminal NV1 and the second voltage terminal NV2 can be coupled to corresponding electrical contacts EP1 and EP2 in the package structure 430 to receive the first voltage V1 and the second voltage V2 respectively. Furthermore, the fifth voltage terminal NV5 and the sixth voltage terminal NV6 can be coupled to corresponding electrical contacts EP3 and EP4 in the package structure 430 to be coupled to the corresponding ground terminals. In this case, the first electrostatic discharge bus B1 of the first die 410 can be coupled to the voltage terminal of the first voltage terminal NV1 and the second voltage terminal NV2 that provides the larger voltage to the same electrical contact in the package structure 430. Correspondingly, the third electrostatic discharge bus B3 can also be coupled to the same electrical contact in the package structure 430 with one of the fifth voltage terminal NV5 and the sixth voltage terminal NV6.
[0046] For example, if the second voltage V2 is greater than the first voltage V1, then the first electrostatic discharge bus B1 can be coupled to the electrical contact EP2 together with the second voltage terminal NV2. At this time, the third electrostatic discharge bus B3 can also be coupled to the second electrical contact EP4 of the package structure 430 with the sixth voltage terminal NV6. In this case, since the second voltage terminal NV2 and the first electrostatic discharge bus B1 are actually coupled to the same potential, no electrostatic discharge protection device is needed between them. Similarly, the sixth voltage terminal NV6 and the third electrostatic discharge bus B3 are also actually coupled to the same potential, so no electrostatic discharge protection device is needed between them either. In other words, compared to... Figure 6In the first die 310 and the first die 410, the electrostatic discharge protection components ESD3, ESD9, and ESD10 can be omitted, yet they can still provide a discharge path between the various voltage terminals when an electrostatic discharge event occurs. This prevents the circuits 412, 414, 422, and 424 in the first die 410 and the second die 420 from being damaged by the electrostatic discharge current. Furthermore, since the electrostatic discharge bus lines B1 and B3 can be coupled to the same electrical contacts as the second voltage terminal NV2 and the sixth voltage terminal NV6, respectively, a discharge path can be provided more quickly during electrostatic discharge without waiting for the electrostatic discharge protection components ESD3, ESD9, or ESD10 to be turned on.
[0047] In summary, the electronic device of the present invention can couple multiple dissimilar voltage terminals in each die to the same electrostatic discharge (ESD) bus via an ESD protection component, and couple the ESD buses in dissimilar dies together through an inter-die connection structure, thereby providing an ESD discharge path between multiple voltage terminals of dissimilar dies and achieving ESD protection. Furthermore, since the ESD bus can provide multiple ESD discharge paths between dissimilar voltage terminals, the required connection structure between dissimilar dies can be reduced, simplifying the packaging process of the electronic device and improving its yield.
[0048] The foregoing description briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to more fully understand the various forms of this disclosure. Those skilled in the art will readily recognize that this disclosure serves as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.
Claims
1. An electronic device, characterized in that, include: The first grain includes: The first voltage terminal is used to provide the first voltage; A first circuit is configured to perform a first operation based on at least the first voltage; The second voltage terminal is used to provide the second voltage; A second circuit is used to perform a second operation based on at least the second voltage; A first electrostatic discharge bus is coupled to a first voltage terminal and a second voltage terminal; and The first electrostatic discharge protection device is coupled between the first voltage terminal and the first electrostatic discharge bus. The second grain includes: The third voltage terminal is used to provide the third voltage; The fourth voltage terminal is used to provide the fourth voltage; A third circuit is configured to perform a third operation based on at least the third voltage; A fourth circuit is configured to perform a fourth operation based on at least the fourth voltage; The second electrostatic discharge bus is coupled to the third voltage terminal and the fourth voltage terminal; and The second electrostatic discharge protection device is coupled between the third voltage terminal and the second electrostatic discharge bus; and A packaging structure for encapsulating the first die and the second die, the packaging structure including a plurality of electrical contacts; The first electrostatic discharge bus and the second electrostatic discharge bus are located inside the package structure and are coupled together through a first connection structure between the first die and the second die.
2. The electronic device as claimed in claim 1, wherein: The first die and the second die are placed side by side on the same substrate, stacked on the same substrate, or glued to each other to be encapsulated together in a package structure. and The first connection structure includes at least one of microbumps, through-silicon vias, and wafer hybrid bonding structures.
3. The electronic device as claimed in claim 1, wherein: The third circuit and the first circuit are located inside the package structure and are coupled to each other through a second connection structure between the first die and the second die. The first circuit and the third circuit transmit signals through the second connection structure. and The second circuit and the fourth circuit are located inside the package structure and are coupled together through a third connection structure between the first die and the second die, and the second circuit and the fourth circuit transmit signals through the third connection structure.
4. The electronic device as claimed in claim 1, wherein: The first voltage terminal, the second voltage terminal, the third voltage terminal, and the fourth voltage terminal are different ground terminals; and The first electrostatic discharge protection device includes at least one of two diodes connected back-to-back, an N-type metal-oxide-semiconductor transistor, a P-type metal-oxide-semiconductor transistor, a bipolar junction transistor, and a silicon controlled rectifier.
5. The electronic device as claimed in claim 1, wherein: The first voltage, the second voltage, the third voltage, and the fourth voltage are different operating voltages greater than ground voltage; and The first electrostatic discharge protection device includes at least one of a diode, an N-type metal-oxide-semiconductor transistor, a P-type metal-oxide-semiconductor transistor, a bipolar junction transistor, and a silicon controlled rectifier.
6. The electronic device of claim 1, wherein the first die further comprises a third electrostatic discharge protection element coupled between the second voltage terminal and the first electrostatic discharge bus.
7. The electronic device according to any one of claims 1 to 6, wherein the second die further includes a fourth electrostatic discharge protection element coupled between the fourth voltage terminal and the second electrostatic discharge bus.
8. The electronic device of claim 1, wherein: The first grain further includes: The fifth voltage terminal is used to provide a fifth voltage to the first circuit; The sixth voltage terminal is used to provide a sixth voltage to the second circuit; The third electrostatic discharge bus is coupled to the fifth voltage terminal and the sixth voltage terminal; The fifth electrostatic discharge protection device is coupled between the fifth voltage terminal and the third electrostatic discharge bus. The second grain also includes: The seventh voltage terminal is used to provide a seventh voltage to the third circuit; The eighth voltage terminal is used to provide the eighth voltage to the fourth circuit; The fourth electrostatic discharge bus is coupled to the seventh and eighth voltage terminals; The sixth electrostatic discharge protection device is coupled between the seventh voltage terminal and the fourth electrostatic discharge bus. The third electrostatic discharge bus and the fourth electrostatic discharge bus are located inside the package structure and are coupled together through a fourth connection structure between the first die and the second die.
9. The electronic device of claim 8, wherein: The fifth voltage terminal, the sixth voltage terminal, the seventh voltage terminal, and the eighth voltage terminal are different ground terminals; and The first voltage is greater than the fifth voltage, the second voltage is greater than the sixth voltage, the third voltage is greater than the seventh voltage, and the fourth voltage is greater than the eighth voltage.
10. The electronic device of claim 9, wherein: The first die further includes a seventh electrostatic discharge protection element, coupled between the first voltage terminal and the fifth voltage terminal; and The second die also includes an eighth electrostatic discharge protection element, coupled between the third voltage terminal and the seventh voltage terminal.
11. The electronic device of claim 9, wherein: The first electrostatic discharge bus is coupled to a first electrical contact among the plurality of electrical contacts in the package structure; and The third electrostatic discharge bus is coupled to the second electrical contact among the plurality of electrical contacts in the package structure.
12. The electronic device of claim 11, wherein: The second voltage is greater than the first voltage; The first electrical contact is used to receive the second voltage supplied externally; and The second electrical contact is used to receive the sixth voltage provided externally.
13. The electronic device of claim 8, wherein: The first electrostatic discharge bus, the second electrostatic discharge bus, the third electrostatic discharge bus, and the fourth electrostatic discharge bus are in a floating state.
14. The electronic device of claim 8, wherein the first die further comprises: The third electrostatic discharge protection device is coupled between the second voltage terminal and the first electrostatic discharge bus. The ninth electrostatic discharge protection device is coupled between the sixth voltage terminal and the third electrostatic discharge bus. and The tenth electrostatic discharge pad is coupled between the second voltage terminal and the sixth voltage terminal.
15. The electronic device of claim 8, wherein: The first die also includes an eleventh electrostatic discharge protection element, coupled between the first electrostatic discharge bus and the third electrostatic discharge bus; and The second die also includes a twelfth electrostatic discharge protection device, coupled between the second electrostatic discharge bus and the fourth electrostatic discharge bus.
16. The electronic device of claim 15, wherein the eleventh electrostatic discharge protection element comprises at least one of an N-type metal-oxide-semiconductor transistor, a P-type metal-oxide-semiconductor transistor, a bipolar junction transistor, and an active electrostatic discharge clamp.
Citation Information
Patent Citations
ESD protection for 2.5d / 3d integrated circuit systems
US20130063843A1
ESD protection circuit
US6867461B1