voltage comparator

Abstract

This invention discloses a voltage comparator, comprising: a first circuit for generating a first voltage signal based on a reference voltage; a second circuit for providing a pull-up current based on an input voltage and the first voltage signal, and applying the pull-up current to a summing node; a first current source for providing a constant pull-down current, and applying the constant pull-down current to the summing node; and an output stage circuit for outputting a comparison signal based on the voltage of the summing node, wherein the voltage depends on the comparison of the pull-up current and the pull-down current. The voltage comparator disclosed in this invention uses the control terminal and the first conductive terminal of a high-voltage transistor as the input terminals of the two comparison signals, respectively, and incorporates a clamping circuit to protect the high-voltage transistor from the use of a voltage divider circuit, thereby reducing the static power consumption of the circuit.

Description

Technical Field

[0001] This invention relates to the field of high voltage comparison technology, and more specifically to a voltage comparator. Background Technology

[0002] Current portable and wearable electronic devices, such as smartphones, tablets, and smartwatches, all use rechargeable batteries to power their systems. This allows the system to operate normally when no external power source is available; when the battery is depleted, it is charged by an external power source, which then powers the system. Therefore, power management integrated circuits (PICs) are crucial for these portable electronic products.

[0003] In power management chips, it's sometimes necessary to compare two high-voltage values ​​and output the comparison result for related logic judgments. Taking the overvoltage protection circuit in a power management chip as an example, the overvoltage protection circuit needs to compare the input voltage with a reference voltage and determine whether the input voltage is overvoltage based on the comparison result. When the input signal is a high-voltage signal, the traditional approach is to divide the input signal to obtain a low-voltage signal, and then compare this low-voltage signal with the reference voltage, making a judgment based on the comparison result. The disadvantages of this approach are that the power consumption of the voltage divider circuit is proportional to the voltage value of the high-voltage signal, there is a static current between the input signal and ground, resulting in significant losses, and in some specific applications, it is undesirable for the input signal to have static current when it is lower than the reference voltage. Furthermore, the comparison rate in this method depends on the comparator's slew rate. To increase the comparison rate, a larger current needs to be used in the comparator to provide a larger slew rate, leading to increased static power consumption and hindering the implementation of low-power, high-precision power management chips. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a voltage comparator that avoids the use of a voltage divider circuit and helps to reduce circuit power consumption.

[0005] According to an embodiment of the present invention, a voltage comparator is provided, comprising: a first circuit for generating a first voltage signal based on a reference voltage; a second circuit for providing a pull-up current based on an input voltage and the first voltage signal, and applying the pull-up current to a summing node; a first current source for providing a constant pull-down current and applying the constant pull-down current to the summing node; and an output stage circuit for outputting a comparison signal based on the voltage of the summing node, wherein the voltage depends on the comparison between the pull-up current and the pull-down current.

[0006] Optionally, the first circuit includes: a first transistor, the control terminal and the first conductive terminal of the first transistor being coupled to a node on which the reference voltage is applied; a second transistor, the first conductive terminal of the second transistor being coupled to the second conductive terminal of the first transistor, the control terminal and the second conductive terminal of the second transistor being coupled to the first node, and the first voltage signal being generated at the first node; and a second current source coupled between the first node and ground.

[0007] Optionally, the second circuit includes: a third transistor, the control terminal and the first conductive terminal of the third transistor being coupled to a node on which the input voltage is applied; and a fourth transistor, the first conductive terminal of the fourth transistor being coupled to the second conductive terminal of the third transistor, the control terminal of the fourth transistor being applied with the first voltage signal, and the second conductive terminal of the fourth transistor being used to generate the pull-up current.

[0008] Optionally, the first transistor and the third transistor are low-voltage NMOS transistors, and the first transistor and the third transistor have the same size.

[0009] Optionally, the second transistor and the fourth transistor are high-voltage PMOS transistors, and the size of the second transistor is larger than the size of the fourth transistor.

[0010] Optionally, the first current source and the second current source provide the same amount of current.

[0011] Optionally, the first circuit further includes: an output node for the first voltage signal; and a fifth transistor, wherein the control terminal of the fifth transistor is coupled to the node on which the reference voltage is applied, the first conductive terminal of the fifth transistor is coupled to the first node, and the second conductive terminal of the fifth transistor is coupled to the output node for the first voltage signal.

[0012] Optionally, the first circuit further includes: a first diode, the anode of the first diode being coupled to the first node, and the cathode of the first diode being coupled to the control terminal of the fifth transistor.

[0013] Optionally, the fifth transistor is a high-voltage NMOS transistor.

[0014] Optionally, the second circuit further includes a sixth transistor coupled between a second conductive terminal of the fourth transistor and the summing node, wherein the control terminal of the sixth transistor is coupled to the node on which the reference voltage is applied.

[0015] Optionally, the sixth transistor is a high-voltage NMOS transistor.

[0016] Optionally, the second circuit further includes a second diode, the anode of which is coupled to the summing node, and the cathode of which is coupled to the control terminal of the sixth transistor.

[0017] Optionally, the second circuit further includes: an auxiliary transistor of the same type as the fourth transistor, the first conductive terminal of the auxiliary transistor being coupled to the control terminal of the fourth transistor, the control terminal of the auxiliary transistor being coupled to the node to which the input voltage is applied, and the second conductive terminal of the auxiliary transistor being to which the first voltage signal is applied.

[0018] Optionally, the voltage comparator further includes a high-voltage clamping circuit coupled to the node where the input voltage is applied and the output node of the first voltage signal. The high-voltage clamping circuit is used to clamp the first voltage signal to a set value when the input voltage is a high-voltage signal, so as to protect the transistor in the second circuit.

[0019] Optionally, the high-voltage clamping circuit includes: a Zener diode, the cathode of which is coupled to the node where the input voltage is applied; a third diode, the anode of which is coupled to the anode of the Zener diode, the cathode of which is coupled to a second node, and the second node is coupled to the output node of the first voltage signal; a normally conducting low-voltage transistor, the first conductive terminal of which is coupled to the second node, and the control terminal of which is coupled to ground; and a resistor, the first terminal of which is coupled to the second conductive terminal of the normally conducting low-voltage transistor, and the second terminal of which is coupled to ground.

[0020] Optionally, the high-voltage clamping circuit further includes a plurality of transistors connected in series between the second node and the first conductive terminal of the normally conducting low-voltage transistor, each transistor being connected as a diode.

[0021] Optionally, the output stage circuit includes: a third current source and a seventh transistor connected in series between the node where the reference voltage is applied and ground, the control terminal of the seventh transistor being coupled to the summing node, the third current source and the seventh transistor being coupled to each other through the third node, and the comparison signal being generated at the third node.

[0022] Optionally, the voltage comparator further includes a fourth diode, the anode of which is coupled to the summing node, and the cathode of which is coupled to the first terminal of the first current source.

[0023] In summary, the voltage comparator of this invention uses a high-voltage transistor to generate a pull-up current based on the comparison result between the input voltage and the reference voltage. This pull-up current is then compared with a constant pull-down current. Finally, an output stage circuit outputs a comparison signal based on the voltage of the summing node. When the input voltage is lower than the reference voltage, the high-voltage transistor is turned off, thus eliminating the quiescent current from the input voltage to ground. Therefore, the voltage comparator of this invention has no static power consumption when the input voltage is lower than the reference voltage, which is beneficial for overvoltage protection in low-power power management chips.

[0024] Furthermore, the voltage comparator of the present invention is also provided with a high-voltage clamping circuit, which can clamp the gate voltage of the high-voltage transistor to a fixed value when the input voltage is a high-voltage signal, so as to protect the high-voltage transistor.

[0025] Furthermore, the comparison rate of the voltage comparator of the present invention depends on the pull-up capability of the high-voltage transistor. When the high-voltage transistor is a PMOS transistor, its pull-up capability is very strong, which can greatly improve the comparison rate of the circuit and reduce the transmission delay.

[0026] Furthermore, the voltage comparator of the present invention has a forward-biased Schottky diode on the transmission path between the input voltage and ground. When the input voltage is a negative voltage signal, the diode can block the current path between ground and the input voltage. Therefore, the voltage comparator of the present invention can also be applied to scenarios where the input voltage is negative. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0028] Figure 1 A schematic circuit diagram of a voltage comparator according to an embodiment of the present invention is shown. Detailed Implementation

[0029] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0030] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0031] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0032] In this application, a MOS transistor includes a first conductive terminal, a second conductive terminal, and a control terminal. When the MOS transistor is in the ON state, current flows from the first conductive terminal to the second conductive terminal. The first conductive terminal, the second conductive terminal, and the control terminal of a PMOS transistor are the source, the drain, and the gate, respectively, and the first conductive terminal, the second conductive terminal, and the control terminal of an NMOS transistor are the drain, the source, and the gate, respectively.

[0033] Figure 1 A schematic circuit diagram of a voltage comparator according to an embodiment of the present invention is shown. Figure 1 As shown, the voltage comparator 100 includes circuit 110, circuit 120, current source A2, and output stage circuit 130. Circuit 110 is configured to generate a first voltage signal V1 based on a reference voltage VREF. Circuit 120 is configured to provide a pull-up current Is1 based on the input voltage VIN and the first voltage signal V1, and apply the pull-up current Is1 to a summing node 105. Current source A2 is coupled to the summing node 105 and configured to provide a constant pull-down current Is2, and apply the pull-down current to the summing node 105. Output stage circuit 130 is configured to output a comparison signal VOUT based on the voltage V2 at the summing node 105, where the voltage V2 depends on the comparison between the pull-up current Is1 and the pull-down current Is2.

[0034] In this embodiment, the circuit 110 includes transistors Mn1 and Mp1, and a current source A1. Transistors Mn1 and Mp1 are coupled (preferably in series) between nodes 102 and 103 where a reference voltage VREF is applied. Specifically, the first conductive terminal (source or drain) and the control terminal (gate) of transistor Mn1 are coupled to node 102 where the reference voltage VREF is applied, while the second conductive terminal (drain or source) of transistor Mp1 is coupled to the first conductive terminal (source or drain), and the control terminal (gate) and the second conductive terminal (drain or source) of transistor Mp1 are coupled to node 103. Further, the first voltage signal V1 is generated at node 103. The current source A1 is coupled between node 103 and ground, that is, the first terminal of current source A1 is coupled to node 103, and the second terminal is coupled to ground GND.

[0035] In this embodiment, transistor Mn1 is an N-type field-effect transistor or an NMOS transistor, and transistor Mp1 is a P-type field-effect transistor or a PMOS transistor. Furthermore, transistor Mn1 is a low-voltage N-type field-effect transistor or an NMOS transistor, and transistor Mp1 is a high-voltage P-type field-effect transistor or a PMOS transistor.

[0036] It is understood that the high-voltage transistor in this embodiment has a higher voltage withstand capability than the low-voltage transistor. For example, the low-voltage transistor is a MOS transistor with a drain-source voltage Vds ≤ 5.5V, while the high-voltage transistor can be a MOS transistor with a drain-source voltage Vds > 5.5V.

[0037] In this embodiment, the first voltage signal V1 = VREF - |Vgsp1| - |Vgsn1|, where VREF is a reference voltage generated using other circuit structures. Furthermore, this reference voltage can be generated based on the power supply voltage using other circuit structures. Even further, this reference voltage satisfies: 2.5V ≤ VREF ≤ 5.5V. Vgsp1 is the gate-source voltage of transistor Mp1, and Vgsn1 is the gate-source voltage of transistor Mn1.

[0038] In this embodiment, since the reference voltage VREF is generated under the power supply voltage, when the power is off (the power supply voltage is 0V), the reference voltage VREF is also 0V. If the input voltage VIN is a high-voltage signal at this time, the high-voltage signal may damage the transistor in circuit 110. To avoid this situation, circuit 110 further includes transistor Mn2. The control terminal (gate) of transistor Mn2 is coupled to node 102 where the reference voltage VREF is applied, the first conductive terminal (source or drain) is coupled to node 103, and the second conductive terminal (drain or source) is coupled to node 104 where the first voltage signal V1 is output.

[0039] Furthermore, transistor Mn2 is an N-type field-effect transistor or an NMOS transistor. Even further, transistor Mn2 is a high-voltage N-type field-effect transistor or an NMOS transistor.

[0040] Taking transistor Mn2 as an NMOS transistor as an example, when the reference voltage VREF is 0V, the gate-source voltage Vgsn2 of transistor Mn2 is also 0V. Therefore, transistor Mn2 is turned off. At this time, even if the input voltage VIN is a high voltage signal, the source of transistor Mn2 will not have a high voltage signal, which can protect other transistors in circuit 110.

[0041] Furthermore, circuit 110 also includes a Schottky diode D1. The anode of diode D1 is coupled to node 103, and the cathode of diode D1 is coupled to the control terminal of transistor Mn2. Diode D1 is configured to protect transistor Mn2. When the transient voltage V1 at node 103 exceeds the reference voltage VREF due to the coupling effect, diode D1 will conduct, ensuring that the transient voltage V1 at node 103 is at most VREF + 0.5V, thus protecting transistor Mn2 from damage.

[0042] In this embodiment, circuit 120 includes transistors Mn7 and Mp3. Transistors Mn7 and Mp3 are coupled (preferably in series) between node 101, where the input voltage VIN is applied, and summing node 105. Specifically, the first conductive terminal (source or drain) and control terminal (gate) of transistor Mn7 are coupled to node 101, while the second conductive terminal (drain or source) is coupled to the first conductive terminal (source or drain) of transistor Mp3. The control terminal (gate) of transistor Mp3 is coupled to the output node 104 of the first voltage signal V1. The second conductive terminal (drain or source) of transistor Mp3 is used to generate the pull-up current Is1 and apply the pull-up current Is1 to summing node 105.

[0043] In this embodiment, transistor Mn7 is an N-type field-effect transistor or an NMOS transistor, and transistor Mp3 is a P-type field-effect transistor or a PMOS transistor. Furthermore, transistor Mn7 is a low-voltage N-type field-effect transistor or an NMOS transistor, and transistor Mp3 is a high-voltage P-type field-effect transistor or a PMOS transistor.

[0044] Furthermore, in this embodiment, transistors Mn1 and Mn7 have the same dimensions, while transistor Mp1 has a larger dimension than transistor Mp3. Since transistors Mp1 and Mp3 are the same type of high-voltage transistors, and the design ensures that transistors Mp1 and Mp3 have no substrate bias effect, |Vthp1|=|Vthp3| (Vthp3 is the threshold voltage of transistor Mp3). Since transistors Mn1 and Mn7 are the same type of low-voltage transistors, and the design ensures that current sources A1 and A2 are equal current sources, Vgsn1=Vgsn7 (Vgsn7 is the gate-source voltage of transistor Mn7). When the reference voltage VREF satisfies 2.5V≤VREF≤5.5V, the design ensures that the first voltage signal V1=VREF-|Vgsp1|-|Vgsn1|>Vthn2 (where Vgsp1 is the gate-source voltage of transistor Mp1, Vgsn1 is the gate-source voltage of transistor Mn1, and Vthn2 is the turn-on threshold of transistor Mn2). Transistor Mn2 is turned on, and the gate voltage of transistor Mp3 is equal to the first voltage signal V1. At this time, the gate-source voltage of transistor Mp3 is: |Vgsp3|=VIN-Vgsn7-(VREF-Vgsn1-|Vgsp1|). The design ensures that the current of current source A1 is small. At this time, it can be assumed that |Vgsp1|=|Vthp1|. Since |Vthp1|=|Vthp3|, when the input voltage VIN is less than the reference voltage VREF, it can be deduced that |Vgsp3|<|Vthp3| (Vthp3 is the conduction threshold of transistor Mp3). Therefore, transistor Mp3 is turned off, that is, the pull-up current Is1=0. At this time, the voltage V2 on the summing node 105 is pulled down to a low level by the pull-down current Is2. The output stage circuit 130 outputs a comparison signal VOUT with a first level (low level or high level) based on the low-level voltage V2.

[0045] Furthermore, when the input voltage VIN is less than the reference voltage VREF, since transistor Mp3 is turned off, there is no static current from node 101 to ground. Therefore, the voltage comparator 100 in this embodiment has no static power consumption when the input voltage is lower than the reference voltage, which is beneficial for realizing a low-power power management chip.

[0046] When the input voltage VIN equals the reference voltage VREF, transistor Mn2 remains in the on state, therefore the gate voltages of transistors Mp1 and Mp3 are equal. Since transistors Mn1 and Mn7 have the same dimensions, and the design ensures that current sources A1 and A2 are equal, Vgsn1 = Vgsn7. At this point, transistors Mp1 and Mp3 have equal gate-source voltages. Transistors Mp1 and Mp3 form a current mirror, and transistor Mp3 generates a pull-up current Is1 by mirroring the current in transistor Mp1, i.e., the pull-up current Is1 = I...A1 / n (where n is the size ratio between transistors Mp1 and Mp3; since the size of transistor Mp1 is larger than the size of transistor Mp3, n is greater than 1), and because current sources A1 and A2 provide the same amount of current, i.e., the pull-down current Is2 = I A2 =I A1 Therefore, the pull-up current Is1 is still less than the pull-down current Is2 at this time. As a result, the voltage V2 of the summing node 105 is still pulled low, meaning that the comparison signal VOUT still has the first level.

[0047] When the input voltage VIN is greater than the reference voltage VREF, the gate-source voltage |Vgsp3| of transistor Mp3 increases, the conduction degree increases, and the pull-up current Is1 is greater than the pull-down current Is2. The summing node 105 is pulled high by the pull-up current Is1, and the output stage circuit 130 outputs a comparison signal VOUT with a second level (high level or low level) according to the high-level voltage V2.

[0048] In this embodiment, the pull-up capability of transistor Mp3 depends on the magnitude of the gate-source voltage |Vgsp3| of transistor Mp3. When the gate-source voltage |Vgsp3| is large, the pull-up capability of transistor Mp3 is strong, and the voltage V2 of summing node 105 can be pulled up quickly. Therefore, the voltage comparator 100 in this embodiment does not need to provide a large current to improve the comparison rate of the circuit, and can provide a very short propagation delay when used for overvoltage protection of power management chips.

[0049] In this embodiment, the output stage circuit 130 includes a current source A3 and a transistor Mn9. The current source A3 and the transistor Mn9 are coupled (preferably in series) between node 102, where the reference voltage VREF is applied, and ground. Specifically, the first terminal of the current source A3 is coupled to node 102, the second terminal of the current source A3 is coupled to the central node 106, the first conductive terminal (source or drain) of the transistor Mn9 is coupled to the central node 106, the control terminal of the transistor Mn9 is coupled to the summing node 105, and the second conductive terminal (drain or source) of the transistor Mn9 is coupled to ground. The comparison signal VOUT is generated at the central node 106.

[0050] In this embodiment, transistor Mn9 is an N-type field-effect transistor or an NMOS transistor. More specifically, transistor Mn9 is a low-voltage N-type field-effect transistor or an NMOS transistor. That is, when the voltage V2 at the summing node 105 is pulled low by the pull-down current Is2, transistor Mn9 is turned off, and the comparison signal VOUT at node 106 is pulled high by the current source A3 (i.e., the first level); when the voltage V2 at the summing node 105 is pulled high by the pull-up current Is1, transistor Mn9 is turned on, and the comparison signal VOUT at node 106 is pulled low by transistor Mn9 (i.e., the second level).

[0051] Furthermore, circuit 120 also includes transistor Mn8, which is coupled between the second conductive terminal (drain) of transistor Mp3 and summing node 105. Specifically, the first conductive terminal (source or drain) of transistor Mn8 is coupled to the second conductive terminal (drain) of transistor Mp3, and the second conductive terminal (drain or source) of transistor Mn8 is coupled to summing node 105. The control terminal (gate) of transistor Mn8 is coupled to node 102 where the reference voltage VREF is applied. Transistor Mn8 is configured to prevent the voltage at summing node 105 from being pulled high to the input voltage VIN, thereby protecting the low-voltage transistor Mn9 in output stage circuit 130 from damage by high-voltage signals. When the input voltage VIN is a high-voltage signal, due to the presence of transistor Mn8, the highest voltage V2 at the summing node 105 is limited by transistor Mn8 to VREF-Vgsn8 (Vgsn8 is the gate-source voltage of transistor Mn8). Since VREF-Vgsn8 is a low-voltage signal, it can protect the low-voltage transistor Mn9 from damage. Similarly, transistor Mn2 in circuit 110 can also play the same role. When the input voltage VIN is a high-voltage signal, transistor Mn2 limits the voltage V1 at node 103 to VREF-Vgsn2 (Vgsn2 is the gate-source voltage of transistor Mn2). Since VREF-Vgsn2 is a low-voltage signal, it can protect transistor Mp1 and current source A1 in circuit 110 from damage by the high-voltage signal at the input terminal.

[0052] Furthermore, in this embodiment, transistor Mn8 is an N-type field-effect transistor or an NMOS transistor. Even further, transistor Mn8 is a high-voltage N-type field-effect transistor or an NMOS transistor.

[0053] Furthermore, circuit 120 also includes a Schottky diode D3. The anode of diode D3 is coupled to the summing node 105, and the cathode is coupled to the control terminal of transistor Mn8. Diode D3 is configured to protect transistor Mn8. When the transient voltage V2 at the summing node 105 exceeds the reference voltage VREF due to the coupling effect, diode D3 will conduct, ensuring that the voltage V2 at node 105 is at most VREF+0.5V, thus protecting transistor Mn8 from damage.

[0054] Furthermore, the voltage comparator 100 in this embodiment also includes a high-voltage clamping circuit 140. The high-voltage clamping circuit 140 is coupled to the node 101 where the input voltage VIN is applied and the output node 104 of the first voltage signal V1, and is configured to clamp the first voltage signal V1 to a set value when the input voltage VIN is a high-voltage signal, so as to protect the high-voltage transistor Mp3 in the circuit 120.

[0055] Furthermore, the high-voltage clamping circuit 140 includes a Zener diode ZD1, a Schottky diode D2, a transistor Mn6, and a resistor R1. Zener diode ZD1 and Schottky diode D2 are coupled (preferably in series) between nodes 101 and 104; that is, the cathode of Zener diode ZD1 is coupled to node 101, the anode of Zener diode ZD1 is coupled to the anode of diode D2, and the anode of diode D2 is coupled to node 104. The first conductive terminal (source or drain) of transistor Mn6 is coupled to node 104, the control terminal (gate) of transistor Mn6 is coupled to ground, the second conductive terminal (drain or source) of transistor Mn6 is coupled to the first terminal of resistor R1, and the second terminal of resistor R1 is coupled to ground.

[0056] In this embodiment, transistor Mn6 is an intrinsic transistor, also known as a normally-on transistor. Furthermore, transistor Mn6 is a low-voltage N-type field-effect transistor or an NMOS transistor. Since the threshold voltage of transistor Mn6 is negative, transistor Mn6 is always on. Transistor Mn6 and resistor R1 effectively form a current source, with a current of Vthn6 / R1 (Vthn6 is the on-threshold of transistor Mn6). When the input voltage VIN is high, the current source formed by transistor Mn6 and resistor R1 turns on, generating a voltage drop across Zener diode ZD1 and Schottky diode D2. Since Zener diode ZD1 has a reverse voltage regulation capability of 5V and the forward conduction voltage of Schottky diode D2 is 0.5V, the input voltage VIN generates a voltage drop of 5.5V across Zener diode ZD1 and Schottky diode D2, which in turn pulls the first voltage signal V1 high to VIN-5.5V, making the gate-source voltage |Vgsp3| of transistor Mp3 equal to 5.5V, thus protecting transistor Mp3.

[0057] Furthermore, the high-voltage clamping circuit 140 also includes multiple transistors series-coupled between node 104 and low-voltage transistor Mn6, and each transistor is connected as a diode, for example... Figure 1 The transistors Mn3-Mn5 are used in the circuit. When the input voltage VIN is high, the current source formed by the low-voltage transistor Mn6 and the resistor R1 will also cause the gate voltage of transistor Mp3 to drop across transistors Mn3-Mn5, thus making the voltage seen at the first conductive terminal (i.e., drain) of transistor Mn6 low, protecting transistor Mn6.

[0058] It should be noted that the number of MOS diodes between the gate of transistor Mp3 and the drain of transistor Mn6 can be selected according to the magnitude of the input voltage VIN, and this invention does not impose any restrictions on this.

[0059] As can be seen from the above description, the voltage comparator 100 of this embodiment can be used simultaneously in scenarios where the input voltage VIN is a low voltage signal and a high voltage signal. In addition, the voltage comparator 100 of this embodiment can also be used in scenarios where the input voltage VIN is a negative voltage.

[0060] like Figure 1 As shown, the voltage comparator 100 also includes a Schottky diode D4 coupled between the summing node 105 and the first terminal of the current source A2. The anode of diode D4 is coupled to the summing node 105, and the cathode of diode D4 is coupled to the first terminal of the current source A2. Diode D4 is configured to block the current path from ground to the input voltage VIN when the input voltage VIN is negative. When the input voltage VIN is negative, the parasitic PN junction of transistor Mp3 conducts. Since transistor Mn8 is also conducting, without diode D4, a current would flow from ground to the input voltage VIN in the circuit, affecting the input voltage VIN. With the reverse-biased diode D4, even if the input voltage VIN is a negative signal, there is no current path from ground to the input voltage VIN.

[0061] Furthermore, the circuit 120 in this embodiment also includes an auxiliary transistor Mp2. The auxiliary transistor Mp2 is of the same type as transistor Mp3, that is, the auxiliary transistor Mp2 is also a high-voltage P-type field-effect transistor or a PMOS transistor. The first conductive terminal (source) of the auxiliary transistor Mp2 is coupled to the control terminal of transistor Mp3, and the control terminal (gate) of the auxiliary transistor Mp2 is coupled to node 101 where the input voltage VIN is applied. The second conductive terminal (drain) of the auxiliary transistor Mp2 is coupled to the first voltage signal V1. The gate voltage of transistor Mp3 is pulled down by current source A1 and a current source composed of transistor Mn6 and resistor R1. However, due to the limited pull-down capability of these two current sources, the gate voltage of transistor Mp3 is pulled down relatively slowly. Due to the presence of the high-voltage clamping circuit, when the input voltage VIN is a high-voltage signal, the gate voltage of transistor Mp3 will be pulled high, thus deviating from the first voltage generated based on the reference voltage VREF. If the input voltage VIN decreases at a relatively fast rate at this time, the gate of transistor Mp3 should also be pulled down to the first voltage generated based on the reference voltage VREF at a relatively fast rate. However, due to the limited pull-down speed at this time, the pull-down rate of the gate voltage of transistor Mp3 cannot keep up with the rate of decrease of the input voltage VIN, causing a change in the transient accuracy of the comparator. After adding the auxiliary transistor Mp2, since the gate voltage of transistor Mp3 decreases at a slower rate than the input voltage VIN, when the gate-source voltage of transistor Mp2 is greater than its own conduction threshold, transistor Mp2 is turned on, assisting in pulling down the gate voltage of transistor Mp3, thereby solving the above problem.

[0062] In summary, the voltage comparator of this invention uses a high-voltage transistor to generate a pull-up current based on the comparison result between the input voltage and the reference voltage. This pull-up current is then compared with a constant pull-down current. Finally, an output stage circuit outputs a comparison signal based on the voltage of the summing node. When the input voltage is lower than the reference voltage, the high-voltage transistor is turned off, thus eliminating the quiescent current from the input voltage to ground. Therefore, the voltage comparator of this invention has no static power consumption when the input voltage is lower than the reference voltage, which is beneficial for overvoltage protection in low-power power management chips.

[0063] Furthermore, the voltage comparator of the present invention is also provided with a high-voltage clamping circuit, which can clamp the gate voltage of the high-voltage transistor to a fixed value when the input voltage is a high-voltage signal, so as to protect the high-voltage transistor.

[0064] Furthermore, the comparison rate of the voltage comparator of the present invention depends on the pull-up capability of the high-voltage transistor. When the high-voltage transistor is a PMOS transistor, its pull-up capability is very strong, which can greatly improve the comparison rate of the circuit and reduce the transmission delay.

[0065] Furthermore, the voltage comparator of the present invention has a forward-biased Schottky diode on the transmission path between the input voltage and ground. When the input voltage is a negative voltage signal, the diode can block the current path between ground and the input voltage. Therefore, the voltage comparator of the present invention can also be applied to scenarios where the input voltage is negative.

[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A voltage comparator, comprising: A first circuit is used to generate a first voltage signal based on a reference voltage; The second circuit is used to provide a pull-up current based on the input voltage and the first voltage signal, and to apply the pull-up current to the summing node; A first current source is provided to provide a constant pull-down current and to apply the constant pull-down current to the summing node; as well as An output stage circuit is configured to output a comparison signal based on the voltage of the summing node, wherein the voltage depends on a comparison between the pull-up current and the pull-down current. The first circuit includes: a first transistor, the control terminal and the first conductive terminal of the first transistor being coupled to a node where the reference voltage is applied; a second transistor, the first conductive terminal of the second transistor being coupled to the second conductive terminal of the first transistor, the control terminal and the second conductive terminal of the second transistor being coupled to the first node, and the first voltage signal being generated at the first node; and a second current source coupled between the first node and ground. The second circuit includes: a third transistor, the control terminal and a first conductive terminal of which are coupled to a node on which the input voltage is applied; and a fourth transistor, the first conductive terminal of which is coupled to a second conductive terminal of the third transistor, the control terminal of which is applied with the first voltage signal, and the second conductive terminal of which is used to generate the pull-up current. The first transistor and the third transistor are low-voltage NMOS transistors and have the same size. The second transistor and the fourth transistor are high-voltage PMOS transistors and the size of the second transistor is larger than that of the fourth transistor.

2. The voltage comparator of claim 1, wherein, The first current source and the second current source provide the same amount of current.

3. The voltage comparator of claim 1, wherein, The first circuit further includes: The output node of the first voltage signal; and The fifth transistor has a control terminal coupled to the node where the reference voltage is applied, a first conductive terminal coupled to the first node, and a second conductive terminal coupled to the output node of the first voltage signal.

4. The voltage comparator of claim 3, wherein, The first circuit further includes: The first diode has its anode coupled to the first node and its cathode coupled to the control terminal of the fifth transistor.

5. The voltage comparator of claim 3, wherein, The fifth transistor is a high-voltage NMOS transistor.

6. The voltage comparator of claim 1, wherein, The second circuit also includes: A sixth transistor is coupled between the second conductive terminal of the fourth transistor and the summing node, and the control terminal of the sixth transistor is coupled to the node where the reference voltage is applied.

7. The voltage comparator of claim 6, wherein, The sixth transistor is a high-voltage NMOS transistor.

8. The voltage comparator of claim 6, wherein, The second circuit also includes: The second diode has its anode coupled to the summing node and its cathode coupled to the control terminal of the sixth transistor.

9. The voltage comparator of claim 1, wherein, The second circuit also includes: An auxiliary transistor of the same type as the fourth transistor is provided, wherein the first conductive terminal of the auxiliary transistor is coupled to the control terminal of the fourth transistor, the control terminal of the auxiliary transistor is coupled to the node to which the input voltage is applied, and the second conductive terminal of the auxiliary transistor is to which the first voltage signal is applied.

10. The voltage comparator of claim 1, wherein, Also includes: A high-voltage clamping circuit is coupled to the node where the input voltage is applied and the output node of the first voltage signal. The high-voltage clamping circuit is used to clamp the first voltage signal to a set value when the input voltage is a high-voltage signal, so as to protect the transistor in the second circuit.

11. The voltage comparator according to claim 10, wherein, The high-voltage clamping circuit includes: A Zener diode, wherein the cathode of the Zener diode is coupled to the node to which the input voltage is applied; The third diode has its anode coupled to the anode of the Zener diode, and its cathode coupled to the second node, which is coupled to the output node of the first voltage signal. A normally conducting low-voltage transistor, wherein a first conductive terminal of the normally conducting low-voltage transistor is coupled to a second node, and a control terminal of the normally conducting low-voltage transistor is coupled to ground; and A resistor, wherein the first terminal of the resistor is coupled to the second conductive terminal of the normally conducting low-voltage transistor, and the second terminal of the resistor is coupled to ground.

12. The voltage comparator of claim 11, wherein, The high-voltage clamping circuit also includes: Multiple transistors are connected in series between the second node and the first conductive terminal of the normally conducting low-voltage transistor, each transistor being connected as a diode.

13. The voltage comparator of claim 1, wherein, The output stage circuit includes: A third current source and a seventh transistor are connected in series between the node where the reference voltage is applied and ground. The control terminal of the seventh transistor is coupled to the summing node. The third current source and the seventh transistor are coupled to each other through the third node, and the comparison signal is generated at the third node.

14. The voltage comparator of claim 1, wherein, Also includes: A fourth diode, the anode of which is coupled to the summing node, and the cathode of which is coupled to the first terminal of the first current source.

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