A high-speed level-shifting circuit and high-voltage half-bridge driver

Abstract

The application relates to the technical field of level shifting, and discloses a high-speed level shifting circuit and a high-voltage half-bridge driver, wherein the level shifting circuit comprises a control signal generating unit, a first pull-down unit, a second pull-down unit, a first signal converting unit, a second signal converting unit and an RS flip-flop; the first signal converting unit and the second signal converting unit comprise signal output ends; in actual use, the circuit of the application has a symmetrical structure and can realize good transmission delay matching; in addition, for the first pull-down unit and the second pull-down unit of the application, the on-off of the corresponding pull-down unit can be controlled by setting a pull-down switch tube, and the position of the pull-down switch tube and a pull-down current mirror can make the gate voltage of the MOS tube in the pull-down current mirror always high, which is helpful to quickly increase the gate-source voltage of the MOS tube in the pull-down current mirror, and then the transmission delay of the level shifting circuit can be obviously reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of level shifting, in particular to a high-speed level shifting circuit and a high-voltage half-bridge driver. BACKGROUND

[0002] In modern electronic devices, integrated high-side and low-side power switches are usually implemented by parallel thin gate oxide high-voltage transistors, which can withstand high drain-source voltage up to the input power supply and low gate-source voltage below 6V.

[0003] For the gate driver of integrated high-side and low-side power switches, the level shifting circuit is an indispensable key module as a bridge between the low-voltage logic control signal and the high-voltage gate drive signal, while keeping the signal swing within the safe range of the thin gate oxide switch; the main performance indicators of the level shifting circuit are transmission delay, power consumption and noise immunity.

[0004] One of the existing technical solutions is published in IEEE Transactionson Power Electronics, named "A High-Voltage DC-DC Buck Converter With Dynamic Level Shifter for Bootstrapped High-Side Gate Driver and Diode Emulator", as shown in Figure 1

[0005] For the circuit shown in Figure 1 When used in practice, as the input voltage VSH increases, the transmission delay of the rising edge will be large due to the existence of parasitic capacitance in the circuit, and the transmission delay of the circuit shown in Figure 1 There is a great mismatch in the transmission delay of the circuit shown in SUMMARY

[0006] In view of the deficiencies in the background art, the present application provides a high-speed level shifting circuit and a high-voltage half-bridge driver, and the technical problems to be solved are that the transmission delay of the rising edge of the existing level shifting circuit is large, and the transmission delay has a great mismatch.

[0007] To solve the above technical problems, the present application provides the following technical solutions: a high-speed level shifting circuit, comprising a control signal generation unit, a first pull-down unit, a second pull-down unit, a first signal conversion unit, a second signal conversion unit and an RS flip-flop; the first signal conversion unit and the second signal conversion unit comprise a signal output end;

[0008] ​The control signal generation unit generates a first control signal and a second control signal based on an input signal VIN, the first control signal being the same as the input signal VIN, and the second control signal being opposite to the input signal VIN;

[0009] The first pull-down unit and the second pull-down unit each include a pull-down switch tube, a pull-down current mirror, a pull-down resistor, and a pull-down high-voltage transistor; an output end of the pull-down switch tube is connected to ground; the first control signal is input to a control end of the pull-down switch tube of the first pull-down unit to control the on-off of the pull-down switch tube of the first pull-down unit; the second control signal is input to a control end of the pull-down switch tube of the second pull-down unit to control the on-off of the pull-down switch tube of the second pull-down unit; an input end of the pull-down switch tube is electrically connected to an output end of a main current mirror branch of the pull-down current mirror and an output end of a slave current mirror branch of the pull-down current mirror respectively; an input end of the main current mirror branch of the pull-down current mirror is electrically connected to an output end of the pull-down high-voltage transistor; an input end of the slave current mirror of the pull-down current mirror is electrically connected to a control end of the pull-down high-voltage transistor through the pull-down resistor; and the control end of the pull-down high-voltage transistor is used for inputting a signal VDDL;

[0010] The first signal conversion unit is electrically connected to an input end of the pull-down high-voltage transistor of the first pull-down unit, and is used for pulling up an output of a signal output end of itself when the pull-down switch tube of the first pull-down unit is turned on, and pulling down an output of a signal output end of the second signal conversion unit;

[0011] The second signal conversion unit is electrically connected to an input end of the pull-down high-voltage transistor of the second pull-down unit, and is used for pulling up an output of a signal output end of itself when the pull-down switch tube of the second pull-down unit is turned on, and pulling down an output of a signal output end of the first signal conversion unit;

[0012] An R input end of the RS flip-flop is electrically connected to a signal output end of the first signal conversion unit, and an S input end of the RS flip-flop is electrically connected to a signal output end of the second signal conversion unit.

[0013] In some embodiments, the control signal generation unit includes an inverter INV1, an inverter INV2, and an inverter INV3; an input end of the inverter INV1 and an input end of the inverter INV3 are electrically connected, and are used for inputting the input signal VIN; an output end of the inverter INV1 and an input end of the inverter INV2 are electrically connected; an output end of the inverter INV2 is used for outputting the first control signal; and an output end of the inverter INV3 is used for outputting the second control signal.

[0014] In some embodiments, the pull-down current mirror comprises a MOS transistor M2 and a MOS transistor M1, a source of the MOS transistor M2 is an output end of a main current mirror branch of the pull-down current mirror, a source of the MOS transistor M1 is an output end of a slave current mirror branch of the pull-down current mirror, a drain of the MOS transistor M1 is electrically connected with a gate of the MOS transistor M1 and a gate of the MOS transistor M2 respectively, and the drain of the MOS transistor M1 is an input end of the slave current mirror branch of the pull-down current mirror, a drain of the MOS transistor M2 is an input end of the main current mirror branch of the pull-down current mirror.

[0015] In some embodiments, the first pull-down unit and the second pull-down unit further comprise a pull-down clamp transistor respectively, an input end of the pull-down clamp transistor is electrically connected with a control end of the pull-down high-voltage transistor, and an output end of the pull-down high-voltage transistor is electrically connected with a control end of the pull-down clamp transistor and an output end of the pull-down clamp transistor respectively.

[0016] In some embodiments, the first signal conversion unit and the second signal conversion unit each comprise a first current mirror, a second current mirror, a third current mirror and a conversion switch transistor, for one of the first signal conversion unit and the second signal conversion unit, a slave current mirror branch of the first current mirror is electrically connected with an input end of the corresponding pull-down high-voltage transistor, a main current mirror branch of the first current mirror is electrically connected with a slave current mirror branch of the second current mirror and a control end of the conversion switch transistor of itself respectively, a main current mirror branch of the second current mirror is electrically connected with a slave current mirror branch of the third current mirror, a main branch of the third current mirror is electrically connected with an input end of the conversion switch transistor of the other signal conversion unit, and an output end of the conversion switch transistor is used for connecting the voltage VS.

[0017] In some embodiments, the main current mirror branch of the first current mirror comprises a MOS transistor M8, and the slave current mirror branch of the first current mirror comprises a MOS transistor M7; the main current mirror branch of the second current mirror comprises a MOS transistor M10, and the slave current mirror branch of the second current mirror comprises a MOS transistor M9; the main current mirror branch of the third current mirror comprises a MOS transistor M17, and the slave current mirror branch of the third current mirror comprises a MOS transistor M11.

[0018] The source of the MOS transistor M17 is electrically connected with the source of the MOS transistor M8, the source of the MOS transistor M11 and the source of the MOS transistor M17, for inputting the voltage VBST; the gate of the MOS transistor M7 is electrically connected with the drain of the MOS transistor M7, the input of the pull-down high-voltage transistor and the gate of the MOS transistor M8, the drain of the MOS transistor M8 is electrically connected with the drain of the MOS transistor M9, the gate of the MOS transistor M9, the gate of the MOS transistor M10 and the control terminal of the self conversion switch transistor, the source of the MOS transistor M9 and the source of the MOS transistor M10 are for inputting the voltage VS; the drain of the MOS transistor M10 is electrically connected with the drain of the MOS transistor M11, the gate of the MOS transistor M11 and the gate of the MOS transistor M17, the drain of the MOS transistor M17 is the signal output terminal of the self signal conversion unit, and is electrically connected with the input terminal of the conversion switch transistor of the other signal conversion unit.

[0019] In some embodiments, the application further comprises the MOS transistor M21, the MOS transistor M22, the MOS transistor M23 and the MOS transistor M24, the source of the MOS transistor M21 and the source of the MOS transistor M23 are for inputting the voltage VBST, the gate of the MOS transistor M21 is electrically connected with the gate of the MOS transistor M24, the drain of the MOS transistor M24 and the input of the pull-down high-voltage transistor of the second pull-down unit, the gate of the MOS transistor M23 is electrically connected with the gate of the MOS transistor M22, the drain of the MOS transistor M22 and the input of the pull-down high-voltage transistor of the first pull-down unit, the drain of the MOS transistor M21 is electrically connected with the source of the MOS transistor M22, and the drain of the MOS transistor M23 is electrically connected with the source of the MOS transistor M24.

[0020] In some embodiments, the first signal conversion unit and the second signal conversion unit further comprise a conversion clamping transistor, the input of the conversion clamping transistor is electrically connected with the gate of the MOS transistor M7 of the first current mirror, and the control terminal and the output of the conversion clamping transistor are for inputting the voltage VS.

[0021] In some embodiments, the signal output terminal of the first signal conversion unit and the signal output terminal of the second signal conversion unit are electrically connected with the RS flip-flop through a common-mode noise suppression unit.

[0022] In certain embodiments, the common mode noise suppression unit comprises an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; the input terminals of the inverter INV4 are electrically connected with the signal output terminal of the first signal conversion unit and the first input terminal of the AND gate AND2 respectively, and the output terminal of the inverter INV4 is electrically connected with the first input terminal of the AND gate AND1; the input terminals of the inverter INV5 are electrically connected with the signal output terminal of the second signal conversion unit and the second input terminal of the AND gate AND1 respectively, and the output terminal of the inverter INV5 is electrically connected with the second input terminal of the AND gate AND2; the output terminal of the AND gate AND1 is electrically connected with the R input terminal of the RS flip-flop, and the output terminal of the AND gate AND2 is electrically connected with the S input terminal of the RS flip-flop.

[0023] Compared with the prior art, the present application has the following beneficial effects:

[0024] Firstly, the circuit of the present application is of symmetrical structure, and good transmission delay matching can be achieved;

[0025] Secondly, for the first pull-down unit and the second pull-down unit of the present application, by setting the pull-down switch tube, it can be controlled whether the corresponding pull-down unit is turned on, and by setting the position of the pull-down switch tube and the pull-down current mirror, the gate voltage of the MOS tube in the pull-down current mirror can be always high, which is helpful to quickly increase the gate-source voltage of the MOS tube in the pull-down current mirror, and thus the transmission delay of the level shifting circuit can be significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a circuit diagram of the prior art level shifting circuit;

[0027] Figure 2 is a circuit diagram of the level shifting circuit of the present application in embodiment one;

[0028] Figure 3 is a structure schematic diagram of the high-voltage half-bridge driver of the present application in embodiment two. DETAILED DESCRIPTION

[0029] The present application will now be further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, and only illustrate the basic structure of the present application in a schematic manner, and thus only show the components related to the present application.

[0030] As shown in Figure 2 Fig. 1, a high-speed level shifting circuit comprises a control signal generation unit 1, a first pull-down unit 2, a second pull-down unit 3, a first signal conversion unit 4, a second signal conversion unit 5 and an RS flip-flop 6; the first signal conversion unit 4 and the second signal conversion unit 5 comprise signal output terminals;

[0031] The control signal generating unit 1 generates a first control signal CON1 and a second control signal CON2 based on an input signal VIN, the first control signal CON1 being the same as the input signal VIN, and the second control signal CON2 being opposite to the input signal VIN;

[0032] In the embodiment, the first pull-down unit 2 and the second pull-down unit 3 have the same circuit, and the first pull-down unit 2 is taken as an example. The first pull-down unit 2 includes a pull-down switch tube M5, a pull-down current mirror 20, a pull-down resistor R1 and a pull-down high-voltage transistor MHV1. The output end of the pull-down switch tube M5 is connected to the ground. The first control signal CON1 is input to the control end of the pull-down switch tube M5 of the first pull-down unit 2, so as to control the on-off of the pull-down switch tube M5 of the first pull-down unit 2. The second control signal CON2 is input to the control end of the pull-down switch tube M6 of the second pull-down unit 3, so as to control the on-off of the pull-down switch tube M6 of the second pull-down unit 3.

[0033] Continuing to take the first pull-down unit 2 as an example, the input end of the pull-down switch tube M5 is electrically connected to the output end of the main current mirror branch of the pull-down current mirror 20 and the output end of the slave current mirror branch of the pull-down current mirror, respectively. The input end of the main current mirror branch of the pull-down current mirror is electrically connected to the output end of the pull-down high-voltage transistor MHV1. The input end of the slave current mirror of the pull-down current mirror is electrically connected to the control end of the pull-down high-voltage transistor MHV1 through the pull-down resistor R1. The control end of the pull-down high-voltage transistor MHV1 is used for inputting the signal VDDL.

[0034] The first signal conversion unit 4 is electrically connected to the input end of the pull-down high-voltage transistor MHV1 of the first pull-down unit 2, and is used for pulling up the output of the signal output end of itself when the pull-down switch tube M5 of the first pull-down unit 2 is turned on, and pulling down the output of the signal output end of the second signal conversion unit 5.

[0035] The second signal conversion unit 5 is electrically connected to the input end of the pull-down high-voltage transistor MHV2 of the second pull-down unit 3, and is used for pulling up the output of the signal output end of itself when the pull-down switch tube M6 of the second pull-down unit 3 is turned on, and pulling down the output of the signal output end of the first signal conversion unit 4.

[0036] The R input end of the RS flip-flop 6 is electrically connected to the signal output end of the first signal conversion unit. The S input end of the RS flip-flop is electrically connected to the signal output end of the second signal conversion unit.

[0037] Specifically, in the embodiment, as shown in FIG. 1, the control signal generating unit 1 includes a first control signal generating unit 10 and a second control signal generating unit 20. Figure 2As shown, the control signal generation unit 1 comprises inverters INV1, INV2 and INV3; the input end of the inverter INV1 and the input end of the inverter INV3 are electrically connected for inputting the input signal VIN, the output end of the inverter INV1 and the input end of the inverter INV2 are electrically connected, the output end of the inverter INV2 is used for outputting the first control signal CON1, and the output end of the inverter INV3 is used for outputting the second control signal CON2.

[0038] In addition, in the Figure 1 , taking the first pull-down unit 2 as an example, the pull-down current mirror 20 of the first pull-down unit 2 comprises MOS tubes M2 and M1, the source of the MOS tube M2 is the output end of the main current mirror branch of the pull-down current mirror, the source of the MOS tube M1 is the output end of the slave current mirror branch of the pull-down current mirror, the drain of the MOS tube M1 is electrically connected with the gate of the MOS tube M1 and the gate of the MOS tube M2, and is the input end of the slave current mirror branch of the pull-down current mirror, and the drain of the MOS tube M2 is the input end of the main current mirror branch of the pull-down current mirror.

[0039] In the Figure 1 , the pull-down high-voltage transistor MHV1, the MOS tube M1, the MOS tube M2 and the MOS tube M5 are all NMOS tubes. For the NMOS tube, the gate of the NMOS tube is the control end of itself, the source of the NMOS tube is the output end of itself, and the drain of the NMOS tube is the input end of itself.

[0040] In actual use, first, the circuit as a whole is a symmetrical structure, which can realize good transmission delay matching;

[0041] Secondly, for the first pull-down unit 2 and the second pull-down unit 3 of the present application, by setting the pull-down switch tube, whether the corresponding pull-down unit is turned on can be controlled, and by setting the position of the pull-down switch tube and the pull-down current mirror, the gate voltage of the MOS tube in the pull-down current mirror can be always high, which helps to quickly increase the gate-source voltage of the MOS tube in the pull-down current mirror, and thus the transmission delay of the level shift circuit can be significantly reduced.

[0042] In addition, in the Figure 2 , as shown, the first pull-down unit 2 and the second pull-down unit 3 further comprise pull-down clamping transistors. Taking the first pull-down unit 2 as an example, the input end of the pull-down clamping transistor MQ1 of the first pull-down unit 2 is electrically connected with the control end of the pull-down high-voltage transistor MHV1, and the output end of the pull-down high-voltage transistor MHV1 is electrically connected with the control end of the pull-down clamping transistor MQ1 and the output end of the pull-down clamping transistor MQ1 respectively. Among them, the pull-down clamping transistor MQ1 is also an NMOS tube.

[0043] Taking the first pull-down unit 2 as an example, in actual use, the gate-source voltage of the pull-down high-voltage transistor MHV1 can be clamped by the pull-down clamping transistor MQ1 to prevent the pull-down high-voltage transistor MHV1 from being broken down.

[0044] In this embodiment, the circuits of the first signal conversion unit 4 and the second signal conversion unit 5 are the same and both include a first current mirror, a second current mirror, a third current mirror and a conversion switch tube; for the first signal conversion unit 4 in the first signal conversion unit 4 and the second signal conversion unit 5, the slave current mirror branch of the first current mirror 40 is electrically connected to the input end of the corresponding pull-down high-voltage transistor MHV1, the main current mirror branch of the first current mirror 40 is electrically connected to the slave current mirror branch of the second current mirror 41 and the control end of its own conversion switch tube M18, respectively, the main current mirror branch of the second current mirror 41 is electrically connected to the slave current mirror branch of the third current mirror 42, the main branch of the third current mirror 42 is electrically connected to the input end of the conversion switch tube M20 of the second signal conversion unit 5, and the output end of the conversion switch tube M18 is used to access the voltage VS.

[0045] More specifically, in Figure 2 In the example, taking the first signal conversion unit 4 as an example, the main current mirror branch of the first current mirror 40 includes a MOS transistor M8, and the slave current mirror branch of the first current mirror 40 includes a MOS transistor M7; the main current mirror branch of the second current mirror 41 includes a MOS transistor M10, and the slave current mirror branch of the second current mirror 41 includes a MOS transistor M9; the main current mirror branch of the third current mirror 42 includes a MOS transistor M17, and the slave current mirror branch of the third current mirror 42 includes a MOS transistor M11;

[0046] The source of the MOS transistor M17 is electrically connected to the source of the MOS transistor M8, the source of the MOS transistor M11, and the source of the MOS transistor M17, respectively, for receiving the voltage VBST. The gate of the MOS transistor M7 is electrically connected to the drain of the MOS transistor M7, the input terminal of the corresponding pull-down high-voltage transistor MHV1, and the gate of the MOS transistor M8, respectively. The drain of the MOS transistor M8 is electrically connected to the drain of the MOS transistor M9, the gate of the MOS transistor M9, the gate of the MOS transistor M10, and the control terminal of its own transfer switch transistor M18, respectively. The source of the MOS transistor M9 and the source of the MOS transistor M10 are electrically connected to the voltage VS. The drain of the MOS transistor M10 is electrically connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11, and the gate of the MOS transistor M17, respectively. The drain of the MOS transistor M17 is the signal output terminal N1 of its own signal conversion unit and is electrically connected to the input terminal of the transfer switch transistor M20 of the second signal conversion unit 5.

[0047] It should be noted that, for the purpose of differentiation, the names of the MOS transistors in the second signal conversion unit 5 are marked differently. In addition, the conversion switch transistor M18 is also an NMOS transistor.

[0048] In addition, in this embodiment, Figure 2 As shown, the present invention further includes a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, and a MOS transistor M24. The source of the MOS transistor M21 and the source of the MOS transistor M23 are used for inputting the voltage VBST. The gate of the MOS transistor M21 is electrically connected to the gate of the MOS transistor M24, the drain of the MOS transistor M24, and the input end of the pull-down high-voltage transistor MHV2 of the second pull-down unit 3, respectively. The gate of the MOS transistor M23 is electrically connected to the gate of the MOS transistor M22, the drain of the MOS transistor M22, and the input end of the pull-down high-voltage transistor MHV1 of the first pull-down unit 2, respectively. The drain of the MOS transistor M21 is electrically connected to the source of the MOS transistor M22, and the drain of the MOS transistor M23 is electrically connected to the source of the MOS transistor M24.

[0049] In addition, in this embodiment, the MOS transistors M21, M22, M23, and M24 are all PMOS transistors. For the PMOS transistors, the source of the PMOS transistor is its own input terminal, the gate of the PMOS transistor is its own control terminal, and the drain of the PMOS transistor is its own output terminal.

[0050] For the present invention Figure 2 In the circuit shown, when the MOS transistors M21, M22, M23, and M24 are absent, ideally, the voltage at node A2 rises synchronously with the voltage VBST. However, due to the parasitic capacitance at node A2, the voltage rise at node A2 lags behind the rise of the voltage VBST, resulting in a large voltage drop. This causes the MOS transistor M12 to turn on, which then causes the MOS transistors M19 and M20 to turn on through the current mirror. The turning on of the MOS transistor M19 increases the voltage at node N2, while the turning on of the MOS transistor M20 decreases the voltage at node N1. This ultimately causes the output VOUT of the level shift circuit to a low level, causing the high-side power transistor of the half-bridge circuit to be erroneously shut down. The operating process of the node A1 changes similarly and is not described here.

[0051] After the MOS transistors M21, M22, M23, and M24 are provided, in actual use, the MOS transistors M21, M22, M23, and M24 form two dynamic branches. When the voltage VS changes, the dynamic branches generate transient currents. By providing a transient current path that quickly responds to the change in voltage VS, the dynamic branches can help stabilize the voltages at nodes A1 and A2. By stabilizing the voltages at nodes A1 and A2, erroneous shutdown of the high-side power transistors of the half-bridge circuit can be avoided.

[0052] Specifically, in this embodiment, Figure 2As shown, the first signal conversion unit 4 and the second signal conversion unit 5 also respectively include a conversion clamp transistor, taking the first signal conversion unit 4 as an example, an input end of the conversion clamp transistor MQ3 is electrically connected with a gate of the MOS tube M7 of the first current mirror 40, and a control end and an output end of the conversion clamp transistor MQ3 are both used for inputting a voltage VS.

[0053] In actual use, the voltage at the node A1 can be clamped by the conversion clamp transistor MQ3, thereby protecting the low-voltage device connected to the node A1.

[0054] In addition, for the level shift circuit, if its noise suppression ability is weak, it will directly affect the reliability of signal transmission, causing the circuit to malfunction. Based on this, in the embodiment, the signal output end N1 of the first signal conversion unit 4 and the signal output end N2 of the second signal conversion unit 5 are electrically connected with the RS flip-flop 6 through the common-mode noise suppression unit 7.

[0055] In Figure 2 , the common-mode noise suppression unit 7 includes an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; an input end of the inverter INV4 is electrically connected with the signal output end N1 of the first signal conversion unit 4 and a first input end of the AND gate AND2 respectively, and an output end of the inverter INV4 is electrically connected with a first input end of the AND gate AND1; an input end of the inverter INV5 is electrically connected with the signal output end N2 of the second signal conversion unit 5 and a second input end of the AND gate AND1 respectively, and an output end of the inverter INV5 is electrically connected with a second input end of the AND gate AND2; an output end of the AND gate AND1 is electrically connected with an R input end of the RS flip-flop, and an output end of the AND gate AND2 is electrically connected with an S input end of the RS flip-flop.

[0056] In the actual signal transmission process, the logic states of the signal output end N1 of the first signal conversion unit 4 and the signal output end N2 of the second signal conversion unit 5 are opposite, and the logic states of the signal output end N1 and the signal output end N2 are rapidly transmitted to the RS output device through the common-mode noise suppression unit 7, thereby changing the output logic state, wherein a truth table of the common-mode noise suppression unit 7 is shown in Table 1:

[0057] Table 1

[0058] [N1] [N2] R S V OUT ]]> 0 1 1 0 0 1 0 0 1 1 1 1 0 0 hold 0 0 0 0 hold

[0059] From Table 1, it can be obtained that during the voltage rapid conversion, even if the logic states of the signal output end N1 and the signal output end N2 are the same and switch between 0 and 1, the logic states of the node R and the node S always remain 0, and the output does not change, always remaining in the logic state before the voltage conversion. Therefore, the common-mode noise suppression unit significantly improves the noise immunity without increasing the circuit delay too much.

[0060] Embodiment two

[0061] As Figure 3 shown, the embodiment provides a high-voltage half-bridge driver, which includes a driving chip 8, the driving chip 8 includes a logic and dead time control unit, a delay matching unit, a high-voltage driving unit, a low-voltage driving unit, a high-voltage switch tube MH and a low-voltage switch tube ML, the driving chip 8 is provided with a VDDL pin, a VBST pin, a VBUS pin, a VS pin, a GND pin, an INH pin and an INL pin, and the driving chip 8 is also provided with the level shift circuit in embodiment one;

[0062] The pin INH and the pin INL are electrically connected with the logic and dead time control unit respectively, for inputting a high-voltage control signal and a low-voltage control signal to the logic and dead time control unit; the VDDL pin is electrically connected with the logic and dead time control unit, the level shift circuit, the delay matching unit and the low-voltage driving circuit respectively, for inputting a signal VDDL, the VBST pin is electrically connected with the level shift circuit and the high-voltage driving unit respectively, for inputting a voltage VBST; the logic and dead time control unit is electrically connected with the level shift circuit and the delay matching unit respectively, the level shift circuit is electrically connected with the high-voltage driving unit, the delay matching unit is electrically connected with the low-voltage matching unit, the high-voltage driving unit is electrically connected with the control end of the high-voltage switch tube MH, the low-voltage driving unit is electrically connected with the control end of the low-voltage switch tube ML, the output end of the high-voltage switch tube MH and the input end of the low-voltage switch tube ML are electrically connected with the VS pin respectively, the output end of the low-voltage switch tube ML is electrically connected with the GND pin, and the input end of the high-voltage switch tube MH is electrically connected with the VBUS pin;

[0063] The VS pin is also electrically connected with one end of an inductor L10 and one end of a capacitor C10 respectively, the other end of the inductor L10 is also electrically connected with the GND pin through a capacitor C11 and a resistor R10 respectively, the other end of the capacitor C10 is electrically connected with the VBST pin and the negative electrode of a diode D10 respectively, and the positive electrode of the diode D10 is electrically connected with the VDDL pin.

[0064] According to the above description, relevant personnel can make various changes and modifications without deviating from the technical idea of the present application. The technical scope of the present application is not limited to the content of the specification, and must be determined by the scope of the claims.

Claims

1. A high-speed level shift circuit, characterized in that: It includes a control signal generating unit, a first pull-down unit, a second pull-down unit, a first signal converting unit, a second signal converting unit and an RS trigger; the first signal converting unit and the second signal converting unit include signal output terminals; The control signal generating unit generates a first control signal and a second control signal based on an input signal VIN, wherein the first control signal is the same as the input signal VIN, and the second control signal is opposite to the input signal VIN; The first pull-down unit and the second pull-down unit respectively include a pull-down switch tube, a pull-down current mirror, a pull-down resistor and a pull-down high-voltage transistor; the output end of the pull-down switch tube is grounded, the first control signal is input to the control end of the pull-down switch tube of the first pull-down unit to control the on-off of the pull-down switch tube of the first pull-down unit, and the second control signal is input to the control end of the pull-down switch tube of the second pull-down unit to control the on-off of the pull-down switch tube of the second pull-down unit; the input end of the pull-down switch tube is electrically connected to the output end of the main current mirror branch of the pull-down current mirror and the output end of the slave current mirror branch of the pull-down current mirror, respectively, the input end of the main current mirror branch of the pull-down current mirror is electrically connected to the output end of the pull-down high-voltage transistor, the input end of the slave current mirror of the pull-down current mirror is electrically connected to the control end of the pull-down high-voltage transistor through the pull-down resistor, and the control end of the pull-down high-voltage transistor is used to input a signal VDDL; The first signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the first pull-down unit, and is configured to pull up the output of its own signal output end and pull down the output of the signal output end of the second signal conversion unit when the pull-down switch tube of the first pull-down unit is turned on; The second signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the second pull-down unit, and is configured to pull up the output of its own signal output end and pull down the output of the signal output end of the first signal conversion unit when the pull-down switch tube of the second pull-down unit is turned on; The R input terminal of the RS trigger is electrically connected to the signal output terminal of the first signal conversion unit, and the S input terminal of the RS trigger is electrically connected to the signal output terminal of the second signal conversion unit.

2. A high-speed level shift circuit according to claim 1, characterized in that: The control signal generating unit includes an inverter INV1, an inverter INV2 and an inverter INV3; the input end of the inverter INV1 is electrically connected to the input end of the inverter INV3, and is used to input the input signal VIN, the output end of the inverter INV1 is electrically connected to the input end of the inverter INV2, the output end of the inverter INV2 is used to output the first control signal, and the output end of the inverter INV3 is used to output the second control signal.

3. The high-speed level shift circuit according to claim 1, wherein: The pull-down current mirror includes a MOS transistor M2 and a MOS transistor M1. The source of the MOS transistor M2 is the output end of the main current mirror branch of the pull-down current mirror, the source of the MOS transistor M1 is the output end of the slave current mirror branch of the pull-down current mirror, the drain of the MOS transistor M1 is electrically connected to the gate of the MOS transistor M1 and the gate of the MOS transistor M2, respectively, and is the input end of the slave current mirror branch of the pull-down current mirror. The drain of the MOS transistor M2 is the input end of the main current mirror branch of the pull-down current mirror.

4. The high-speed level shift circuit according to claim 3, wherein: The first pull-down unit and the second pull-down unit further include a pull-down clamping transistor, respectively. The input end of the pull-down clamping transistor is electrically connected to the control end of the pull-down high-voltage transistor, and the output end of the pull-down high-voltage transistor is electrically connected to the control end of the pull-down clamping transistor and the output end of the pull-down clamping transistor, respectively.

5. The high-speed level shift circuit according to claim 1, wherein: The first signal conversion unit and the second signal conversion unit both include a first current mirror, a second current mirror, a third current mirror and a conversion switch tube; for one of the first signal conversion unit and the second signal conversion unit, the slave current mirror branch of the first current mirror is electrically connected to the input end of the corresponding pull-down high-voltage transistor, the main current mirror branch of the first current mirror is electrically connected to the slave current mirror branch of the second current mirror and the control end of its own conversion switch tube, respectively, the main current mirror branch of the second current mirror is electrically connected to the slave current mirror branch of the third current mirror, the main branch of the third current mirror is electrically connected to the input end of the conversion switch tube of another signal conversion unit, and the output end of the conversion switch tube is used to access the voltage VS.

6. The high-speed level shift circuit according to claim 5, characterized in that: The main current mirror branch of the first current mirror includes a MOS transistor M8, and the slave current mirror branch of the first current mirror includes a MOS transistor M7; the main current mirror branch of the second current mirror includes a MOS transistor M10, and the slave current mirror branch of the second current mirror includes a MOS transistor M9; the main current mirror branch of the third current mirror includes a MOS transistor M17, and the slave current mirror branch of the third current mirror includes a MOS transistor M11; The source of the MOS transistor M17 is electrically connected to the source of the MOS transistor M8, the source of the MOS transistor M11, and the source of the MOS transistor M17, respectively, for receiving the voltage VBST; the gate of the MOS transistor M7 is electrically connected to the drain of the MOS transistor M7, the input terminal of the corresponding pull-down high-voltage transistor, and the gate of the MOS transistor M8, respectively. The drain of the MOS transistor M8 is electrically connected to the drain of the MOS transistor M9, the gate of the MOS transistor M9, the gate of the MOS transistor M10, and the control terminal of its own conversion switch, respectively. The source of the MOS transistor M9 and the source of the MOS transistor M10 are electrically connected to the voltage VS; the drain of the MOS transistor M10 is electrically connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11, and the gate of the MOS transistor M17, respectively. The drain of the MOS transistor M17 is the signal output terminal of its own signal conversion unit and is electrically connected to the input terminal of the conversion switch of another signal conversion unit.

7. The high-speed level shift circuit according to claim 6, characterized in that: The circuit further includes a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, and a MOS transistor M24. The source of the MOS transistor M21 and the source of the MOS transistor M23 are used for inputting the voltage VBST. The gate of the MOS transistor M21 is electrically connected to the gate of the MOS transistor M24, the drain of the MOS transistor M24, and the input end of the pull-down high-voltage transistor of the second pull-down unit, respectively. The gate of the MOS transistor M23 is electrically connected to the gate of the MOS transistor M22, the drain of the MOS transistor M22, and the input end of the pull-down high-voltage transistor of the first pull-down unit, respectively. The drain of the MOS transistor M21 is electrically connected to the source of the MOS transistor M22, and the drain of the MOS transistor M23 is electrically connected to the source of the MOS transistor M24.

8. The high-speed level shift circuit according to claim 7, characterized in that: The first signal conversion unit and the second signal conversion unit further include a conversion clamp transistor respectively, the input end of the conversion clamp transistor is electrically connected to the gate of the MOS transistor M7 of the first current mirror, and the control end and output end of the conversion clamp transistor are both used for input voltage VS.

9. A high-speed level shift circuit according to any one of claims 1 to 8, characterized in that: The signal output terminal of the first signal conversion unit and the signal output terminal of the second signal conversion unit are electrically connected to the RS trigger through the common mode noise suppression unit; The common-mode noise suppression unit includes an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; the input end of the inverter INV4 is electrically connected to the signal output end of the first signal conversion unit and the first input end of the AND gate AND2, respectively, and the output end of the inverter INV4 is electrically connected to the first input end of the AND gate AND1; the input end of the inverter INV5 is electrically connected to the signal output end of the second signal conversion unit and the second input end of the AND gate AND1, respectively, and the output end of the inverter INV5 is electrically connected to the second input end of the AND gate AND2; the output end of the AND gate AND1 is electrically connected to the R input end of the RS trigger, and the output end of the AND gate AND2 is electrically connected to the S input end of the RS trigger.

10. A high-voltage half-bridge driver, comprising a driver chip, the driver chip comprising a logic and dead time control unit, a delay matching unit, a high-voltage driver unit, a low-voltage driver unit, a high-voltage switch tube, and a low-voltage switch tube, the driver chip being provided with a VDDL pin, a VBST pin, a VBUS pin, a VS pin, a GND pin, an INH pin, and an INL pin, characterized in that: The driver chip is further provided with a level shift circuit according to any one of claims 1 to 9; The pin INH and the pin INL are respectively electrically connected to the logic and dead time control unit, and are used to input a high-voltage control signal and a low-voltage control signal to the logic and dead time control unit; the VDDL pin is respectively electrically connected to the logic and dead time control unit, the level shift circuit, the delay matching unit and the low-voltage drive circuit, and is used to input the signal VDDL; the VBST pin is respectively electrically connected to the level shift circuit and the high-voltage drive unit, and is used to input the voltage VBST; the logic and dead time control unit is respectively electrically connected to the level shift circuit and the delay matching unit, the level shift circuit is electrically connected to the high-voltage drive unit, the delay matching unit is electrically connected to the low-voltage drive unit, the high-voltage drive unit is electrically connected to the control end of the high-voltage switch tube, the low-voltage drive unit is electrically connected to the control end of the low-voltage switch tube, the output end of the high-voltage switch tube and the input end of the low-voltage switch tube are respectively electrically connected to the VS pin, the output end of the low-voltage switch tube is electrically connected to the GND pin, and the input end of the high-voltage switch tube is electrically connected to the VBUS pin; The VS pin is also electrically connected to one end of the inductor L10 and one end of the capacitor C10, respectively. The other end of the inductor L10 is also electrically connected to the GND pin through the capacitor C11 and the resistor R10, respectively. The other end of the capacitor C10 is electrically connected to the VBST pin and the cathode of the diode D10, respectively. The anode of the diode D10 is electrically connected to the VDDL pin.

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