Frequency synthesizer with dynamically selected oscillating output signal level shifting

Abstract

The present application relates to a frequency synthesizer with dynamically selected level shifting of an oscillating output signal. An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal to output as a selected oscillating output signal in response to a selection signal. A lock loop circuit controls a frequency of the oscillating output signal based on the selected oscillating output signal and a reference oscillating signal. The selection signal also selects one of the source voltage of the oscillator circuit and a reference voltage as an error amplifier reference voltage for a voltage regulator circuit that generates a first supply voltage.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 62 / 777,446, filed December 10, 2018, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to a frequency synthesizer, and more particularly to the dynamic selection of a level shift operation performed on the oscillation output signal from a current-controlled oscillator of the frequency synthesizer. Background Technology

[0004] right Figure 1 For reference, a circuit diagram of a conventional current-controlled oscillator (CCO) circuit 10 is shown. The CCO circuit 10 includes a ring oscillator 12 formed by an odd number of inverting delay elements 14(1) to 14(n) connected in series. The output of one inverting delay element is connected to the input of the next inverting delay element, and the output of the last inverting delay element 14(n) is connected to the input of the first inverting delay element 14(1). The inverting delay elements 14 are coupled between a source node 18 at a source voltage Vs level and a ground node at a ground voltage level. The level of the source voltage at node 18 depends on the threshold voltage of the transistor in the inverting delay element 14 and the corresponding circuit overdrive. Each inverting delay element 14 provides a delay from input to output that depends on a charging current Icharge, which is provided by a current source 30 from the source voltage Vdd to the source node 18. The oscillation frequency fo of the oscillation output signal 13 (Fout) generated by the ring oscillator depends on the delay amount, and therefore the output frequency can be controlled by the charging current Icharge. The oscillation amplitude of the oscillation output signal 13 (Fout) is controlled by the source voltage Vs at node 18.

[0005] The magnitude of the charging current Icharge output by the current source 30 is set by the voltage control signal CONT. In one embodiment, a p-channel transistor 32 forms the current source 30, wherein the source of the transistor 32 is connected to the source voltage Vdd node, and the drain of the transistor 32 is connected to provide the charging current Icharge to the source node 18. The gate of the transistor 32 is coupled to receive the voltage control signal CONT. The current source 30 accordingly serves as a voltage-to-current converter circuit. The control signal CONT controls the conductivity of the transistor 32, and thus controls the magnitude of the charging current Icharge provided to the source node 18 of the ring oscillator. Therefore, the voltage magnitude of the control signal CONT is used to set the oscillation frequency fo of the oscillation output signal 13Fout.

[0006] Figure 2 A block diagram of a frequency synthesizer circuit 50, such as a frequency-locked loop (FFL) or phase-locked loop (PLL), is shown. Circuit 50 includes a control oscillator 52, which in this implementation is... Figure 1 The CCO circuit 10 is of the type shown. The oscillation output signal 13Fout from the ring oscillator 12 of the control oscillator 52 is level-shifted by the level shifter circuit 54 and divided by the frequency divider circuit 56 to generate an oscillation feedback signal 15(Ffb) with a frequency fo / N, where N is the divider value (integer or decimal) of the frequency divider circuit 56. Level shifting is required in the case of the ring oscillator 12 because the oscillation output signal 13Fout has an oscillation amplitude at the voltage Vs of the source node 18, and the oscillation feedback signal 15Ffb is required to have an amplitude at the source voltage Vdd level of the locked loop circuit 50. The phase-frequency detector circuit 60 compares the phase and frequency fo / N of the oscillation feedback signal 15Ffb with the phase and frequency fr of the oscillation reference signal 17Fref to generate an error signal ERR indicating the determined phase-frequency difference. The error signal ERR is fed to the charge pump (CP) 62, which outputs an equivalent error voltage Verr. This equivalent error voltage Verr is filtered by the filter circuit 64 (e.g., a low-pass filter type) to generate the voltage control signal CONT. (See above for further details.) Figure 1 The control signal CONT is applied to the voltage-to-current converter 66 formed by the current source 30 to generate a charging current Icharge, which controls the frequency fo of the oscillation output signal 13Fout. The feedback loop of the frequency synthesizer circuit 50 controls the magnitude of the control signal CONT such that the phase and frequency fo / N of the oscillation feedback signal 15Ffb derived from the oscillation output signal Fout from the ring oscillator 12 are driven to be equal to the phase and frequency fr of the oscillation reference signal 17Fref.

[0007] In some implementations, the circuitry of the frequency synthesizer circuit 50 can be referenced to two different power supply domains. This is in Figure 3The first supply domain has a positive voltage at a Vdda level (used primarily as a power supply for analog circuit modules, and thus referred to as the analog power supply for the lock loop circuit), and the second supply domain has a positive voltage at a Vddb level (used primarily as a power supply for digital circuit modules, and thus referred to as the digital power supply for the lock loop circuit). In a typical implementation, Vddb is less than Vdda, but it will be appreciated that this is merely an example. Phase frequency detector circuit 60, charge pump 62, filter circuit 64, and voltage-to-current converter 66 are powered by the Vdda level of the first supply domain. Level shifter circuit 54 and frequency divider circuit 56 are powered by the Vddb level of the second supply domain. Another level shifting circuit 58 receives the oscillating feedback signal 15Ffb and the oscillating reference signal 17Fref, and is used to shift those oscillating signals from the Vddb level of the second supply domain to the Vdda level of the first supply domain. Level shifter circuit 54 is used to shift the oscillating output signal 13Fout from the Vs voltage level to the Vddb level of the second supply domain.

[0008] A power management circuit 80 is provided to generate the voltages of the two different supply domains. From an input supply voltage Vsupply provided by an off-chip power supply, for example, a reference voltage generator circuit 82, such as a bandgap reference voltage generator circuit, is used to generate a reference voltage Vref (which can include a bandgap voltage Vbg). A first voltage regulator, such as a low dropout (LDO) type linear voltage regulator 84, generates the Vdda level positive voltage for the first supply domain from the supply voltage Vsupply and the reference voltage Vref, where Vref is the reference voltage for the error amplifier of the regulator. A second voltage regulator, such as a high dropout (HDO) type linear voltage regulator 86, generates the Vddb level positive voltage for the second supply domain from the supply voltage Vsupply and the reference voltage Vref, where Vref is the reference voltage for the error amplifier of the regulator. The ground voltages for the first and second supply domains can be either commonly shared or separate. Figure 4 A basic circuit diagram is shown for a conventional linear regulator circuit of the type used for voltage regulators 84 and 86, in which the error amplifier 70 and power transistor 72 are powered by the input supply voltage Vsupply, and the inputs of the error amplifier are coupled to receive the reference voltage Vref. The voltage level of the regulated output voltage Vdda or Vddb is set by a resistive voltage divider 74 in the feedback loop for the error amplifier.

[0009] Due to the relatively high oscillation frequency fo of the oscillating output signal fout and the large power consumption required to generate this signal, the level shifter circuit 54 for shifting the frequency signal Fout to the Vddb level of the second supply domain must be designed for high speed and high power operation. Therefore, the level shifter circuit 54 is a major consumer of current within the frequency synthesizer circuit 50. Since the frequency synthesizer circuit 50 can be a component of a battery powered device, there is a need in the art to address and reduce current consumption. Another challenge is that digital circuits such as the level shifter circuit 54 must meet certain maximum speed requirements even at the lowest possible supply voltage under slow process corners and worst case temperature values. SUMMARY

[0010] In one embodiment, a circuit includes an oscillator circuit powered with a source voltage and configured to generate an oscillating output signal having an amplitude of a level of the source voltage; and a first level shifter circuit powered by a first supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal; a first multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the first multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal to output as a selected oscillating output signal; a locked loop circuit configured to control a frequency of the selected oscillating output signal from the selected oscillating output signal and a reference oscillating signal; and a first voltage regulator circuit configured to generate the first supply voltage using the source voltage as an error amplifier reference voltage.

[0011] In one embodiment, a circuit includes an oscillator circuit powered with a source voltage and configured to generate an oscillating output signal having an amplitude of a level of the source voltage; a frequency divider circuit powered by a first supply voltage and configured to frequency divide the oscillating output signal to generate a feedback oscillating signal; a phase frequency comparator powered by a second supply voltage and configured to compare the feedback oscillating signal to a reference oscillating signal and generate an error signal; a current source circuit configured to generate a current in response to the error signal, wherein the source voltage of the oscillator circuit is generated in response to the current, and wherein a frequency of the oscillating output signal is controlled by the current; a first voltage regulator circuit configured to generate the first supply voltage using the source voltage of the oscillator circuit as a first error amplifier reference voltage; and a second voltage regulator circuit configured to generate the second supply voltage using a reference voltage as a second error amplifier reference voltage.

[0012] In one embodiment, a circuit includes an oscillator circuit powered by a source voltage and configured to generate an oscillating output signal having a level of the source voltage, a frequency divider circuit powered by a first supply voltage and configured to frequency divide the oscillating output signal to generate a feedback oscillating signal, a phase frequency comparator powered by a second supply voltage and configured to compare the feedback oscillating signal to a reference oscillating signal and generate an error signal, a current source circuit configured to generate a current in response to the error signal, wherein the source voltage of the oscillator circuit is generated in response to the current, and wherein a frequency of the oscillating output signal is controlled by the current, a first multiplexer circuit having a first input configured to receive a reference voltage and a second input configured to receive the source voltage of the oscillator circuit, wherein the second multiplexer circuit selects one of the reference voltage and the source voltage of the oscillator circuit to output as a selected reference voltage, a first voltage regulator circuit configured to generate the first supply voltage using the selected reference voltage as a first error amplifier reference voltage, and a second voltage regulator circuit configured to generate the second supply voltage using the reference voltage as a second error amplifier reference voltage. BRIEF DESCRIPTION OF DRAWINGS

[0013] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings in which:

[0014] Figure 1 is a circuit diagram of a conventional current-controlled oscillator (CCO) circuit;

[0015] Figure 2 is a block diagram of a frequency synthesizer circuit of the lock-in loop operating type;

[0016] Figure 3 illustrates a frequency synthesizer circuit using multiple supply domains;

[0017] Figure 4 illustrates a basic circuit diagram of a conventional linear regulator circuit; and

[0018] Figure 5 to Figure 7 shows a block diagram of an embodiment of a frequency synthesizer circuit of the lock-in loop operating type with dynamically selected level shifting operations. DETAILED DESCRIPTION

[0019] Reference will now be made to Figure 5 , which shows a block diagram of a frequency synthesizer circuit 50' of the lock-in loop operating type with dynamically selected level shifting operations. Like reference numerals refer to like or similar components as shown in Figure 2 to Figure 3 .

[0020] A control oscillator 52 (e.g., includingFigure 1 The CCO circuit 10 of the type shown in Fig. 1 comprises a ring oscillator 12 which generates an oscillating output signal 13 Fout. A level shifter circuit 54 receives the oscillating output signal 13 Fout, performs a level shifting operation to shift the oscillating output signal Fout from a Vs level to a Vddb level of a second supply domain, and thus generates a level shifted oscillating output signal 13'. A first input of a digital multiplexer 90 is coupled to receive the level shifted oscillating output signal 13', and a second input of the digital multiplexer 90 is coupled to receive the (non-level shifted) oscillating output signal 13. A select signal 92 SEL is connected to a select input of the digital multiplexer 90. The logic state of the select signal 92 SEL controls whether the digital multiplexer 90 passes the level shifted oscillating output signal 13' or the (non-level shifted) oscillating output signal 13 to an output 94. The level shifted oscillating output signal 13' or the (non-level shifted) oscillating output signal 13 selected for the output 94 is referred to herein as the selected oscillating output signal Fouts.

[0021] The selected oscillating output signal Fouts at the output 94 of the digital multiplexer 90 is divided by a frequency divider circuit 56 to generate an oscillating feedback signal 15 (Ffb) having a frequency fo / N, where N is the divider value (integer or fractional) of the frequency divider circuit 56. A level shifting circuit 58 receives the oscillating feedback signal Ffb and an oscillating reference signal 17 Fref, and is operative to level shift both of these oscillating signals from the Vddb level of the second supply domain to the Vdda level of the first supply domain. A phase frequency detector circuit 60 compares the phase and frequency fo / N of the level shifted oscillating feedback signal 15 Ffb with the phase and frequency fr of the level shifted oscillating reference signal 17 Fref to generate an error signal ERR indicative of the determined phase frequency difference. The error signal ERR is converted to an error voltage Verr by a charge pump (CP) 62, and the error voltage Verr is filtered by a filter circuit 64 (e.g., of the low pass filter type) to generate a voltage control signal CONT. The control signal CONT is applied to a voltage to current converter 66 formed by the current source 30 to generate a charging current Icharge which controls the frequency fo of the oscillating output signal 13 Fout output by the ring oscillator 12 of the control oscillator 52. The feedback loop of the frequency synthesizer circuit 50' is operative to control the magnitude of the control signal CONT such that the phase and frequency fo / N of the oscillating feedback signal 15 Ffb derived from the oscillating output signal 13 Fout from the ring oscillator 12 is driven to be equal to the phase and frequency fr of the oscillating reference signal 17 Fref.

[0022] The first power domain, having a positive voltage at the Vdda level, powers the phase frequency detector circuit 60, the charge pump 62, the filter circuit 64, and the voltage-to-current converter 66. The second power domain, having a positive voltage at the Vddb level, powers the level shifter circuit 54, the digital multiplexer 90, and the frequency divider circuit 56. The level shifting circuit 58 is powered by both the first power domain and the second power supply domain. In this implementation, Vddb < Vdda, merely by way of example.

[0023] A power management circuit 80' is provided to generate voltages for the two different power supply domains. From an input supply voltage Vsupply provided, for example, by an off-chip power source, a reference voltage generator circuit 82, for example a bandgap reference voltage generator circuit, generates a reference supply voltage Vref (e.g., having a bandgap voltage Vbg level). A first voltage regulator, for example a low dropout (LDO) type linear voltage regulator 84, generates the Vdda level positive voltage for the first power supply domain from the supply voltage Vsupply and the reference voltage Vref, where Vref provides the reference voltage for an error amplifier 70 of the regulator (see Figure 4 ). A first input of an analog multiplexer 100 is coupled to receive the reference voltage Vref, and a second input of the analog multiplexer 100 is coupled to receive the source voltage Vs (or a scaled down source voltage Vs) from the node 18 of the ring oscillator 12. A select signal 92SEL is connected to a select input of the analog multiplexer 100. The logic state of the select signal 92SEL controls whether the analog multiplexer 100 passes the reference voltage Vref or the source voltage Vs to an output 102 (to be used as a reference voltage for the second voltage regulator circuit). The reference voltage Vref or the source voltage Vs passed by the analog multiplexer 100 is referred to herein as the selected reference voltage Vrefs. A second voltage regulator, for example a high dropout (HDO) type linear voltage regulator 86, generates the Vddb level positive voltage for the second power supply domain from the supply voltage Vsupply and the selected reference voltage Vrefs, where Vrefs is used as the reference voltage for an error amplifier 70 of the regulator Figure 4 ). The ground voltages for the first and second power supply domains can be commonly shared or separate.

[0024] In case the selection signal 92SEL is in the first logic state, the digital multiplexer 90 selects the level-shifted oscillating output signal 13' as the selected oscillating output signal Fouts for the output 94, and the analog multiplexer 100 selects the reference voltage Vref output by the reference voltage generator circuit 82 as the selected reference voltage Vrefs for the output 102. Conversely, in case the selection signal 92SEL is in the second logic state, the digital multiplexer 90 selects the (non-level-shifted) oscillating output signal 13 as the selected oscillating output signal Fouts for the output 94, and the analog multiplexer 100 selects the supply voltage Vs of the ring oscillator 12 as the selected reference voltage Vrefs for the output 102.

[0025] During start-up of the frequency synthesizer circuit 50', the oscillation frequency fo of the oscillating output signal Fout will be relatively slow due to the relatively low magnitude of the charging current Icharge. Here, it should be noted that the establishment of the voltage control signal CONT takes time (which depends on the bandwidth of the lock-in loop circuit and the current of the charge pump). The level-shifting of the oscillating output signal Fout to the Vddb level of the second supply domain is crucial to ensure proper acquisition of frequency lock and further to ensure that the supply voltage Vs of the oscillator is at a sufficient amplitude to power the digital circuitry. Therefore, the selection signal 92SEL is set to the first logic state so that the digital multiplexer 90 selects the level-shifted oscillating output signal 13' as the selected oscillating output signal Fouts for the output 94. At the same time, in case the selection signal 92SEL is set to the first logic state, the reference voltage Vref output by the reference voltage generator circuit 82 is selected as the selected reference voltage Vrefs by the analog multiplexer 100. Therefore, the Vddb level of the second supply domain is generated by the second voltage regulator 86 using the reference voltage Vref as error amplifier reference voltage (see Figure 4 ).

[0026] After the time period required for the increase of the supply voltage Vs and the increase of the oscillation frequency fo of the oscillating output signal Fout has expired, the selection signal 92SEL is switched to the second logic state. Now, the digital multiplexer 90 selects the (non-level-shifted) oscillating output signal 13 as the selected oscillating output signal Fouts for the output 94. Now, the analog multiplexer 100 selects the supply voltage Vs as the selected reference voltage Vrefs. Therefore, the Vddb level of the second supply domain is generated by the second voltage regulator 86 using the supply voltage Vs as error amplifier reference voltage (see Figure 4 ).

[0027] Importantly, the source voltage Vs inherently has information about the process, temperature, and frequency of oscillation of the ring oscillator 12, which is automatically transferred to the Vddb level of the second power supply domain when the analog multiplexer 100 selects the source voltage Vs as the selected reference voltage Vrefs for the error amplifier of the second voltage regulator 86.

[0028] The selection signal 92SEL can be generated by any suitable control circuit. In the implementation shown in Figure 5 In the implementation shown in Fig. 1, the selection signal 92SEL is generated by a lock detection circuit 110, which senses the level-shifted oscillation feedback signal 15Ffb and the level-shifted oscillation reference signal 17Fref. These signals are compared by the lock detection circuit 110 to determine the degree to which the level-shifted oscillation feedback signal 15Ffb is locked to the level-shifted oscillation reference signal 17Fref. When this degree exceeds a threshold, the lock detection circuit 110 switches the selection signal 92SEL from the first logic state to the second logic state. For example, lock-in-loop circuits are known to have a coarse lock detector and / or a fine lock detector. One of these lock detectors can further be used to generate the selection signal 92SEL. For example, a switch from the first logic state to the second logic state can occur when coarse lock is achieved.

[0029] In another implementation, the control circuit for generating the selection signal 92SEL can be a calibration circuit 110a (see Fig. 2). During a calibration mode, the calibration circuit 110a sets the selection signal 92SEL to the first logic state. When calibration is complete, the calibration circuit 110a switches the selection signal 92SEL to the second logic state. Figure 6

[0030] In another implementation, the control circuit for generating the selection signal 92SEL can be an open-loop initialization circuit 110b (see Fig. 3). During initialization of the frequency synthesizer circuit 50', the circuit 110ba sets the selection signal 92SEL to the first logic state. When initialization is complete, the circuit 110b switches the selection signal 92SEL to the second logic state. Figure 7

[0031] Figure 5 to Figure 7 An advantage of the implementation shown in Fig. 1 is that the high-speed level shifter 54 is removed from the feedback loop without the need for the high-speed level shifter 54. Since the level shifter 54 operates at maximum speed and also since the phase is non-differential to the ring oscillator, the level shifter 54 consumes a significant amount of current. In one implementation, the level shifter 54 is disabled when the control multiplexer 90 selects the unlevel-shifted Fout signal.

[0032] Figure 5 to Figure 7 ​​The main benefit of the implementation shown in the middle is that the disclosed technology automatically tracks the process, temperature, and frequency of oscillation. For example, if the process is automatically fast, the power supply will be low, thus saving current and power consumption in the voltage divider, level shifter, etc. Similarly, depending on the voltage (whether mobility or threshold effect is dominant), the voltage will be lower at the lowest or highest temperature. If the oscillator is at the minimum oscillation frequency, the voltage will be minimum, and if the oscillation frequency increases, the voltage will automatically be higher. This will greatly reduce the possibility of functional failure. Furthermore, it should be noted that since the voltage divider directly acts on the frequency of the oscillator output signal Fout, it operates at a very high speed. It is a standard practice to use a high-speed true single-phase clock (TSPC) flip-flop in the voltage divider to achieve high-frequency operation. Since the supply of the voltage divider can now track the process, temperature, and frequency of oscillation, the voltage divider is easier to design.

[0033] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed application, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: an oscillator circuit powered with a source voltage and configured to generate an oscillating output signal having an amplitude of a level of the source voltage; a first level shifter circuit powered with a first supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal; a first multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the first multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal to output as a selected oscillating output signal; a lock loop circuit configured to control a frequency of the oscillating output signal from the selected oscillating output signal and a reference oscillating signal; and a first voltage regulator circuit configured to generate the first supply voltage using the source voltage as an error amplifier reference voltage.

2. The circuit of claim 1, wherein the lock loop circuit comprises: a frequency divider circuit configured to frequency divide the selected oscillating output signal to generate a feedback oscillating signal; a phase frequency comparator configured to compare the feedback oscillating signal to the reference oscillating signal and generate an error signal; wherein the frequency of the oscillating output signal is set from the error signal.

3. The circuit of claim 2, wherein the frequency divider circuit is powered with the first supply voltage, and wherein the phase frequency comparator is powered with a second supply voltage, the first supply voltage being less than the second supply voltage.

4. The circuit of claim 3, further comprising a second voltage regulator circuit configured to generate the second supply voltage using a reference voltage as an error amplifier reference voltage.

5. The circuit of claim 4, wherein the reference voltage is a bandgap voltage. a second multiplexer circuit having a first input configured to receive the reference voltage and a second input configured to receive the source voltage of the oscillator circuit, wherein the second multiplexer circuit selects one of the reference voltage and the source voltage of the oscillator circuit to output as the error amplifier reference voltage of the first voltage regulator circuit.

6. The circuit of claim 4, further comprising:

7. The circuit of claim 6, further comprising a control circuit configured to generate a selection signal applied to selection inputs of the first multiplexer circuit and the second multiplexer circuit, the selection signal having: a first logic state to cause the first multiplexer circuit to select the level shifted oscillating output signal and the second multiplexer circuit to simultaneously select the reference voltage; and a second logic state to cause the first multiplexer circuit to select the oscillating output signal and the second multiplexer circuit to simultaneously select the source voltage of the oscillator circuit. a second logic state for causing the first multiplexer circuit to select the oscillating output signal and the second multiplexer circuit to simultaneously select the source voltage.

8. The circuit of claim 7, wherein the control circuit includes a lock detection circuit that causes the selection signal to transition from the first logic state to the second logic state in response to detecting a lock condition of the oscillating output signal.

9. The circuit of claim 8, wherein the lock condition is a coarse lock of phase frequency between the feedback oscillating signal and the reference oscillating signal.

10. The circuit of claim 7, wherein the control circuit includes a calibration circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of a calibration operation.

11. The circuit of claim 7, wherein the control circuit includes an initialization circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of an initialization operation.

12. The circuit of claim 11, wherein the initialization operation is a start-up operation.

13. The circuit of claim 3, further comprising a second level shifter configured to shift the feedback oscillating signal from the first supply voltage level to the second supply voltage.

14. The circuit of claim 3, further comprising a voltage-to-current conversion circuit configured to convert a control voltage derived from the error signal to a current from which the source voltage of the oscillator circuit is generated.

15. The circuit of claim 14, wherein the voltage-to-current conversion circuit is powered by the second supply voltage.

16. The circuit of claim 1, wherein the error amplifier reference voltage is scaled from the source voltage.

17. A circuit, comprising: an oscillator circuit powered with a source voltage and configured to generate an oscillating output signal of a level of amplitude of the source voltage; a frequency divider circuit powered by a first supply voltage and configured to frequency divide the oscillating output signal to generate a feedback oscillating signal; a phase frequency comparator powered by a second supply voltage and configured to compare the feedback oscillating signal to a reference oscillating signal and generate an error signal; a current source circuit configured to generate a current in response to the error signal, wherein the source voltage of the oscillator circuit is generated in response to the current and a frequency of the oscillating output signal is controlled by the current; a first voltage regulator circuit configured to generate the first supply voltage using the source voltage of the oscillator circuit as a first error amplifier reference voltage; and a second voltage regulator circuit configured to generate the second supply voltage using a reference voltage as a second error amplifier reference voltage. ​ 18. The circuit of claim 17, wherein the current source circuit is powered by the second supply voltage.

19. The circuit of claim 17, wherein the reference voltage is a bandgap voltage.

20. The circuit of claim 17, further comprising: a first level shifter circuit powered by the first supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal; and a first multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the first multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal to output as a selected oscillating output signal from which the frequency divider circuit generates the feedback oscillating signal.

21. The circuit of claim 20, further comprising a control circuit configured to generate a selection signal applied to a select input of the first multiplexer circuit, the selection signal having: a first logic state to cause the first multiplexer circuit to select the level shifted oscillating output signal; and a second logic state to cause the first multiplexer circuit to select the oscillating output signal.

22. The circuit of claim 21, wherein the control circuit includes a lock detect circuit that causes the selection signal to transition from the first logic state to the second logic state in response to detecting a lock condition of the oscillating output signal.

23. The circuit of claim 22, wherein the lock condition is a coarse lock of phase frequency between the feedback oscillating signal and the reference oscillating signal.

24. The circuit of claim 21, wherein the control circuit includes a calibration circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of a calibration operation.

25. The circuit of claim 21, wherein the control circuit includes an initialization circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of an initialization operation.

26. The circuit of claim 25, wherein the initialization operation is a start-up operation.

27. The circuit of claim 17, further comprising a second multiplexer circuit having a first input configured to receive the reference voltage and a second input configured to receive the source voltage of the oscillator circuit, wherein the second multiplexer circuit selects one of the reference voltage and the source voltage of the oscillator circuit to output as the first error amplifier reference voltage of the first voltage regulator circuit. ​ 28. The circuit of claim 27, further comprising a control circuit configured to generate a select signal applied to a select input of the second multiplexer circuit, the select signal having: a first logic state to cause the second multiplexer circuit to select the reference voltage; and a second logic state to cause the second multiplexer circuit to select the source voltage.

29. The circuit of claim 28, wherein the control circuit comprises a lock detect circuit that causes the select signal to transition from the first logic state to the second logic state in response to detecting a lock condition.

30. The circuit of claim 29, wherein the lock condition is a coarse lock of phase frequency between the feedback oscillation signal and the reference oscillation signal.

31. The circuit of claim 28, wherein the control circuit comprises a calibration circuit that causes the select signal to transition from the first logic state to the second logic state in response to completion of a calibration operation.

32. The circuit of claim 28, wherein the control circuit comprises an initialization circuit that causes the select signal to transition from the first logic state to the second logic state in response to completion of an initialization operation.

33. The circuit of claim 32, wherein the initialization operation is a start-up operation.

34. The circuit of claim 17, wherein the first error amplifier reference voltage is scaled from the source voltage.

35. A circuit comprising: an oscillator circuit powered with a source voltage and configured to generate an oscillation output signal having an amplitude at a level of the source voltage; a frequency divider circuit powered by a first supply voltage and configured to frequency divide the oscillation output signal to generate a feedback oscillation signal; a phase frequency comparator powered by a second supply voltage and configured to compare the feedback oscillation signal to a reference oscillation signal and generate an error signal; a current source circuit configured to generate a current in response to the error signal, wherein the source voltage of the oscillator circuit is generated in response to the current, and wherein a frequency of the oscillation output signal is controlled by the current; a first multiplexer circuit having a first input configured to receive a reference voltage and a second input configured to receive the source voltage of the oscillator circuit, wherein the first multiplexer circuit selects one of the reference voltage and the source voltage of the oscillator circuit to output as a selected reference voltage; a first voltage regulator circuit configured to generate the first supply voltage using the selected reference voltage as a first error amplifier reference voltage; and a second voltage regulator circuit configured to generate the second supply voltage using the reference voltage as a second error amplifier reference voltage.

36. The circuit of claim 35, further comprising a control circuit configured to generate a select signal applied to a select input of the first multiplexer circuit, the select signal having: a first logic state to cause the first multiplexer circuit to select the reference voltage; and a second logic state to cause the first multiplexer circuit to select the source voltage of the oscillator circuit.

37. The circuit of claim 36, wherein the control circuit comprises a lock detect circuit that causes the select signal to transition from the first logic state to the second logic state in response to detecting a lock condition.

38. The circuit of claim 37, wherein the lock condition is a coarse lock of phase frequency between the feedback oscillation signal and the reference oscillation signal.

39. The circuit of claim 36, wherein the control circuit comprises a calibration circuit that causes the select signal to transition from the first logic state to the second logic state in response to completion of a calibration operation.

40. The circuit of claim 36, wherein the control circuit comprises an initialization circuit that causes the select signal to transition from the first logic state to the second logic state in response to completion of an initialization operation.

41. The circuit of claim 40, wherein the initialization operation is a start-up operation.

42. The circuit of claim 35, wherein the first error amplifier reference voltage is scaled from the source voltage.

43. The circuit of claim 35, wherein the second error amplifier reference voltage is scaled from the reference voltage.

36. The circuit of claim 35, wherein the current source circuit is powered by the second supply voltage.

37. The circuit of claim 35, wherein the reference voltage is a bandgap voltage.

38. The circuit of claim 35, further comprising a control circuit configured to generate a selection signal applied to a selection input of the first multiplexer circuit, the selection signal having: a first logic state to cause the first multiplexer circuit to select the reference voltage; and a second logic state to cause the first multiplexer circuit to select the source voltage.

39. The circuit of claim 35, further comprising: a level shifter circuit powered by the first supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal; and a second multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the second multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal to output as a selected oscillating output signal from which the frequency divider circuit generates the feedback oscillating signal.

40. The circuit of claim 39, further comprising a control circuit configured to generate a selection signal applied to selection inputs of the first multiplexer circuit and the second multiplexer circuit, the selection signal having: a first logic state to cause the first multiplexer circuit to select the reference voltage and the second multiplexer circuit to simultaneously select the level shifted oscillating output signal; and a second logic state to cause the first multiplexer circuit to select the source voltage and the second multiplexer circuit to simultaneously select the oscillating output signal.

41. The circuit of claim 40, wherein the control circuit includes a lock detect circuit that causes the selection signal to transition from the first logic state to the second logic state in response to detecting a lock condition.

42. The circuit of claim 40, wherein the control circuit includes a calibration circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of a calibration operation.

43. The circuit of claim 40, wherein the control circuit includes an initialization circuit that causes the selection signal to transition from the first logic state to the second logic state in response to completion of an initialization operation. ​

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