Level conversion circuit
By setting up current branches and current mirror circuits, the problems of high power consumption and slow conversion speed of level conversion circuits are solved, and fast response and low-energy conversion at the voltage output end are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-10
AI Technical Summary
Existing level conversion circuits suffer from high power consumption and slow conversion speed.
By employing a different width-to-length ratio for the first and second current branches, the current is mirrored to the voltage output terminal through a current mirror circuit. The input voltage is controlled to reverse the magnitude relationship of the current branches. Combined with an inverter and a current source, a rapid conversion of the voltage output is achieved.
It achieves fast voltage response and low-power level conversion at the voltage output terminal, solving the problems of high power consumption and slow conversion speed in existing level conversion circuits.
Smart Images
Figure CN121841344A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a level conversion circuit. Background Technology
[0002] Level shifting circuits play an indispensable role in the field of integrated circuits. They are used to transmit signals between two power supply systems, achieving level shifting from the low power rail (GND~VCCL) to the high power rail (FGND~VCCH). However, related technologies for level shifting circuits suffer from problems such as high power consumption and slow conversion speed. Summary of the Invention
[0003] This application provides a level conversion circuit to solve at least some of the problems in the related art.
[0004] This application provides a level conversion circuit, including: a first voltage terminal, a second voltage terminal, an input terminal, a first current branch, a second current branch, a current mirror circuit, and a voltage output terminal. The voltage of the first voltage terminal is greater than the voltage of the second voltage terminal. The first current branch includes a first switching transistor, and the second current branch includes a second switching transistor. The aspect ratio of the first switching transistor is greater than the aspect ratio of the second switching transistor. Both the first current branch and the second current branch are connected between the first voltage terminal and a ground terminal. The input terminal is connected to the first switching transistor. The voltage at the input terminal is used to control the switching on and off of the first switching transistor, and the voltage controlling the first switching transistor to conduct is the same as the voltage driving the second switching transistor to conduct, so that the magnitude relationship between the first current branch and the second current branch is reversed. The current mirror circuit is connected to both the first current branch and the second current branch, and the current mirror circuit is used to mirror the current of the first current branch and the current of the second current branch to the area between the first voltage terminal and the voltage output terminal, and the area between the voltage output terminal and the second voltage terminal, respectively.
[0005] Furthermore, the voltage at the input terminal includes a first voltage and a second voltage, wherein the first voltage is greater than the second voltage, and the first switch is turned on when the voltage at the input terminal is the first voltage; and the first switch is turned off when the voltage at the input terminal is the second voltage, wherein the first voltage is the same as the voltage that drives the second switch to turn on.
[0006] Furthermore, when the first switch is off, the current in the second current branch is greater than the current in the first current branch and the current in the second current branch is a times the current in the first current branch, where a is not less than 2; when the first switch is on, the current in the first current branch is greater than the current in the second current branch and the current in the first current branch is b times the current in the second current branch, where b is not less than 2.
[0007] Furthermore, the first current branch also includes a third switch, which is connected in parallel with the first switch. The width-to-length ratio of the third switch is smaller than that of the second switch. The voltage at the input terminal that controls the first switch to turn on is the same as the voltage that drives the third switch to turn on.
[0008] Furthermore, the ratio of the width-to-length ratio of the first switch transistor, the width-to-length ratio of the third switch transistor, and the width-to-length ratio of the second switch transistor is (n×n-1):1:n, where n is not less than 2.
[0009] Furthermore, the first switch, the second switch, and the third switch are all NMOS transistors. The input terminal is connected to the gate of the first switch. The gate voltage of the second switch and the gate voltage of the third switch are both the first voltage. The source of the first switch, the source of the second switch, and the source of the third switch are all connected to the ground terminal. The drain of the first switch, the drain of the second switch, and the drain of the third switch are all connected to the first voltage terminal.
[0010] Furthermore, the current mirror circuit includes a first current mirror, a second current mirror, and a third current mirror. Each of the first, second, and third current mirrors includes a reference branch and a mirror branch. The reference branch of the first current mirror is connected between the first voltage terminal and the first current branch. The reference branch of the second current mirror is connected between the first voltage terminal and the second current branch. The mirror branch of the second current mirror and the reference branch of the third current mirror are connected in series between the first voltage terminal and the second voltage terminal. The mirror branch of the first current mirror is connected between the first voltage terminal and the voltage output terminal. The mirror branch of the third current mirror is connected between the voltage output terminal and the second voltage terminal.
[0011] Furthermore, the level conversion circuit includes a first inverter and a second inverter, the first inverter being located between the input terminal and the first switching transistor, and the second inverter being connected to the voltage output terminal.
[0012] Furthermore, the number of the first inverters is odd, the number of the second inverters is odd, the odd number of the first inverters are connected in series, and the odd number of the second inverters are connected in series.
[0013] Furthermore, it also includes a current source, one end of which is connected to both the first current branch and the second current branch, and the other end of which is connected to the grounding terminal.
[0014] Furthermore, the current source includes a reference current generating circuit and a fourth current mirror. The fourth current mirror includes a fourth switch and a fifth switch connected to each other. The reference current generating circuit is connected to the fourth switch. The fifth switch is connected to both the first current branch and the second current branch. The width-to-length ratio of the fourth switch is equal to the width-to-length ratio of the fifth switch.
[0015] Furthermore, the level conversion circuit also includes a resistor, one end of which is connected to both the first current branch and the second current branch, and the other end of which is connected to the ground terminal.
[0016] The level conversion circuit provided in this application includes: a first voltage terminal, a second voltage terminal, an input terminal, a first current branch, a second current branch, a current mirror circuit, and a voltage output terminal. The voltage of the first voltage terminal is greater than the voltage of the second voltage terminal. The first current branch includes a first switching transistor, and the second current branch includes a second switching transistor. The width-to-length ratio of the first switching transistor is greater than the width-to-length ratio of the second switching transistor. Both the first current branch and the second current branch are connected between the first voltage terminal and the ground terminal. The input terminal is connected to the first switching transistor. The voltage at the input terminal is used to control the on / off state of the first switching transistor, and the voltage controlling the first switching transistor to conduct is the same as the voltage driving the second switching transistor to conduct, so that the magnitude relationship between the first current branch and the second current branch is reversed. The current mirror circuit is connected to both the first current branch and the second current branch. The current mirror circuit is used to mirror the current of the first current branch and the current of the second current branch to the space between the first voltage terminal and the voltage output terminal and the space between the voltage output terminal and the second voltage terminal, respectively.
[0017] Thus, by controlling the voltage at the input terminal to control the switching on and off of the first switching transistor, the relationship between the current in the first current branch and the current in the second current branch is reversed, thereby reversing the relationship between the current between the first voltage terminal and the voltage output terminal, and between the voltage output terminal and the second voltage terminal. When the current between the first voltage terminal and the voltage output terminal is greater than the current between the voltage output terminal and the second voltage terminal, the voltage at the voltage output terminal approaches the voltage at the first voltage terminal. When the current between the first voltage terminal and the voltage output terminal is less than the current between the voltage output terminal and the second voltage terminal, the voltage at the voltage output terminal approaches the voltage at the second voltage terminal. In this way, the voltage at the voltage output terminal can be controlled by controlling the voltage at the input terminal, a simple, fast, and energy-efficient method. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0019] Figure 1 This is a circuit diagram of one type of level conversion circuit in related technologies; Figure 2 This is a circuit diagram of another level conversion circuit in the related technology; Figure 3 This is a schematic block diagram of a level conversion circuit according to one embodiment of this application; Figure 4 for Figure 3 A circuit diagram of one embodiment of the level conversion circuit shown; Figure 5 This is a schematic block diagram of a level conversion circuit according to another embodiment of this application; Figure 6 for Figure 5 A circuit diagram of one embodiment of the level conversion circuit shown; Figure 7 This is a circuit diagram of a level conversion circuit shown in another embodiment of this application; Figure 8 This is a circuit diagram of a level conversion circuit shown in another embodiment of this application.
[0020] Figure label: Level conversion circuit 1, first voltage terminal 11, second voltage terminal 12, input terminal 13, voltage output terminal 14, first current branch 20, second current branch 30, current mirror circuit 40, first switch 21, second switch 31, third switch 22, ground terminal 17, first inverter 15, second inverter 16, first current mirror 41, second current mirror 42, third current mirror 43, current source 50, fourth current mirror 51, fourth switch 52, fifth switch 53, resistor 55. Detailed Implementation
[0021] This application provides a level conversion circuit. The level conversion circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.
[0022] Please refer to Figure 1 , Figure 1 This is a circuit diagram of one type of level conversion circuit in related technologies. Figure 1 In the level conversion circuit shown, a common-source circuit is used to achieve the level conversion from GND~VCCL to GND~VCCH. When Vin=VCCL is high, the potential at point A is low, MN1 is cut off, and Vout=VCCH-Idmn1×R≈VCCH, where Idmn1 is the cutoff current of the switching transistor MN1. When Vin=GND is low, the potential at point A is high, MN1 is on, and by selecting an appropriate resistor R, Vout=VCCH-Idmn1×R≈GND can be achieved.
[0023] Figure 1 The level shifting circuit shown uses resistor sampling for Vout, only achieving level shifting from GND~VCCL to GND~VCCH. According to the voltage equation Vout=VCCH-Idmn1×R, when MN1 is off, Vout≈VCCH. However, when MN1 is on, the resistance of R must be much larger than the on-resistance of MN1 to achieve Vout≈GND. Secondly, after MN1 is on, the current in the entire circuit is large, resulting in significant power dissipation across the large resistor R. Furthermore, resistor sampling cannot achieve rapid level shifting.
[0024] Please refer to Figure 2 , Figure 2 This is a circuit diagram of another level conversion circuit in related technologies. Figure 2 The level shifting circuit shown has a potential range of GND to VCCH when Vin switches between GND and VCCL. When VCCH differs significantly from FGND, the NMOS transistor in the I2 inverter requires a high gate oxide breakdown voltage; otherwise, a negative breakdown of VGS will occur, i.e., VGS = GND - FGND. Furthermore, MN1, MN2, MP1, and MP2 also require high gate oxide breakdown voltages. This type of full-port high-voltage transistor has a complex manufacturing process, a large layout area, high cost, and consumes more chip resources.
[0025] Please refer to Figure 3 , Figure 3 This is a schematic block diagram of a level conversion circuit 1 according to an embodiment of this application. Figure 3As shown, the level conversion circuit 1 includes: a first voltage terminal 11, a second voltage terminal 12, an input terminal 13, a first current branch 20, a second current branch 30, a current mirror circuit 40, and a voltage output terminal 14. The voltage at the first voltage terminal 11 is greater than the voltage at the second voltage terminal 12. The first current branch 20 includes a first switching transistor 21, and the second current branch 30 includes a second switching transistor 31. The aspect ratio of the first switching transistor 21 is greater than that of the second switching transistor 31. Both the first current branch 20 and the second current branch 30 are connected between the first voltage terminal 11 and the ground terminal 17. The input terminal 13 is connected to the first switching transistor 21. The voltage at the input terminal 13 is used to control the on / off state of the first switching transistor 21, and the voltage controlling the first switching transistor 21 to conduct is the same as the voltage driving the second switching transistor 31 to conduct, so that the magnitude relationship between the currents in the first current branch 20 and the second current branch 30 is reversed. The current mirror circuit 40 is connected to both the first current branch 20 and the second current branch 30. The current mirror circuit 40 is used to mirror the current of the first current branch 20 and the current of the second current branch 30 to the area between the first voltage terminal 11 and the voltage output terminal 14 and the area between the voltage output terminal 14 and the second voltage terminal 12, respectively.
[0026] When the voltage at input terminal 13 controls the first switch 21 to turn off, the current in the first current branch 20 is the cutoff current of the first switch 21. The current in the first current branch 20 is extremely small and less than the current in the second current branch 30.
[0027] When the voltage at input terminal 13 controls the first switch 21 to turn on, because the width-to-length ratio of the first switch 21 is greater than that of the second switch 31, and both the first current branch 20 and the second current branch 30 are connected between the first voltage terminal 11 and the ground terminal 17, and the voltage controlling the first switch 21 to turn on is the same as the voltage driving the second switch 31 to turn on, the current in the first current branch 20 is greater than the current in the second current branch 30. Thus, the switching on and off of the first switch 21 can be controlled by controlling the voltage at input terminal 13 to reverse the relationship between the currents in the first current branch 20 and the second current branch 30.
[0028] The current mirror circuit 40 is used to mirror the current of the first current branch 20 and the current of the second current branch 30 to the area between the first voltage terminal 11 and the voltage output terminal 14, and between the voltage output terminal 14 and the second voltage terminal 12, respectively. When the voltage of the control input terminal 13 controls the switching of the first switch 21 to reverse the relationship between the currents of the first current branch 20 and the second current branch 30, the relationship between the currents between the first voltage terminal 11 and the voltage output terminal 14, and between the voltage output terminal 14 and the second voltage terminal 12, will also be reversed.
[0029] When the first switch 21 is on and off, the current between the first voltage terminal 11 and the voltage output terminal 14 is not equal to the current between the voltage output terminal 14 and the second voltage terminal 12. However, according to the circuit connection and the principle of current conservation, the current between the first voltage terminal 11 and the voltage output terminal 14 must be equal to the current between the voltage output terminal 14 and the second voltage terminal 12. Therefore, the drain-source voltages of the switches located between the first voltage terminal 11 and the voltage output terminal 14 and between the voltage output terminal 14 and the first voltage terminal 11 in the current mirror circuit 40 need to be adjusted so that the current between the first voltage terminal 11 and the voltage output terminal 14 and the current between the voltage output terminal 14 and the second voltage terminal 12 are the same. When the switching transistors located between the first voltage terminal 11 and the voltage output terminal 14 and the switching transistors located between the voltage output terminal 14 and the first voltage terminal 11 in the current mirror circuit 40 adjust the drain-source voltage, the potential of the voltage output terminal 14 will shift towards the first voltage terminal 11 or the second voltage terminal 12, so that the voltage of the voltage output terminal 14 approaches the voltage of the first voltage terminal 11 or the voltage of the second voltage terminal 12.
[0030] When the first switch 21 is turned on, the current in the first current branch 20 is greater than the current in the second current branch 30. After the action of the current mirror circuit 40, the current between the first voltage terminal 11 and the voltage output terminal 14 is greater than the current between the voltage output terminal 14 and the second voltage terminal 12. In the current mirror circuit 40, the switch located between the first voltage terminal 11 and the voltage output terminal 14 needs to reduce its drain-source voltage, and the switch located between the voltage output terminal 14 and the second voltage terminal 12 needs to increase its drain-source voltage, causing the voltage of the voltage output terminal 14 to approach the voltage of the first voltage terminal 11.
[0031] When the first switch 21 is turned off, the current in the first current branch 20 is less than the current in the second current branch 30. After the action of the current mirror circuit 40, the current between the first voltage terminal 11 and the voltage output terminal 14 is less than the current between the voltage output terminal 14 and the second voltage terminal 12. In the current mirror circuit 40, the switch located between the first voltage terminal 11 and the voltage output terminal 14 needs to increase the drain-source voltage, and the switch located between the voltage output terminal 14 and the second voltage terminal 12 needs to decrease the drain-source voltage, causing the voltage of the voltage output terminal 14 to approach the voltage of the second voltage terminal 12.
[0032] The greater the difference between the current in the first current branch 20 and the current in the second current branch 30, that is, the greater the difference between the current between the first voltage terminal 11 and the voltage output terminal 14, and the current between the voltage output terminal 14 and the second voltage terminal 12, the closer the voltage output terminal 14 is to the voltage of the first voltage terminal 11 or the voltage of the second voltage terminal 12.
[0033] In some embodiments, when the first switch 21 is off, the current in the second current branch 30 is greater than the current in the first current branch 20, and the current in the second current branch 30 is *a* times the current in the first current branch 20, where *a* is not less than 2. When the first switch 21 is on, the current in the first current branch 20 is greater than the current in the second current branch 30, and the current in the first current branch 20 is *b* times the current in the second current branch 30, where *b* is not less than 2. Thus, whether the first switch 21 is off or on, the current difference between the first current branch 20 and the second current branch 30 is relatively large, resulting in a relatively large difference between the current between the first voltage terminal 11 and the voltage output terminal 14, and between the voltage output terminal 14 and the second voltage terminal 12. Consequently, the voltage at the voltage output terminal 14 significantly approaches the voltage at the first voltage terminal 11 or significantly approaches the voltage at the second voltage terminal 12.
[0034] Within a certain range, the greater the current difference between the first current branch 20 and the second current branch 30, the closer the voltage at the output terminal will be to either the first or the second voltage terminal. However, the current difference between the first current branch 20 and the second current branch 30 does not need to be infinitely large. When a and b are greater than 5, the approaching effect will not improve significantly as the values of a and b increase, and it will also lead to increased cost and circuit area. Generally, the values of a and b should not exceed 5.
[0035] In this embodiment, the voltage at input terminal 13 includes a first voltage and a second voltage, where the first voltage is greater than the second voltage. When the voltage at input terminal 13 is the first voltage, the first switch 21 is turned on. When the voltage at input terminal 13 is the second voltage, the first switch 21 is turned off. The first voltage is the same as the voltage that drives the second switch 31 to turn on. Thus, when the voltage at input terminal is the first voltage, the voltage at output terminal 14 approaches the voltage at first voltage terminal 11; and when the voltage at input terminal 13 is the second voltage, the voltage at output terminal 14 approaches the voltage at second voltage terminal 12. This achieves the conversion from power rail (second voltage ~ first voltage) to power rail (voltage at second voltage terminal 12 ~ voltage at first voltage terminal 11).
[0036] In this embodiment, the voltage of the first voltage terminal 11 is greater than the first voltage of the input terminal 13, and the voltage of the second voltage terminal 12 is greater than the second voltage of the input terminal 13. The first voltage of the input terminal is VCCL, the second voltage of the input terminal is GND, the voltage of the first voltage terminal 11 is VCCH, and the voltage of the second voltage terminal 12 is FGND. Therefore, this embodiment can realize the level conversion of the signal from the low power rail of GND~VCCL to the high power rail of FGND~VCCH.
[0037] In this embodiment, when the voltage at the first voltage terminal 11 is high, such as 30V, and the voltage difference between the first voltage terminal 11 and the second voltage terminal 12 is less than 5V, only the gate oxide and source-drain of the switching transistors in the first current branch 20 and the second current branch 30 need to withstand high voltage. Low-voltage transistors can be used for the switching transistors in the current mirror circuit 40. When the voltage at the first voltage terminal 11 is high, such as 30V, and the voltage difference between the first voltage terminal 11 and the second voltage terminal 12 is greater than 5V, the gate oxide and source-drain of the switching transistors in the first current branch 20, the second current branch 30, and the current mirror circuit 40 need to withstand high voltage to achieve a wide range of high power rail variations (from the voltage at the first voltage terminal 11 to the voltage at the second voltage terminal 12). The voltage at the second voltage terminal 12 can be any voltage from the ground terminal 17 to the first voltage terminal 11. Compared to the prior art, the potential of the voltage output terminal 14 is always higher than the voltage at the second voltage terminal 12. If an inverter is connected after the voltage output terminal 14, the transistors in the inverter do not have the risk of gate oxide negative voltage breakdown.
[0038] Please refer to Figure 4 , Figure 4 for Figure 3 The circuit diagram shown illustrates one embodiment of the level conversion circuit 1. Figure 4 In the illustrated embodiment, both the first switch 21 and the second switch 23 are NMOS transistors. The input terminal 13 is connected to the gate of the first switch 21, and the gate voltage of the second switch 31 is a first voltage. The sources of both the first and second switch 21 are connected to ground, and the drains of both the first and second switch 31 are connected to the first voltage terminal. In this way, the gate-source voltage of the first switch 21 is the same as that of the second switch 32. When the first switch 21 is turned on, the relationship between the current of the first switch 21 and the current of the second switch 31 is only related to the relationship between the width-to-length ratio of the first switch 21 and the width-to-length ratio of the second switch 23.
[0039] Please refer to Figure 5 , Figure 5 This is a schematic block diagram of a level conversion circuit 1 according to another embodiment of this application. Figure 5 The illustrated embodiments and Figure 3 The illustrated embodiments are essentially the same. The difference lies in that... Figure 5In the illustrated embodiment, the first current branch 20 further includes a third switch 22, which is connected in parallel with the first switch 21. The aspect ratio of the third switch 22 is smaller than that of the second switch 31. The voltage at the input terminal 13 that controls the first switch 21 to turn on is the same as the voltage that drives the third switch 31 to turn on. Thus, when the voltage at the input terminal 13 controls the first switch 21 to turn off, the current in the first current branch 20 is the sum of the cutoff current of the first switch 21 and the on current of the third switch 22. Because the aspect ratio of the third switch 22 is smaller than that of the second switch 31, when the gate-source voltages of the third switch 22 and the second switch 31 are equal, the on current of the third switch 22 is smaller than the on current of the second switch 31, and consequently, the current in the first current branch 20 is smaller than the current in the second current branch 30.
[0040] When the voltage at input terminal 13 controls the first switch 21 to turn on, the current in the first current branch 20 is the sum of the on-state current of the first switch 21 and the on-state current of the third switch 23. Because the width-to-length ratio of the first switch 21 is greater than that of the second switch 31, and the gate-source voltages of the first switch 21, the third switch 22, and the second switch 31 are equal, the current in the first current branch 20 is greater than the current in the second current branch 30. Thus, the voltage at input terminal 13 can control the on / off state of the first switch 21, thereby reversing the relationship between the currents in the first current branch 20 and the second current branch 30.
[0041] And in Figure 4 In the illustrated embodiment, when the voltage at input terminal 13 switches from controlling the first switch 21 to controlling the first switch 21 to turn on, the current in the first current branch 20 increases from the on-state current of the third switch 22, not from the off-state current of the first switch 21 (which is approximately 0). This improves the response speed of the current in the first current branch 20 to the low-to-high voltage switching at input terminal 13, thereby improving the response speed of the voltage switching at output terminal 14 to the low-to-high voltage switching at input terminal 13. This results in a smaller delay and faster response speed for the level conversion circuit 1.
[0042] In some embodiments, the ratio of the width-to-length ratio of the first switching transistor 21, the width-to-length ratio of the third switching transistor 22, and the width-to-length ratio of the second switching transistor 31 is (n×n-1):1:n, where n is not less than 2. When the voltage at the input terminal 13 controls the first switching transistor 21 to turn off, the current in the first current branch 20 is the sum of the cutoff current of the first switching transistor 21 and the on-current of the third switching transistor 22. The ratio of the width-to-length ratio of the third switching transistor 22 to the width-to-length ratio of the second switching transistor 31 is 1:n. Therefore, the ratio of the current in the first current branch 20 to the current in the second current branch 30 is 1:n.
[0043] When the voltage at input terminal 13 controls the first switch 21 to turn on, the current in the first current branch 20 is the sum of the conduction current of the first switch 21 and the conduction current of the third switch. The ratio of the width-to-length ratio of the first switch 21, the width-to-length ratio of the third switch 22, and the width-to-length ratio of the second switch 31 is (n×n-1):1:n. Therefore, the ratio of the current in the first current branch 20 to the current in the second current branch 30 is n:1.
[0044] Therefore, by setting the ratio of the width-to-length ratio of the first switch tube 21, the width-to-length ratio of the third switch tube 22, and the width-to-length ratio of the second switch tube 31 to (n×n-1):1:n, the on / off state of the first switch tube 21 can be controlled by controlling the voltage of the control input terminal 13, thereby reversing the relationship between the current of the first current branch 20 and the current of the second current branch 30.
[0045] Please refer to Figure 6 , Figure 6 for Figure 5 The circuit diagram shown illustrates one embodiment of the level conversion circuit 1. Figure 6 In the illustrated embodiment, the first switch 21, the second switch 31, and the third switch 23 are all NMOS transistors. Input terminal 13 is connected to the gate of the first switch 21. The gate voltages of the second switch 31 and the third switch 23 are both a first voltage. The sources of the first switch 21, the second switch 31, and the third switch 23 are all connected to ground. The drains of the first switch 21, the second switch 31, and the third switch 23 are all connected to the first voltage terminal. This ensures that the gate-source voltages of the first switch 21, the second switch 31, and the third switch 23 are all the same. When the first switch 21 is not turned on, the relationship between the current in the first current branch 20 and the current in the second current branch 30 is only related to the relationship between the width-to-length ratio of the second switch 31 and the width-to-length ratio of the third switch 23. When the first switch 21 is turned on, the relationship between the current in the first current branch 20 and the current in the second current branch 30 is only related to the relationship between the width-to-length ratio of the first switch 21, the width-to-length ratio of the second switch 31, and the width-to-length ratio of the third switch 23.
[0046] In this patent application, the sources of the first switching transistor 21, the second switching transistor 31, and the third switching transistor 23 are all connected to the ground terminal, and the drains of the first switching transistor 21, the second switching transistor 31, and the third switching transistor 23 are all connected to the first voltage terminal. Therefore, the source-drain withstand voltages of the first switching transistor 21, the second switching transistor 31, and the third switching transistor 23 are adapted to the voltage difference between the first voltage terminal 11 and the ground terminal.
[0047] Please continue to refer to this. Figure 6 ,exist Figure 6 In the illustrated embodiment, the current mirror circuit includes a first current mirror 41, a second current mirror 42, and a third current mirror 43. Each of the three current mirrors includes a reference branch and a mirror branch. The reference branch of the first current mirror 41 is connected between the first voltage terminal 11 and the first current branch 20. The reference branch of the second current mirror 42 is connected between the first voltage terminal 11 and the second current branch 30. The mirror branch of the second current mirror 42 and the reference branch of the third current mirror 43 are connected in series between the first voltage terminal 11 and the second voltage terminal 12. The mirror branch of the first current mirror 41 is connected between the first voltage terminal 11 and the voltage output terminal 14. The mirror branch of the third current mirror 43 is connected between the voltage output terminal 14 and the second voltage terminal 12. Thus, the current mirror circuit 40 mirrors the current of the first current branch 20 to the area between the first voltage terminal 11 and the voltage output terminal 14, and mirrors the current of the second current branch 30 to the area between the voltage output terminal 14 and the second voltage terminal 12.
[0048] Please refer to Figure 7 , Figure 7 This is a circuit diagram of a level conversion circuit 1 according to one embodiment of this application. Figure 7 The illustrated embodiments and Figure 6 The illustrated embodiments are essentially the same. The difference lies in that... Figure 7 In the embodiment shown, the level conversion circuit 1 includes a first inverter 15 and a second inverter 16. The first inverter 15 is located between the input terminal 13 and the first switching transistor 21, and the second inverter 16 is connected to the voltage output terminal 14.
[0049] Thus, when the voltage at input terminal 13 is VCCL or close to VCCL, the voltage at the ground terminal output through the first inverter 15 is 0V, which is less than the conduction threshold voltage of the first switch 21. The first switch 21 is turned off, and the current in the first current branch 20 is less than the current in the second current branch 30. The voltage at voltage output terminal 14 approaches the voltage FGND of the second voltage terminal 12. However, because the switch in the current mirror circuit 40 located between voltage output terminal 14 and the second voltage terminal 12 has a conduction voltage, the voltage at voltage output terminal 14 will not be equal to the voltage FGND of the second voltage terminal 12. Instead, it will be equal to the sum of the voltage FGND of the second voltage terminal 12 and the conduction voltage of the switch in the current mirror circuit 40 located between the first voltage terminal 11 and the voltage output terminal. The voltage at voltage source terminal 14, after passing through the second inverter 16, outputs the voltage VCCH of the first voltage terminal 11.
[0050] When the voltage at input terminal 13 is 0V or close to 0V, the output VCCL after passing through the first inverter 15 is greater than the conduction threshold voltage of the first switch 21. The first switch 21 conducts, and the current in the first current branch 20 is greater than the current in the second current branch 30. The voltage at voltage output terminal 14 approaches the voltage VCCH of the first voltage terminal 11. However, because the switch in the current mirror circuit 40 located between the first voltage terminal 11 and the voltage output terminal 14 has a conduction voltage, the voltage at voltage output terminal 14 will not be equal to the voltage at the first voltage terminal 11. Instead, it will be equal to the difference between the voltage at the first voltage terminal 11 and the conduction voltage of the switch in the current mirror circuit 40 located between the first voltage terminal 11 and the voltage output terminal 14. The voltage at voltage source terminal 14, after passing through the second inverter 16, outputs the voltage FGND of the second voltage terminal 11.
[0051] In summary, by setting the first inverter 15 and the second inverter 16, when the voltage at the input terminal 13 is the first voltage VCCL or close to VCCL, the voltage output by the second inverter 16 is the voltage VCCH at the first voltage terminal 11. When the voltage at the input terminal 13 is the voltage at the ground terminal or close to the ground terminal, the voltage output by the second inverter 16 is the voltage FGND at the second voltage terminal 12, thus realizing the level conversion of the signal from the low power rail of GND~VCCL to the high power rail of FGND~VCCH.
[0052] In other embodiments, the number of first inverters 15 is odd, the number of second inverters 16 is odd, the odd number of first inverters 15 are connected in series, and the odd number of second inverters 16 are connected in series. The effect of an odd number of first inverters 15 connected in series is the same as that of a single first inverter 15, and the effect of an odd number of second inverters 16 connected in series is the same as that of a single second inverter 16. This embodiment is... Figure 7 The level conversion circuit 1 shown is a variation.
[0053] Please continue to refer to this. Figure 6 ,exist Figure 6 In the illustrated embodiment, a current source 50 is also included. One end of the current source 50 is connected to both the first current branch 20 and the second current branch 30, and the other end of the current source 50 is connected to the ground terminal 17. Thus, the sum of the current in the first current branch 20 and the current in the second current branch 30 is the current of the current source 50. The energy consumption of the level conversion circuit is limited by the current source 50, and energy consumption can be controlled.
[0054] exist Figure 6In the embodiment shown, the current source 50 includes a reference current generating circuit 54 and a fourth current mirror 51. The fourth current mirror 51 includes a fourth switch 52 and a fifth switch 53 connected to each other. The reference current generating circuit 54 and the fourth switch 52 are connected. The fifth switch 53 is connected to both the first current branch 20 and the second current branch 30. The width-to-length ratio of the fourth switch 52 is equal to the width-to-length ratio of the fifth switch 53.
[0055] Thus, by including a reference current generation circuit 54 and a fourth current mirror 51 in the current source 50, the fourth current mirror 51 can introduce the reference current Iref generated by the reference current generation circuit 54 between the first current branch 20, the second current branch 30, and the ground terminal. The sum of the current in the first current branch 20 and the current in the second current branch 30 is the reference current of the reference current generation circuit 54. The power consumption of the level conversion circuit is limited by the reference current generated by the reference current generation circuit 54, and the power consumption can be controlled.
[0056] Please refer to Figure 8 , Figure 8 This is a circuit diagram of a level conversion circuit 1 according to one embodiment of this application. Figure 8 The illustrated embodiments and Figure 6 The illustrated embodiments are essentially the same. The difference lies in that... Figure 8 In the illustrated embodiment, the level shifting circuit 1 further includes a resistor 55. One end of the resistor 55 is connected to both the first current branch 20 and the second current branch 30, and the other end of the resistor 55 is connected to the ground terminal 17. Thus, the bias current can be set by configuring the resistor 55. This is similar to how a stable current can be achieved when a switching transistor operates in the saturation region. Figure 8 In the embodiment shown, based on the ohmic characteristics of resistor 55, if the voltage across resistor 55 is relatively stable, a stable current can also be obtained. Furthermore, using resistor 55 is simpler than using a switching transistor circuit, and it also has a current limiting effect.
[0057] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0058] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A level conversion circuit, characterized in that, include: The system comprises a first voltage terminal, a second voltage terminal, an input terminal, a first current branch, a second current branch, a current mirror circuit, and a voltage output terminal. The voltage at the first voltage terminal is greater than the voltage at the second voltage terminal. The first current branch includes a first switching transistor, and the second current branch includes a second switching transistor. The aspect ratio of the first switching transistor is greater than that of the second switching transistor. Both the first and second current branches are connected between the first voltage terminal and the ground terminal. The input terminal is connected to the first switching transistor. The voltage at the input terminal is used to control the switching on and off of the first switching transistor, and the voltage controlling the first switching transistor to conduct is the same as the voltage driving the second switching transistor to conduct, so that the magnitude relationship between the first and second current branches is reversed. The current mirror circuit is connected to both the first and second current branches. The current mirror circuit is used to mirror the current of the first current branch and the current of the second current branch to the area between the first voltage terminal and the voltage output terminal, and the area between the voltage output terminal and the second voltage terminal, respectively.
2. The level conversion circuit according to claim 1, characterized in that, The voltage at the input terminal includes a first voltage and a second voltage. The first voltage is greater than the second voltage. When the voltage at the input terminal is the first voltage, the first switch is turned on. When the voltage at the input terminal is the second voltage, the first switch is turned off. The first voltage is the same as the voltage that drives the second switch to turn on.
3. The level conversion circuit according to claim 1, characterized in that, When the first switch is off, the current in the second current branch is greater than the current in the first current branch and the current in the second current branch is a times the current in the first current branch, where a is not less than 2; when the first switch is on, the current in the first current branch is greater than the current in the second current branch and the current in the first current branch is b times the current in the second current branch, where b is not less than 2.
4. The level conversion circuit according to claim 2, characterized in that, The first current branch also includes a third switch, which is connected in parallel with the first switch. The width-to-length ratio of the third switch is smaller than that of the second switch. The voltage at the input terminal that controls the first switch to turn on is the same as the voltage that drives the third switch to turn on.
5. The level conversion circuit according to claim 4, characterized in that, The ratio of the width-to-length ratio of the first switch transistor, the width-to-length ratio of the third switch transistor, and the width-to-length ratio of the second switch transistor is (n×n-1):1:n, where n is not less than 2.
6. The level conversion circuit according to claim 4, characterized in that, The first, second, and third switching transistors are all NMOS transistors. The input terminal is connected to the gate of the first switching transistor. The gate voltage of the second and third switching transistors is the first voltage. The source of the first, second, and third switching transistors is connected to the ground terminal. The drain of the first, second, and third switching transistors is connected to the first voltage terminal.
7. The level conversion circuit according to claim 1, characterized in that, The current mirror circuit includes a first current mirror, a second current mirror, and a third current mirror. Each of the first, second, and third current mirrors includes a reference branch and a mirror branch. The reference branch of the first current mirror is connected between the first voltage terminal and the first current branch. The reference branch of the second current mirror is connected between the first voltage terminal and the second current branch. The mirror branch of the second current mirror and the reference branch of the third current mirror are connected in series between the first voltage terminal and the second voltage terminal. The mirror branch of the first current mirror is connected between the first voltage terminal and the voltage output terminal. The mirror branch of the third current mirror is connected between the voltage output terminal and the second voltage terminal.
8. The level conversion circuit according to claim 1, characterized in that, The level conversion circuit includes a first inverter and a second inverter. The first inverter is located between the input terminal and the first switching transistor, and the second inverter is connected to the voltage output terminal.
9. The level conversion circuit according to claim 8, characterized in that, The number of first inverters is odd, the number of second inverters is odd, the odd number of first inverters are connected in series, and the odd number of second inverters are connected in series.
10. The level conversion circuit according to claim 1, characterized in that, It also includes a current source, one end of which is connected to both the first current branch and the second current branch, and the other end of which is connected to the grounding terminal.
11. The level conversion circuit according to claim 10, characterized in that, The current source includes a reference current generating circuit and a fourth current mirror. The fourth current mirror includes a fourth switch and a fifth switch connected to each other. The reference current generating circuit is connected to the fourth switch. The fifth switch is connected to both the first current branch and the second current branch. The width-to-length ratio of the fourth switch is equal to the width-to-length ratio of the fifth switch.
12. The level conversion circuit according to claim 1, characterized in that, The level conversion circuit further includes a resistor, one end of which is connected to both the first current branch and the second current branch, and the other end of which is connected to the ground terminal.