Level shift enable latch

Abstract

This invention provides a level-shifting enable latch, comprising a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. When the latch enable signal is set to a first logic value, the latch circuit sets a second data output signal in response to the first data output signal, and latches the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. The latch circuit includes a first control circuit. The first control circuit enables the latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.

Description

Technical Field

[0001] This invention relates to a latch design, and more specifically, to a level converting enable latch. Background Technology

[0002] Latches are widely used circuit elements for temporarily storing data from a first logic circuit and transferring that data to a second logic circuit. In some applications, integrated circuits (e.g., microprocessors) may have multiple power domains, such as a power-down domain and an always-on (AON) domain. The power to the power-down domain can be turned off to reduce power consumption. Generally, it is required that essential logic be placed in the AON domain. Consider the case where the first logic circuit operates in the power-down domain and the second logic circuit operates in the AON domain. Data from the first logic circuit needs to be transferred to the second logic circuit before the power to the power-down domain is turned off. Therefore, an innovative latch design is needed to handle data transfer between different power domains. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide an innovative level-shifting enable latch capable of handling data transfer between different power domains.

[0004] According to a first aspect of the present invention, an exemplary level-shifting enable latch is disclosed. The exemplary level-shifting enable latch includes a level shifter circuit and a latch circuit. The level shifter circuit is configured to receive a first data input signal, generate and output a first data output signal, wherein the voltage swing of the first data output signal is different from the voltage swing of the first data input signal. When a latch enable signal is set to a first logic value, the latch circuit receives the first data output signal and sets a second data output signal in response to the first data output signal, and latches the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. The latch circuit includes a first control circuit. The first control circuit is configured to enable the latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disable the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.

[0005] According to a second aspect of the present invention, an exemplary level-shifting enable latch is disclosed. The exemplary level-shifting enable latch includes a level-shifting circuit and a latch circuit. The level-shifting circuit is configured to receive a first data input signal, generate and output a first data output signal, wherein the voltage swing of the first data output signal is different from the voltage swing of the first data input signal. When a latch enable signal is set to a first logic value, the latch circuit receives the first data output signal and sets a second data output signal in response to the first data output signal, and latches the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. The level-shifting circuit includes a first transistor, a second transistor, a first bottom transistor, and a second bottom transistor. The first transistor has a control terminal for receiving the first data input signal. The control terminal of the second transistor is arranged to receive a second data input signal that is an inverted version of the first data input signal. The first bottom transistor has a first connection terminal coupled to a first connection point and a second connection terminal coupled to a reference voltage. When the latch enable signal is set to a first logic value, the first bottom transistor is turned on; when the latch enable signal is set to a second logic value, the first bottom transistor is turned off. The second bottom transistor has a first connection terminal coupled to a first connection point and a second connection terminal coupled to a reference voltage. When the latch enable signal is set to the first logic value, the second bottom transistor is turned on; when the latch enable signal is set to the second logic value, the second bottom transistor is turned off. The second connection terminal of the second transistor is used to output a first data output signal.

[0006] According to a third aspect of the present invention, an exemplary level-shifting enable latch is disclosed. The exemplary level-shifting enable latch includes a level-shifting circuit and a latch circuit. The level-shifting circuit receives a first data input signal, generates and outputs a first data output signal, wherein the voltage swing of the first data output signal is different from the voltage swing of the first data input signal. When a latch enable signal is set to a first logic value, the latch circuit receives the first data output signal and sets a second data output signal in response to the first data output signal; when the latch enable signal is set to a second logic value different from the first logic value, the second data output signal is latched. The level-shifting circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor has a control terminal for receiving the first data input signal. The second transistor has a control terminal coupled to the control terminal of the first transistor and a first connection terminal coupled to the connection terminal of the first transistor. The third transistor has a connection terminal for outputting the first data output signal. The fourth transistor has a control terminal coupled to the control terminal of the third transistor and its first connection terminal coupled to the connection terminal of the third transistor. The fifth transistor has a control terminal coupled to the connection terminal of the third transistor, a first connection terminal coupled to the second connection terminal of the second transistor, and a second connection terminal coupled to a reference voltage. The sixth transistor has a control terminal coupled to the connection terminal of the first transistor, a first connection terminal coupled to the second connection terminal of the fourth transistor, and a second connection terminal coupled to a reference voltage. The first connection terminal of the seventh transistor is coupled to the second connection terminal of the fourth transistor, and the second connection terminal is coupled to the reference voltage. The seventh transistor is off when the latch enable signal is set to a first logic value, and on when the latch enable signal is set to a second logic value. The latch circuit includes a multiplexer. The first input node of the multiplexer is used to receive the internal signal of the latch circuit, the second input node is used to receive the second data input signal which is inverted by the first data input signal, and the output node is used to output the multiplexer output signal to the control terminal of the third transistor and the control terminal of the fourth transistor. When the latch enable signal is set to the second logic value, the multiplexer selects the internal signal as the multiplexer output signal, and when the latch enable signal is set to the first logic value, the multiplexer selects the second data input signal as the multiplexer output signal.

[0007] The level conversion enable latch of the present invention can handle data transmission and latching between different power domains.

[0008] These and other objects of the invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating the basic architecture of a level-shifting enable latch proposed according to an embodiment of the present invention.

[0010] Figure 2 This is a circuit diagram of a first level-shifting enable latch design according to an embodiment of the present invention.

[0011] Figure 3 This is an example of an embodiment of the present invention. Figure 2 A schematic diagram of an alternative design for the level converter circuit used in the level conversion enable latch 200 shown.

[0012] Figure 4 This is a schematic diagram illustrating an operational scenario of a high-enable type latch according to an embodiment of the present invention.

[0013] Figure 5 This is a circuit diagram of a second level-shifting enable latch design according to an embodiment of the present invention.

[0014] Figure 6 This is a schematic diagram illustrating an operational scenario of a low-enable type latch according to an embodiment of the present invention.

[0015] Figure 7 This is a circuit diagram of a third level-shifting enable latch design according to an embodiment of the present invention.

[0016] Figure 8 This is a description of an embodiment of the present invention. Figure 7 The diagram shows an alternative design for the level shifter circuit used by the level shifter enable latch shown.

[0017] Figure 9 This is a circuit diagram of the fourth level conversion enable latch design according to an embodiment of the present invention.

[0018] Figure 10 This is a description of an embodiment of the present invention. Figure 9 The diagram shows an alternative design for the level shifter circuit in the level shift enable latch.

[0019] Figure 11 This is a circuit diagram of a fifth level-shifting enable latch design according to an embodiment of the present invention.

[0020] Figure 12 This is a circuit diagram of a sixth level-shifting enable latch design according to an embodiment of the present invention. Detailed Implementation

[0021] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The term "comprising" throughout the specification and subsequent claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0022] The following description is intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention should be determined by referring to the appended claims.

[0023] Figure 1 This is a schematic diagram illustrating the basic architecture of a level-converting enable latch according to an embodiment of the present invention. The level-converting enable latch (LCE_Latch) 100 includes a level-converting circuit 102 and a latch circuit 104. It should be noted that the level-converting enable latch 100 may also include additional circuit elements, depending on the actual design. The level-converting enable latch 100 receives a data input signal I from logic circuitry in a first power domain (e.g., a power-down domain 10 with power supply voltage VDD1) and generates a data output signal Q to logic circuitry in a second power domain (e.g., an AON domain 20 with power supply voltage VDD2). For example, the level-converting circuit 102 is powered by power supply voltage VDD2, receives the data input signal I (also referred to as the first data input signal) from logic circuitry in power-down domain 10, and generates the data output signal Q based on the data input signal I. LS (Also referred to as the first data output signal). Specifically, the level converter circuit 102 is used to convert the voltage difference between the power supply voltages VDD1 and VDD2, so that the data input signal I of the level converter circuit 102 has a voltage swing (VDD1-VSS) and the data output signal I of the level converter circuit 102. LS It has a voltage swing (VDD2-VSS), where VSS is the ground voltage. The latch circuit 104 is powered by the power supply voltage VDD2. The latch circuit 104 is used to receive the data output signal I from the level converter circuit 102. LS And when the latch enable signal E is set to the first logic value, it responds to the received data output signal I. LSThe latch circuit 104 is used to set the data output signal Q (also referred to as the second data output signal), and further to latch the data output signal Q when the latch enable signal E is set to a second logic value different from the first logic value. In other words, when the latch enable signal E is set to the first logic value, the data output signal Q can change with the data input signal I, while when the latch enable signal E is set to the second logic value, the data output signal Q will maintain the logic value obtained from the data input signal I when the latch enable signal E changes from the first logic value to the second logic value.

[0024] In some embodiments, latch circuit 104 may have a latch feedback loop that can be selectively enabled or disabled under the control of latch enable signal E. In some embodiments, the footer transistors of level shifter circuit 102, initially used for electrostatic discharge (ESD) protection, can be reused to disable the cross-coupled function. Because the footer transistors of level shifter circuit 102 are reused, the number of transistors in level shifter enable latch 100 can be reduced, resulting in lower dynamic power consumption for level shifter enable latch 100. In some embodiments, the quasi-inverter of level shifter circuit 102 can be reused as a latch feedback inverter. Because the quasi-inverter of level shifter circuit 102 is reused, the number of transistors in level shifter enable latch 100 can be reduced, resulting in lower dynamic power consumption for level shifter enable latch 100. Furthermore, since the quasi-inverter of the level shifter circuit 102 is reused as a latch feedback inverter located in the leakage path between VDD2 and VSS, latch leakage power can be reduced in the case of VDD1 power failure. Details of the proposed level shifting enable latch 100 are described below with reference to the accompanying drawings.

[0025] Figure 2 This is a circuit diagram of a first level-shifting enable latch designed according to an embodiment of the present invention. The level-shifting enable latch 200 follows the following... Figure 1The architecture shown includes a level shifter circuit 202 and a latch circuit 204. Furthermore, the level shifting enable latch 200 may also include signal generation circuits 206 and 208, which act as buffers to provide cleaner data input signals and cleaner latch enable signals. Signal generation circuit 206 operates according to different reference voltages (including power supply voltage VDD1 and ground voltage VSS) and has multiple P-channel metal-oxide semiconductor (PMOS) transistors MP1, MP2 and multiple N-channel metal-oxide semiconductor (NMOS) transistors MN1, MN2. In this embodiment, signal generation circuit 206 includes an inverter composed of PMOS transistor MP1 and NMOS transistor MN1, and another inverter composed of PMOS transistor MP2 and NMOS transistor MN2. Therefore, the signal generation circuit 206 generates a data input signal ib based on the data input signal I provided by the logic circuit located in the power domain (e.g., the power-down domain) having a power supply voltage VDD1, and also generates a data input signal ibb based on the data input signal ib, wherein the data input signal ib is the inverse signal of the data input signal I (i.e., The data input signal ibb is the inverted signal of the data input signal ib (i.e., Alternatively, the signal generation circuit 206 can be modified to omit the PMOS transistor MP2 and NMOS transistor MN2, so that the data input signal I and its inverted signal (i.e., the data input signal ib) can be used in the level shifter circuit 202.

[0026] The signal generation circuit 208 can operate according to different reference voltages, including the power supply voltage VDD2 (VDD2≠VDD1) of another power domain (e.g., the AON domain) and the ground voltage VSS. The signal generation circuit 208 includes multiple PMOS transistors MP3, MP4 and multiple NMOS transistors MN3, MN4. In this embodiment, the signal generation circuit 208 includes an inverter composed of PMOS transistor MP3 and NMOS transistor MN3, and another inverter composed of PMOS transistor MP4 and NMOS transistor MN4. Therefore, the signal generation circuit 208 generates a latch enable signal eb based on the latch enable signal E, and generates a latch enable signal ebb based on the latch enable signal eb, wherein the latch enable signal eb is the inverse of the latch enable signal E (i.e., ...). The latch enable signal ebb is the inverse of the latch enable signal eb (i.e., Alternatively, the signal generation circuit 208 can be modified to omit the PMOS transistor MP4 and NMOS transistor MN4, so that the latch circuit 204 can use the latch enable signal E and the inverted version of the latch enable signal (i.e., the latch enable signal eb).

[0027] The level converter circuit 202 is used to receive the data input signal ibb and generate and output the data output signal I. LS In this embodiment, the data output signal I LS This can be viewed as a level-shifted version of the inverted signal of the data input signal ibb, i.e., a level-shifted version of the data input signal ib. Specifically, the data input signal ibb of the level converter circuit 202 has a voltage swing (VDD1-VSS), while the data output signal I of the level converter circuit 202... LS It has a voltage swing (VDD2-VSS). In this embodiment, the level shifter circuit 202 adopts a cross-coupled level shifter architecture, thus supporting both VDD1 > VDD2 and VDD1 < VDD2. Figure 2 As shown, the level shifter circuit 202 includes PMOS transistors MP5, MP6, MP7, MP8 and NMOS transistors MN5, MN6, and also includes optional NMOS transistors MN7, MN8, wherein NMOS transistors MN7, MN8 serve as footer transistors for ESD protection.

[0028] Each of the PMOS and NMOS transistors has a control terminal (e.g., a gate terminal) and two connection terminals (e.g., a source terminal and a drain terminal). According to the cross-coupling architecture, the source terminal of PMOS transistor MP5 is coupled to the power supply voltage VDD2, its drain terminal is coupled to the source terminal of PMOS transistor MP7, and its gate terminal is coupled to the drain terminal of NMOS transistor MN6; the source terminal of PMOS transistor MP6 is coupled to the power supply voltage VDD2, its drain terminal is coupled to the source terminal of PMOS transistor MP8, and its gate terminal is coupled to the drain terminal of NMOS transistor MN5. Furthermore, the drain terminal of PMOS transistor MP7 is coupled to the drain terminal of NMOS transistor MN5, and its gate terminal is coupled to the gate terminal of NMOS transistor MN5. The drain terminal of PMOS transistor MP8 is coupled to the drain terminal of NMOS transistor MN6, and its gate terminal is coupled to the gate terminal of NMOS transistor MN6. The gate terminal of NMOS transistor MN5 receives the data input signal. The gate of NMOS transistor MN6 receives the data input signal ibb (ibb = I), and the source of NMOS transistor MN5 is coupled to the source of NMOS transistor MN6. NMOS transistors MN7 and MN8 act as bottom transistors for ESD protection. The drain of NMOS transistor MN7 is coupled to the source of NMOS transistor MN5, which is coupled to ground voltage VSS. Its gate receives a high bias voltage tieH, meaning that in normal mode, NMOS transistor MN7 is turned on by the high bias voltage tieH. The drain of NMOS transistor MN8 is coupled to the source of NMOS transistor MN6, which is coupled to ground voltage VSS. Its gate receives a high bias voltage tieH, meaning that in normal mode, NMOS transistor MN8 is turned on by the high bias voltage tieH.

[0029] Figure 2 The circuit design of the level converter circuit 202 shown is for illustrative purposes only and is not intended to limit the invention. In some embodiments, the level converter circuit 202 may be modified to employ another cross-coupled level converter architecture. Figure 3 This is an example of an embodiment of the present invention. Figure 2 A schematic diagram of an alternative design for the level converter circuit 202 used by the level conversion enable latch 200 shown. Figure 2 The level converter circuit 202 shown can be derived from... Figure 3 The level shifter circuit 300 shown is used instead. The main difference between level shifter circuits 202 and 300 is that level shifter circuit 300 does not include the PMOS transistors MP7 and MP8 included in level shifter circuit 202.

[0030] As described above, NMOS transistors MN7 and MN8 act as bottom transistors for ESD protection. In some embodiments, the level shifter circuit 202 / 300 can be modified to omit NMOS transistors MN7 and MN8 and directly connect the source terminals of NMOS transistors MN5 and MN6 to the ground voltage VSS.

[0031] Data output signal I LS It is a level-shifted version of the inverted data input signal Ibb. The latch circuit 204 is configured to receive the data output signal I. LS And when the latch enable signal E is set to logic value 1, it responds to the data output signal I. LS The data output signal Q is set, and when the latch enable signal E is set to another logic value of 0, the data output signal Q is latched. In the data output signal I... LS After being latched by latch circuit 204, the power supply voltage VDD1 can be turned off to save power. For example... Figure 2As shown, the latch circuit 204 includes multiple control circuits 210, 212 and multiple inverters 214, 216.

[0032] Control circuit 210 (also referred to as the second control circuit) includes multiple PMOS transistors MP9 and MP10 and multiple NMOS transistors MN9 and MN10. The source terminal of PMOS transistor MP9 is coupled to the power supply voltage VDD2, and the gate terminal receives the data output signal I. LS The drain terminal of PMOS transistor MP10 is coupled to the source terminal of PMOS transistor MP10. The gate terminal of PMOS transistor MP10 receives the latch enable signal eb, and its drain terminal is coupled to the drain terminal of NMOS transistor MN9. The gate terminal of NMOS transistor MN9 receives the latch enable signal ebb, and its source terminal is coupled to the drain terminal of NMOS transistor MN10. The gate terminal of NMOS transistor MN10 receives the data output signal I. LS The source terminal is coupled to ground voltage VSS.

[0033] When the latch enable signal E is set to logic 1, the latch enable signal eb has logic 0, and the latch enable signal ebb has logic 1. Therefore, both the PMOS transistor MP10 and the NMOS transistor MN9 in the control circuit 210 are turned on, and the inverter composed of the PMOS transistor MP9 and the NMOS transistor MN9 becomes active, outputting the data signal I. LS The inverting phase generates the data output signal IB at the drain terminals of PMOS transistor MP10 and NMOS transistor MN9. LS (Also known as the second data output signal), where the data output signal IB LS It is the data output signal I LS The inversion of the latch enable signal E. In other words, when the latch enable signal E is set to logic 1, the control circuit 210 enables the data output signal I to be received. LS The data output signal IB is obtained from this. LS .

[0034] When the latch enable signal E is set to logic 0, the latch enable signal eb has logic 1, and the latch enable signal ebb has logic 0. Therefore, control circuit 210 is disabled because both PMOS transistor MP10 and NMOS transistor MN9 are turned off. In other words, when the latch enable signal E is set to logic 0, control circuit 210 prevents data output signal I from being received. LS The data output signal IB is obtained from this. LS .

[0035] In response to the data output signal IB via inverters 214 and 216 LSThe data output signal Q is set. The inverter 214 consists of a PMOS transistor MP11 and an NMOS transistor MN11, and has an input node N1 for receiving the data output signal IB. LS Inverter 216 consists of PMOS transistor MP12 and NMOS transistor MN12, and has an input node N3 coupled to the output node N2 of inverter 214, and an output node N4 for outputting the data output signal Q.

[0036] The control circuit 212 (also referred to as the first control circuit) includes multiple PMOS transistors MP13 and MP14 and multiple NMOS transistors MN13 and MN14. The source terminal of PMOS transistor MP13 is coupled to the power supply voltage VDD2, its gate terminal is coupled to the output node N2 of inverter 214, and its drain terminal is coupled to the source terminal of PMOS transistor MP14. The gate terminal of PMOS transistor MP14 receives a latch enable signal ebb, and its drain terminal is coupled to the drain terminal of NMOS transistor MN13. The gate terminal of NMOS transistor MN13 receives a latch enable signal eb, and its source terminal is coupled to the drain terminal of NMOS transistor MN14. The gate terminal of NMOS transistor MN14 is coupled to the output node N2 of inverter 214, and its source terminal is coupled to ground voltage VSS.

[0037] When the latch enable signal E is set to logic 1, the latch enable signal eb has logic 0, while the latch enable signal ebb has logic 1. Therefore, since both PMOS transistor MP14 and NMOS transistor MN13 are off, control circuit 212 disables the latch feedback loop 215. When the latch enable signal E is set to logic 0, the latch enable signal eb has logic 1, while the latch enable signal ebb has logic 0. Therefore, since both PMOS transistor MP14 and NMOS transistor MN13 are on, control circuit 212 enables (activates) the latch feedback loop 215, and control circuit 212 also has an effective inverter (composed of PMOS transistor MP13 and NMOS transistor MN14) for inverting the output signal of inverter 214 to set the input signal of inverter 214 (i.e., the data output signal IB). LS ).

[0038] In this embodiment, the latch circuit 204 is a high-enable type latch. When E = ebb = 1 and eb = 0, the latch feedback loop 215 is cut off, and the control circuit 210 outputs the data signal I... LS (It is the output of the level converter circuit 202) Inverting the input signal of the inverter 214 sets the input signal of the inverter 214, so that by controlling the control circuit 210 and the inverters 214 and 216, the data output signal I can be responded to. LSThe data output signal Q is set. When E = ebb = 0 and eb = 1, the control circuit 210 prevents the input signal of the inverter 214 from being affected by the level converter circuit 202, and the latch feedback loop 215 is enabled, so that the data output signal Q is latched through the control circuit 212 and the inverters 214 and 216.

[0039] Figure 4 This is a schematic diagram illustrating an operational scenario of a high-enable type latch according to an embodiment of the present invention. During the period when the latch enable signal E is set to a logic value of 1, the data output signal Q is set in response to the data input signal I. During the period when the latch enable signal E is set to a logic value of 0, the data output signal Q is latched regardless of the data input signal I. Because the data output signal Q is latched, the power supply voltage VDD1 in the power-down domain can be turned off to save power.

[0040] Figure 5 This is a circuit diagram of a second level-shifting enable latch design according to an embodiment of the present invention. The level-shifting enable latch 500 follows... Figure 1 The architecture is shown. The main difference between level-shifting enable latches 500 and 200 is that the gate of the PMOS transistor MP10 of the control circuit 510 in latch circuit 504 is used to receive the latch enable signal ebb; the gate of the NMOS transistor MN9 of the control circuit 510 in latch circuit 504 is used to receive the latch enable signal eb; the gate of the PMOS transistor MP14 of the control circuit 512 in latch circuit 504 receives the latch enable signal eb; and the gate of the NMOS transistor MN13 of the control circuit 512 in latch circuit 504 receives the latch enable signal ebb.

[0041] In this embodiment, the latch circuit 504 is a low-enable type latch. When E = ebb = 0 and eb = 1, the latch feedback loop 215 is cut off, and the control circuit 510 outputs the data signal I... LS (It is the output of the level converter circuit 202) Inverting the input signal of the inverter 214 to set the input signal, thereby controlling the control circuit 510 and the inverters 214 and 216 in response to the data output signal I. LS The data output signal Q is set. When E = ebb = 1 and eb = 0, the control circuit 510 prevents the input signal of the inverter 214 from being affected by the level converter circuit 202, and the latch feedback loop 215 is enabled, so that the data output signal Q is latched through the control circuit 512 and the inverters 214 and 216.

[0042] Figure 6This is a schematic diagram illustrating an operational scenario of a low-enable type latch according to an embodiment of the present invention. During the time period when the latch enable signal E is set to a logic value of 0, the data output signal Q is set in response to the data input signal I. During the time period when the latch enable signal E is set to a logic value of 1, the data output signal Q is latched, regardless of the data input signal I. Because the data output signal Q is latched, the power supply voltage VDD1 in the power-down domain can be turned off to save power.

[0043] Figure 7 This is a circuit diagram of a third level-shifting enable latch design according to an embodiment of the present invention. The level-shifting enable latch 700 follows... Figure 1 The architecture shown includes a level shifter circuit 702 and a latch circuit 704. Furthermore, the level shifter enable latch 700 may also include the aforementioned signal generation circuits 206 and 208, where signal generation circuits 206 and 208 act as buffers to provide a cleaner data input signal and a cleaner latch enable signal. However, this does not imply limitation of the invention. Alternatively, signal generation circuit 206 can be modified to omit PMOS transistor MP2 and NMOS transistor MN2, allowing level shifter circuit 702 to use data input signal I and its inverted signal (i.e., data input signal ib). Similarly, signal generation circuit 208 can be modified to omit PMOS transistor MP4 and NMOS transistor MN4, allowing latch circuit 704 to use latch enable signal E and its inverted signal (i.e., latch enable signal eb), and level shifter circuit 702 to use latch enable signal E.

[0044] The level converter circuit 702 is used to receive the data input signal ibb and generate and output the data output signal I. LS In this embodiment, the data output signal I LS This can be viewed as a level-shifted version of the data input signal ibb. Specifically, the data input signal ibb of the level converter circuit 702 has a voltage swing (VDD1-VSS), while the data output signal I of the level converter circuit 702... LS The voltage swing is (VDD2 - VSS). In this embodiment, the level converter circuit 702 adopts a cross-coupled level converter architecture, thus supporting both VDD1 > VDD2 and VDD1 < VDD2. Figure 7As shown, the level shifter circuit 702 includes PMOS transistors MP5, MP6, MP7, MP8, and MP15, and NMOS transistors MN5, MN6, MN7, and MN8, where NMOS transistors MN7 and MN8 can act as bottom transistors for ESD protection. The main difference between level shifter circuits 702 and 202 is that the data input signal ibb is received by the gates of PMOS transistors MP7 and MN5, the data input signal ib is received by the gates of PMOS transistors MP8 and MN6, and the latch enable signal ebb is received by the gates of NMOS transistors MN7 and MN8. The source terminal of the additional PMOS transistor MP15 is coupled to the power supply voltage VDD2, the drain terminal is coupled to the drain terminal of NMOS transistor MN5, and the gate terminal receives the latch enable signal ebb.

[0045] When the latch enable signal E is set to logic 1, the latch enable signal ebb has a logic value of 1. Therefore, PMOS transistor MP15 is turned off and NMOS transistors MN7 and MN8 are turned on, allowing the level shifter circuit 702 to operate normally, level-shifting the data input signal ibb to set the data output signal I. LS However, when the latch enable signal E is set to logic 0, the latch enable signal ebb has a logic value of 0. Therefore, NMOS transistors MN7 and MN8 are turned off, thus disabling the specified level shifting function of the level shifter circuit 702. Furthermore, to prevent leakage caused by the unknown state of the level shifter circuit 702 when NMOS transistors MN7 and MN8 are turned off, PMOS transistor MP15 is turned on to couple the supply voltage VDD2 to a cross-coupled path. In other words, PMOS transistor MP15 is controlled by the latch enable signal ebb to reduce leakage.

[0046] More specifically, NMOS transistors MN7 and MN8 (which originally served as bottom transistors for ESD protection) can be reused to replace Figure 2 The control circuit 210 is shown in the diagram. Therefore, latch circuit 704 can be obtained by removing control circuit 210 from latch circuit 204, such that when latch feedback loop 215 is disabled by control circuit 212, the data output signal I output by level converter circuit 702 is... LS The data output signal I output by the level converter circuit 702 is set by inverting the output signal of the inverter 214 when the latch feedback loop 215 is enabled by the control circuit 212, and received by the input node N1 of the inverter 214. LSSpecifically, when the latch enable signal E is set to logic 1, the latch enable signal eb has logic 0, while the latch enable signal ebb has logic 1. Therefore, since both PMOS transistor MP14 and NMOS transistor MN13 are turned off, control circuit 212 disables latch feedback loop 215. When the latch enable signal E is set to logic 0, the latch enable signal eb has logic 1, while the latch enable signal ebb has logic 0. Therefore, since both PMOS transistor MP14 and NMOS transistor MN13 are turned on, control circuit 212 enables latch feedback loop 215 and causes the inverter (composed of PMOS transistor MP13 and NMOS transistor MN14, used to invert the output signal of inverter 214) to set the input signal of inverter 214 (i.e., data output signal I). LS ).

[0047] Figure 7 The circuit design of the level converter circuit 702 shown is for illustrative purposes only and is not intended to limit the invention. In some embodiments, the level converter circuit 702 may be modified to employ another cross-coupled level converter architecture. Figure 8 This is a description of an embodiment of the present invention. Figure 7 The diagram shows an alternative design of the level converter circuit 702 used by the level conversion enable latch 700 shown. Figure 7 The level converter circuit 702 shown can be replaced with Figure 8 The level converter circuit 800 is shown. The main difference between level converter circuits 702 and 800 is that level converter circuit 800 does not include the PMOS transistors MP7 and MP8 found in level converter circuit 702.

[0048] In this embodiment, the latch circuit 704 is a high-enable type latch. When E = ebb = 1 and eb = 0, the latch feedback loop 215 is turned off, and the bottom transistors MN7 and MN8 are turned on, enabling the level converter circuit 702 to operate normally, thereby generating and outputting the data output signal I. LS And the data output signal I is responded to by inverters 214 and 216. LS Set the data output signal Q. When E = ebb = 0 and eb = 1, the bottom transistors MN7 and MN8 are turned off to disable the cross-coupling function, and the latch feedback loop 215 is enabled, so that the data output signal Q is latched through the control circuit 212 and the inverters 214 and 216.

[0049] like Figure 4As shown, while the latch enable signal E is set to logic 1, the data output signal Q is set in response to the data input signal I; and while the latch enable signal E is set to logic 0, the data output signal Q is latched regardless of the data input signal I. Because the data output signal Q is latched, the power supply voltage VDD1 in the power-down domain can be turned off to save power.

[0050] Figure 9 This is a circuit diagram of a fourth level-shifting enable latch design according to an embodiment of the present invention. The level-shifting enable latch 900 follows... Figure 1 The architecture is shown. The main difference between level shifting enable latches 900 and 700 is that the latch enable signal eb is received by the gates of NMOS transistors MN7 and MN8 and PMOS transistor MP15 in level shifter circuit 902, the gate of PMOS transistor MP14 in control circuit 512 of latch circuit 904 is arranged to receive the latch enable signal eb, and the gate of NMOS transistor MN13 in control circuit 512 used by latch circuit 904 is arranged to receive the latch enable signal ebb.

[0051] Figure 9 The circuit design of the level converter circuit 902 shown is for illustrative purposes only and is not intended to limit the invention. In some embodiments, the level converter circuit 902 may be modified to employ another cross-coupled level converter architecture. Figure 10 This is a description of an embodiment of the present invention. Figure 9 A schematic diagram of an alternative design for the level converter circuit 902 in the level conversion enable latch 900 shown. Figure 9 The level converter circuit 902 shown can be replaced with Figure 10 The level shifter circuit 1000 is shown. The main difference between level shifter circuits 902 and 1000 is that level shifter circuit 1000 does not include the PMOS transistors MP7 and MP8 found in level shifter circuit 902.

[0052] In this embodiment, the latch circuit 904 is a low-enable type latch. When E = ebb = 0 and eb = 1, the latch feedback loop 215 is turned off, and the bottom transistors MN7 and MN9 are turned on, enabling the level converter circuit 902 to operate normally to generate and output the data output signal I. LS And in response to the data output signal I LSThe data output signal Q is set by inverters 214 and 216. When E = ebb = 1 and eb = 0, the bottom transistors MN7 and MN8 are turned off to disable the cross-coupling function, and the latch feedback loop 215 is enabled, so that the data output signal Q is latched by the control circuit 512 and inverters 214 and 216.

[0053] like Figure 6 As shown, while the latch enable signal E is set to logic 0, the data output signal Q is set in response to the data input signal I; and while the latch enable signal E is set to logic 1, the data output signal Q is latched, regardless of the data input signal I. Because the data output signal Q is latched, the power-down domain power supply VDD1 can be turned off to save power.

[0054] Figure 11 This is a circuit diagram of a fifth level-shifting enable latch design according to an embodiment of the present invention. The level-shifting enable latch 1100 follows... Figure 1 The architecture shown includes a level shifter circuit 1102 and a latch circuit 1104. Furthermore, the level shift enable latch 1100 may also include the aforementioned signal generation circuits 206 and 208, which act as buffers to provide a cleaner data input signal and a cleaner latch enable signal. However, this does not imply limitation of the invention. Alternatively, the signal generation circuit 206 can be modified to omit the PMOS transistor MP2 and the NMOS transistor MN2, allowing the level shifter circuit 1102 and the latch circuit 1104 to use the data input signal I and its inverted form (i.e., the data input signal ib). Additionally, the signal generation circuit 208 can be omitted, allowing the latch enable signal E to be directly used by the level shifter circuit 1102 and the latch circuit 1104.

[0055] Level converter circuit 1102 is used to receive data input signal ibb, generate and output data output signal I. LS In this embodiment, the data output signal I LS This can be viewed as a level-shifted version of the data input signal ibb. Specifically, the data input signal ibb of the level converter circuit 1102 has a voltage swing of (VDD1-VSS), while the data output signal I of the level converter circuit 1102... LSIt has a voltage swing of (VDD2-VSS). In this embodiment, the level converter circuit 1102 adopts a cross-coupled level converter architecture, thus supporting both VDD1 > VDD2 and VDD1 < VDD2. The main difference between level converter circuits 1102 and 202 is that the data input signal ibb is received by the gate terminals of PMOS transistor MP7 and NMOS transistor MN5, the output M_OUT of the multiplexer is received by the gate terminals of PMOS transistor MP8 and NMOS transistor MN6, and the source terminal of the additional PMOS transistor MP16 is coupled to the power supply voltage VDD2, the drain terminal is coupled to the source terminal of PMOS transistor MP8, and the gate terminal is used to receive the latch enable signal ebb.

[0056] It should be noted that NMOS transistors MN7 and MN8 act as bottom transistors for ESD protection. In some embodiments, the level shifter circuit 1102 can be modified to omit NMOS transistors MN7 and MN8 and directly couple the source terminals of NMOS transistors MN5 and MN6 to ground voltage VSS.

[0057] The latch circuit 1104 includes a multiplexer (MUX) 1106 and the aforementioned inverters 214 and 216. The multiplexer 1106 has an input node N5, which is coupled to the output node N2 of the inverter 214 and is arranged to receive the internal signal preQ of the latch circuit 1104.

[0058] Multiplexer 1106 also has another input node N6, which is arranged to receive the data input signal ib. Multiplexer 1106 has an output node N7, which is arranged to output the multiplexer output signal M_OUT. Multiplexer 1106 is controlled by a selection signal set by the latch enable signal ebb. That is, multiplexer 1106 refers to the latch enable signal ebb to select one of the internal signal preQ and the data input signal ib as the multiplexer output signal M_OUT.

[0059] When the latch enable signal E is set to logic 1, the latch enable signal ebb has a logic value of 1. Therefore, the PMOS transistor MP16 is turned off, and the multiplexer 1106 selects the data input signal ib as the multiplexer output signal M_OUT (i.e., M_OUT = ib), allowing the level shifter circuit 1102 to operate normally. In other words, the multiplexer 1106 acts as a control circuit, disabling the latch feedback loop 215 when the latch enable signal E is set to logic 1. The operation of the level shifter circuit 1102 is similar to that of the level shifter circuit 702, where the data output signal I... LS It can be considered a level-shifted version of the data input signal Ibb, responding to the data output signal I. LSThe data output signal Q is set using inverters 214 and 216.

[0060] When the latch enable signal E is set to logic 0, the latch enable signal ebb also has a logic value of 0. Therefore, the PMOS transistor MP16 is turned on, and the multiplexer 1106 selects the internal signal preQ as the multiplexer output signal M_OUT (i.e., M_OUT = preQ). In other words, the multiplexer 1106 acts as a control circuit, enabling the latch feedback loop 215 when the latch enable signal E is set to logic 0. Furthermore, the level shifter circuit 1102 has a quasi-inverter (composed of a PMOS transistor MP8 and an NMOS transistor MN6) that can be reused while the PMOS transistor MP16 is turned on. Specifically, when PMOS transistor MP16 is turned on, the quasi-inverter (composed of PMOS transistor MP8 and NMOS transistor MN6) becomes a latch feedback inverter, which sets the input signal (i.e., the data output signal I) of inverter 214 by inverting the multiplexer output signal M_OUT (M_OUT = preQ). LS ).

[0061] In this embodiment, the latch circuit 1104 is a high-enable type latch. When E = ebb = 1, the PMOS transistor MP16 is turned off, the multiplexer 1106 selects the data input signal ib as the multiplexer output signal M_OUT, causing the latch feedback loop 215 to open, and the level converter circuit 702 to work normally to generate and output the data output signal I. LS Response data output signal I LS The data output signal Q is set using inverters 214 and 216. When E = ebb = 0, PMOS transistor MP16 is turned on, and multiplexer 1106 selects the internal signal preQ of latch circuit 1104 as the multiplexer output signal M_OUT, enabling latch feedback loop 215. The quasi-inverter of level converter circuit 1102 becomes a latch feedback inverter, and the data output signal Q is latched by multiplexer 1106, quasi-inverter of level converter circuit 1102, and inverters 214 and 216.

[0062] like Figure 4 As shown, while the latch enable signal E is set to logic 1, the data output signal Q is set in response to the data input signal I; and while the latch enable signal E is set to logic 0, the data output signal Q is latched regardless of the data input signal I. Because the data output signal Q is latched, the power supply VDD1 in the power-down domain can be turned off to save power.

[0063] Figure 12 This is a circuit diagram of a sixth level-shifting enable latch design according to an embodiment of the present invention. The level-shifting enable latch 1200 follows... Figure 1 The architecture is shown. The main difference between level shift enable latches 1200 and 1100 is that the gate of the PMOS transistor MP16 in level shifter circuit 1202 is used to receive the latch enable signal eb. The multiplexer 1206 of latch circuit 1204 is configured to select the data input signal ib as the multiplexer output signal M_OUT when the latch enable signal ebb is set to logic value 0, and to select the internal signal preQ of latch circuit 1204 as the multiplexer output signal M_OUT when the latch enable signal ebb is set to logic value 1.

[0064] In this embodiment, the latch circuit 1204 is a low-enable type latch. When E = ebb = 0 and eb = 1, the PMOS transistor MP16 is turned off, the multiplexer 1106 selects the data input signal ib as the multiplexer output signal M_OUT, causing the latch feedback loop 215 to open, and the level converter circuit 702 to work normally to generate and output the data output signal I. LS Response data output signal I LS The data output signal Q is set through inverters 214 and 216. When E = ebb = 1 and eb = 0, PMOS transistor MP16 is turned on, and multiplexer 1106 selects the internal signal preQ of latch circuit 1104 as the multiplexer output signal M_OUT, enabling latch feedback loop 215. The quasi-inverter of level converter circuit 1102 becomes a latch feedback inverter, and the data output signal Q is latched through multiplexer 1106, quasi-inverter of level converter circuit 1102, and inverters 214 and 216.

[0065] like Figure 6 As shown, while the latch enable signal E is set to logic 0, the data output signal Q is set in response to the data input signal I; and while the latch enable signal E is set to logic 1, the data output signal Q is latched, regardless of the data input signal I. Because the data output signal Q is latched, the power supply VDD1 in the power-down domain can be turned off to save power.

[0066] Those skilled in the art will readily recognize that various modifications and alterations can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the scope and limits of the appended claims.

Claims

1. A level-shifting enable latch, comprising: A level converter circuit is used to receive a first data input signal, generate and output a first data output signal, wherein the voltage swing of the first data output signal is different from the voltage swing of the first data input signal. as well as A latch circuit is configured to receive the first data output signal and set the second data output signal in response to the first data output signal when the latch enable signal is set to a first logic value, and to latch the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. A first control circuit is configured to enable the latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and to disable the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value. The level converter circuit mentioned above includes: The first transistor has a control terminal used to receive the first data input signal; The second transistor has a control terminal for receiving a second data input signal, which is the inverse of the first data input signal. A first bottom transistor has a first connection terminal coupled to a first connection terminal of the first transistor, and a second connection terminal coupled to a reference voltage, wherein the first bottom transistor is turned on when the latch enable signal is set to the first logic value, and turned off when the latch enable signal is set to the second logic value; and The second bottom transistor has a first connection terminal coupled to the first connection terminal of the second transistor and a second connection terminal coupled to the reference voltage, wherein the second bottom transistor is turned on when the latch enable signal is set to the first logic value and is turned off when the latch enable signal is set to the second logic value. The first data output signal is output at the second connection terminal of the second transistor; The latch circuit further includes: The third transistor has its control terminal coupled to the second connection terminal of the second transistor; A fourth transistor, the control terminal of which is coupled to the second connection terminal of the first transistor; and A fifth transistor has a first connection terminal coupled to another reference voltage and a second connection terminal coupled to the second connection terminal of the first transistor, wherein the fifth transistor is turned on when the latch enable signal is set to the second logic value, and the fifth transistor is turned off when the latch enable signal is set to the first logic value.

2. The level shift enable latch as described in claim 1, wherein the level shifter circuit adopts a cross-coupled level shifter architecture.

3. The level-shifting enable latch of claim 1, wherein when the latch enable signal is set to the first logic value, a second data input signal derived from the first data output signal is used to set the second data output signal, and the latch circuit further includes: The second control circuit, when the latch enable signal is set to the first logic value, causes the second data input signal to be derived from the first data output signal, and when the latch enable signal is set to the second logic value, prevents the second data input signal from being derived from the first data output signal.

4. The level-shifting enable latch as described in claim 3, wherein, When the latch enable signal is set to the first logic value, the second control circuit also functions as an inverter to invert the first data output signal to generate and output the second data input signal.

5. The level-shifting enable latch as described in claim 3, wherein the latch circuit further comprises: An inverter, wherein the input node of the inverter is coupled to the output node of the first control circuit, and the output node of the inverter is coupled to the input node of the first control circuit; When the latch enable signal is set to the second logic value, the first control circuit also functions as another inverter to invert the output signal of the inverter to set the input signal of the inverter.

6. The level shifting enable latch as claimed in claim 5, wherein when the latch enable signal is set to the first logic value, the input node of the inverter is further configured to receive the second data input signal.

7. The level-shifting enable latch as described in claim 1, wherein the latch circuit further comprises: An inverter whose input node is coupled to the output node of the first control circuit, and whose output node is coupled to the input node of the first control circuit. When the latch enable signal is set to the second logic value, the first control circuit also functions as another inverter to invert the output signal of the inverter to set the input signal of the inverter.

8. The level-shifting enable latch as claimed in claim 7, wherein when the latch enable signal is set to the first logic value, the input node of the inverter is configured to receive the first data output signal.

9. The level shifting enable latch as described in claim 1, wherein the first control circuit comprises: A multiplexer has a first input node for receiving internal signals from the latch circuit, a second input node for receiving a second data input signal, wherein the second data input signal is the inverted version of the first data input signal, and an output node for outputting a multiplexer output signal to the control terminals of the second transistor and the third transistor. When the latch enable signal is set to the second logic value, the multiplexer selects the internal signal as its output signal; and when the latch enable signal is set to the first logic value, the multiplexer selects the second data input signal as its output signal.

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