Level shifting circuit, display apparatus, and driving method
By combining logic processing circuits and delay circuits, a target clock signal is generated, which solves the problem that existing level conversion circuits cannot flexibly adjust the timing of clock signals and improves display quality.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2026-01-04
- Publication Date
- 2026-07-16
AI Technical Summary
Existing level conversion circuits cannot flexibly adjust the timing of clock signals, resulting in poor display effects at both high and low refresh rates, thus affecting display quality.
By introducing a combination of logic processing circuits, delay circuits, and level output circuits, a target clock signal is generated. The delay circuit responds to the working instructions to delay the initial clock signal, thereby achieving flexible adjustment of the clock signal timing.
It enables flexible adjustment of the clock signal timing at different refresh rates, improving the display effect and avoiding display quality problems caused by clock signal duty cycle mismatch.
Smart Images
Figure CN2026070165_16072026_PF_FP_ABST
Abstract
Description
Level conversion circuit, display device and driving method
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202510045465.7, filed on January 10, 2025, entitled "Level Conversion Circuit, Display Device and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of display technology, and in particular to level conversion circuits, display devices, and driving methods. Background Technology
[0004] Displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting Diodes (OLEDs) typically consist of multiple pixel units. Each pixel unit can include multiple subpixels of different colors. By controlling the brightness of each subpixel, the desired colors are mixed to display a color image. Summary of the Invention
[0005] The level conversion circuit provided in this embodiment includes: a logic processing circuit, a delay circuit, and a level output circuit;
[0006] The logic processing circuit is configured to generate at least one initial clock signal based on a first clock reference signal and a second clock reference signal.
[0007] The delay circuit is electrically connected to the logic processing circuit and the level output circuit. The delay circuit is configured to delay the initial clock signal and transmit it to the level output circuit in response to the first working instruction.
[0008] The level output circuit is configured to output a target clock signal based on the clock signal output by the delay circuit.
[0009] In some embodiments, the delay circuit is further configured to delay at least one of the rising and falling edges of the initial clock signal in response to the first operating instruction.
[0010] In some embodiments, the delay circuit is further configured to transmit the initial clock signal to the level output circuit in response to a second operating instruction.
[0011] The display device provided in this embodiment includes: a display panel, a timing controller, and the level conversion circuit described above;
[0012] The timing controller is configured to acquire display data from the display panel, output a first clock reference signal and a second clock reference signal based on the display data, and output a first working instruction or a second working instruction.
[0013] The level conversion circuit is connected to the timing controller and the display panel respectively, and is configured to receive a first clock reference signal and a second clock reference signal, as well as the first working instruction or the second working instruction, and output a target clock signal to the display panel.
[0014] In some embodiments, the display panel operates at multiple refresh rates, and the timing controller is further configured to: determine that the refresh rate of the display panel decreases, and output the first operating instruction.
[0015] In some embodiments, the timing controller is further configured to: determine that the current refresh rate of the display panel is less than the maximum refresh rate, and output the first working instruction.
[0016] In some embodiments, the timing controller is further configured to: determine that the current refresh rate of the display panel is the maximum refresh rate, and output the second operating instruction.
[0017] In some embodiments, the display panel includes: a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines;
[0018] Each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row of sub-pixels respectively.
[0019] A column of sub-pixels is electrically connected to one of the data lines.
[0020] In some embodiments, odd-numbered columns of subpixels in each row are connected to the same gate line, and even-numbered columns of subpixels are connected to the same gate line.
[0021] In some embodiments, the timing controller is further configured to output the first operating instruction.
[0022] In some embodiments, the display panel includes: a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines;
[0023] Each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row of sub-pixels respectively.
[0024] Two adjacent sub-pixels in each row are electrically connected to the same data line.
[0025] In some embodiments, the timing controller is further configured to output the first operating instruction.
[0026] The driving method for a display device provided in this disclosure includes:
[0027] The display data of the display panel is acquired, and based on the display data, a first clock reference signal and a second clock reference signal are output, as well as a first working instruction or a second working instruction is output;
[0028] The system receives a first clock reference signal and a second clock reference signal, as well as the first working instruction or the second working instruction, and outputs a target clock signal to the display panel. Attached Figure Description
[0029] Figure 1 is a schematic diagram of the level conversion circuit in the related technology;
[0030] Figure 2 is a schematic diagram of the level conversion circuit provided in an embodiment of this disclosure;
[0031] Figure 3 is a schematic diagram of some structures of the display device provided in the embodiments of this disclosure;
[0032] Figure 4 is a schematic diagram of some other structures of the display device provided in the embodiments of this disclosure;
[0033] Figure 5 is a signal timing diagram in the related technology;
[0034] Figure 6 is a timing diagram of some signals provided in the embodiments of this disclosure;
[0035] Figure 7 is a schematic diagram of some structures of the display panel provided in the embodiments of this disclosure;
[0036] Figure 8 is a schematic diagram of some other structures of the display panel provided in the embodiments of this disclosure;
[0037] Figure 9 shows some other signal timing diagrams provided in the embodiments of this disclosure;
[0038] Figure 10 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;
[0039] Figure 11 shows some more signal timing diagrams provided in the embodiments of this disclosure;
[0040] Figure 12 is a flowchart of the driving method provided in an embodiment of this disclosure. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0043] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0044] Currently used level shift (LS) circuits generally operate with a few inputs and many outputs, as shown in Figure 1. Taking a 4-input, 12-output level shift circuit 300 as an example, the logic processing circuit 10 in the level shift circuit 300 provides an initial clock signal in response to the signals from the clock reference signal terminals CPV1, CPV2, CPV3, and CPV4. The level output circuit 30 then provides clock signals to the clock signal terminals CLK1 to CLK12 based on the initial clock signal. The rising edge of the clock signal at the odd-numbered clock signal terminals (e.g., CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in Figure 1) is generated based on the rising edge of the first clock reference signal at the input signal terminal CPV1, and the falling edge of the clock signal at the odd-numbered clock signal terminals (e.g., CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in Figure 1) is generated based on the rising edge of the first clock reference signal at the input signal terminal CPV1. The rising edge of the second clock reference signal of the CPV2 terminal is generated; the rising edge of the clock signal of the even-numbered clock signal terminals (e.g., CLK2, CLK4, CLK6, CLK8, CLK10, CLK12 in Figure 1) is generated based on the rising edge of the first clock reference signal of the input signal terminal CPV3, and the falling edge of the clock signal of the even-numbered clock signal terminals (e.g., CLK2, CLK4, CLK6, CLK8, CLK10, CLK12 in Figure 1) is generated based on the rising edge of the second clock reference signal of the input signal terminal CPV4. Therefore, when it is necessary to adjust the clock signal of the clock signal terminal, the timing of the clock signal of the odd-numbered clock signal terminal or the timing of the clock signal of the even-numbered clock signal terminal can only be adjusted at the same time, and the timing of the clock signal of a certain clock signal terminal cannot be adjusted individually. Therefore, it is not conducive to flexibly adjusting the timing of the clock signal according to the needs of the display device.
[0045] As display products gradually move towards higher refresh rates and lower costs, more and more problems related to image quality and clock signal timing are encountered in practical applications. These problems can be effectively solved by adjusting the timing of one or more clock signals. However, it is currently not possible to adjust the timing of the clock signal at the clock signal terminal individually.
[0046] Based on the above problems, the level conversion circuit provided in this embodiment of the present disclosure, as shown in FIG2, includes: a logic processing circuit 10, a delay circuit 20, and a level output circuit 30;
[0047] The logic processing circuit 10 is configured to generate at least one initial clock signal based on the first clock reference signal and the second clock reference signal;
[0048] The delay circuit 20 is electrically connected to the logic processing circuit 10 and the level output circuit 30. The delay circuit 20 is configured to delay the initial clock signal and transmit it to the level output circuit 30 in response to the first working instruction.
[0049] The level output circuit 30 is configured to output a target clock signal based on the clock signal output by the delay circuit 20.
[0050] This embodiment of the invention utilizes the cooperation of a logic processing circuit, a time delay circuit, and a level output circuit. Specifically, the logic processing circuit generates at least one initial clock signal based on a first clock reference signal and a second clock reference signal. The time delay circuit, in response to a first working instruction, performs a time delay on the initial clock signal and transmits it to the level output circuit. Consequently, the level output circuit outputs a target clock signal based on the clock signal output by the time delay circuit. The timing of this target clock signal can be adjusted as needed. In other words, by generating a clock signal through the time delay circuit, the target clock signal can be adjusted independently based on the clock signal, thereby enabling flexible adjustment of the clock signal timing according to the requirements of the display device.
[0051] In some embodiments of this disclosure, as shown in FIG2, the delay circuit 20 is further configured to delay at least one of the rising edge and falling edge of the initial clock signal in response to a first operating instruction.
[0052] For example, if the delay circuit delays the rising edge of the initial clock signal, the rising edge of the initial clock signal is not aligned with the rising edge of the first clock reference signal; or, if the delay circuit delays the falling edge of the initial clock signal, the falling edge of the initial clock signal is not aligned with the rising edge of the second clock reference signal; or, if the delay circuit delays both the rising and falling edges of the initial clock signal, the rising edge of the initial clock signal is not aligned with the rising edge of the first clock reference signal and the falling edge is not aligned with the rising edge of the second clock reference signal.
[0053] In some embodiments of this disclosure, as shown in FIG2, the delay circuit 20 is also configured to transmit an initial clock signal to the level output circuit 30 in response to a second operating instruction.
[0054] For example, when there is no need to delay the initial clock signal, the delay circuit directly transmits the initial clock signal to the level output circuit.
[0055] Based on the same inventive concept, the display device provided in the embodiments of this disclosure, as shown in FIG3 and FIG4, includes: a display panel 100, a timing controller 200, and a level conversion circuit 300;
[0056] The timing controller 200 is configured to acquire display data from the display panel 100, output a first clock reference signal and a second clock reference signal based on the display data, and output a first working instruction or a second working instruction.
[0057] The level conversion circuit 300 is connected to the timing controller 200 and the display panel 100 respectively, and is configured to receive the first clock reference signal and the second clock reference signal, as well as the first working instruction or the second working instruction, and output the target clock signal to the display panel 100.
[0058] For example, the timing controller 200 is electrically connected to the logic processing circuit 10 in the level conversion circuit 300 through the clock reference signal terminals CPV1, CPV2, CPV3, and CPV4; the timing controller 200 provides a first clock reference signal to the clock reference signal terminals CPV1 and CPV3, and a second clock reference signal to the clock reference signal terminals CPV2 and CPV4.
[0059] For example, the display panel 100 includes a plurality of pixel units arranged in an array, each pixel unit including multiple sub-pixels of different colors. For instance, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following explanation uses a pixel unit including red sub-pixels, green sub-pixels, and blue sub-pixels as an example.
[0060] As exemplarily shown in Figure 4, the display device further includes: multiple gate lines GA, multiple data lines DA, a gate driving circuit 110, and a source driving circuit 120; the gate driving circuit 110 is electrically connected to the gate lines GA, and the source driving circuit 120 is electrically connected to the data lines DA. The timing controller 200 can input a target clock signal to the gate driving circuit 110 via the level conversion circuit 300, thereby driving the gate lines GA. The timing controller 200 inputs a control signal to the source driving circuit 120, causing the source driving circuit 120 to input data signals to the data lines DA, thereby charging the sub-pixels and enabling the sub-pixels to input corresponding data signals, thus realizing the image display function. The source driving circuit 120 can be configured as two, with one source driving circuit 120 connected to half of the data lines and the other source driving circuit 120 connected to the other half of the data lines. Of course, three, four, or more source driving circuits 120 can also be configured, which can be designed and determined according to the actual application requirements, and are not limited here.
[0061] For example, the display device supports Hardware Super Resolution (HSR) mode and can support refresh rates of 240Hz and 330Hz. Experimental tests revealed that in HSR mode, the duty cycle of the clock signal needs to be set to 5 / 12. However, in actual testing, when the refresh rate is 330Hz, the duty cycle of the clock signals at odd-numbered clock signal terminals (e.g., CLK1, CLK3, CLK5, CLK7, CLK9, CLK11 in Figure 1) is 41.77%, and the duty cycle of the clock signals at even-numbered clock signal terminals (e.g., CLK2, CLK4, CLK6, CLK8, CLK10, CLK12 in Figure 1) is 41.55%. It can be seen that the duty cycle of the clock signals at odd-numbered and even-numbered clock signal terminals basically meets the 5 / 12 requirement; however… When the refresh rate is reduced, i.e., when the refresh rate is 240Hz, the duty cycle of the clock signals of odd-numbered clock signal terminals (such as CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in Figure 1) is 43.98%, and the duty cycle of the clock signals of even-numbered clock signal terminals (such as CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in Figure 1) is 39.29%. It can be seen that the duty cycle of the clock signals of odd-numbered and even-numbered clock signal terminals does not conform to the preset 5 / 12. Multiple experimental tests revealed that in hardware super-resolution mode, when the refresh rate is reduced, the duty cycle of the clock signals at odd-numbered clock signal terminals (such as CLK1, CLK3, CLK5, CLK7, CLK9, and CLK11 in Figure 1) increases, while the clock signals at even-numbered clock signal terminals (such as CLK2, CLK4, CLK6, CLK8, CLK10, and CLK12 in Figure 1) decrease. This results in poor display effects and affects display quality.
[0062] It should be noted that the above problem is determined by the timing mechanism of the timing controller generating the clock reference signal, and therefore cannot be solved by adjusting the timing of the timing controller generating the clock reference signal. The following explanation will be based on the signal timing diagram shown in Figure 5. In hardware super-resolution mode with a refresh rate of 330Hz, the rising edge of the control signal DE generated by the timing controller always coincides with the rising edge of the data transmission signal VBO DATA. The period of the data transmission signal VBO DATA is 1H, and the falling edge of the control signal DE is fixed at a fixed position according to the internal frequency of the timing controller. Let A be the time interval between the rising edge of clock reference signal CPV1 (cpv1) and the rising edge of control signal DE; B be the time interval between the rising edge of clock reference signal CPV2 (cpv2) and the rising edge of clock reference signal CPV3 (cpv3) and the rising edge of clock reference signal CPV4 (cpv4) and the rising edge of clock reference signal DE; where the high-level width of signals cpv1, cpv2, cpv3, and cpv4 is W, currently set to W = AB = 0.5H (W can also be set to other values). Then, the period of clock signal clk1 is 6H + AA = 6H, the high-level width of clock signal clk1 is 3H + BA, and the duty cycle of clock signal clk1 is... The period of clock signal clk2 is 6H + BB = 6H, the high-level width of clock signal clk2 is 2H + AB, and the duty cycle of clock signal clk2 is... When the refresh rate decreases, the time of 1H increases, while AB is a fixed value. Therefore, the duty cycle of clock signal clk1 increases, and the duty cycle of clock signal clk2 decreases. That is, when the refresh rate decreases, the duty cycle of the clock signal at the odd-numbered clock signal terminal increases, and the clock signal at the even-numbered clock signal terminal decreases. This will lead to poor display effect and affect display quality. This problem cannot be solved by adjusting the TCON timing at present.
[0063] In some embodiments of this disclosure, as shown in FIG3, the display panel 100 operates at multiple refresh frequencies, and the timing controller 200 is further configured to: determine that the refresh frequency of the display panel 100 decreases, and output a first operating instruction.
[0064] In this embodiment, the timing controller determines that the refresh rate of the display panel is reduced and outputs a first working command. Then, the delay circuit in the level conversion circuit responds to the first working command, performs delay processing on the initial clock signal and transmits it to the level output circuit. Thus, the level output circuit outputs a target clock signal according to the clock signal output by the delay circuit. The timing of the target clock signal can be adjusted as needed. That is, the clock signal is generated through the delay processing of the delay circuit, and the target clock signal can be adjusted separately according to the clock signal. Thus, the timing of a certain clock signal can be set and adjusted separately according to the needs of the display device.
[0065] In some embodiments of this disclosure, as shown in FIG3, the timing controller 200 is further configured to: determine that the current refresh frequency of the display panel 100 is less than the maximum refresh frequency, and output a first working instruction.
[0066] In some embodiments of this disclosure, as shown in FIG3, the timing controller 200 is further configured to: determine that the current refresh frequency of the display panel 100 is the maximum refresh frequency, and output a second working instruction.
[0067] The following will take the structure shown in Figure 3 as an example and explain it in detail with reference to the signal timing diagram shown in Figure 6.
[0068] As shown in Figure 6, cpv1 represents the first clock reference signal of the clock reference signal terminal CPV1, cpv2 represents the second clock reference signal of the clock reference signal terminal CPV2, cpv3 represents the first clock reference signal of the clock reference signal terminal CPV3, cpv4 represents the second clock reference signal of the clock reference signal terminal CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, clk1 represents the target clock signal, and clk2 represents the target clock signal.
[0069] The timing controller 200 acquires the display data from the display panel 100, outputs first clock reference signals cpv1 and cpv3 and second clock reference signals cpv2 and cpv4 based on the display data, and determines that the current refresh frequency of the display panel 100 is less than the maximum refresh frequency, and outputs a first working instruction; the logic processing circuit 10 generates an initial clock signal vclk1 based on the first clock reference signal cpv1 and the second clock reference signal cpv2, and generates an initial clock signal vclk2 based on the first clock reference signal cpv3 and the second clock reference signal cpv4; the delay circuit 20 delays the rising edge of the initial clock signal vclk1 according to the first working instruction, with a delay duration of [duration missing]. At time t1, the falling edge of the initial clock signal vclk1 is delayed for a duration of t2, and the falling edge of the initial clock signal vclk2 is delayed for a duration of t3. Then, the level output circuit 30 outputs the target clock signals clk1 and clk2 based on the clock signals output after the delay processing by the time delay circuit 10. The duty cycle of the initial clock signal vclk1 is greater than 5 / 12, meaning its high-level time is too long. The duty cycle of the initial clock signal vclk2 is less than 5 / 12, meaning its high-level time is too short. Therefore, the time difference between the rising edges of the initial clock signals vclk1 and vclk2 is greater than 1H, which does not meet the preset value. After the delay processing, the phase difference between the rising edges of the target clock signals cclk1 and clk2 is 1H, which meets the preset value. Furthermore, the duty cycles of the target clock signals cclk1 and clk2 are the same. This avoids the situation where, in hardware super-resolution mode, when the refresh rate is reduced, the duty cycle of the target clock signal clk1 at odd-numbered clock signal terminals (such as CLK1 in Figure 3) increases, while the duty cycle of the target clock signal clk2 at even-numbered clock signal terminals (such as CLK2 in Figure 3) decreases, thereby improving the display effect and enhancing the display quality.
[0070] For example, the delay durations t1, t2, and t3 are adjusted to the optimal state, and then the parameter information about the delay durations t1, t2, and t3 is saved in the timing controller. When the timing controller detects that the first working instruction needs to be output, it provides the parameter information to the delay circuit in the level conversion circuit.
[0071] In some embodiments of this disclosure, each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row; a column of sub-pixels is electrically connected to a data line.
[0072] For example, as shown in Figure 7, the first row of sub-pixels spx corresponds to the gate lines GA1 and GA2, and two adjacent sub-pixels spx in the first row are electrically connected to the gate lines GA1 and GA2 respectively; the second row of sub-pixels spx corresponds to the gate lines GA3 and GA4, and two adjacent sub-pixels spx in the second row are electrically connected to the gate lines GA3 and GA4 respectively; the third row of sub-pixels spx corresponds to the gate lines GA5 and GA6, and two adjacent sub-pixels spx in the third row are electrically connected to the gate lines GA5 and GA6 respectively; the fourth row of sub-pixels spx corresponds to the gate lines GA7 and GA8, and two adjacent sub-pixels spx in the fourth row are electrically connected to the gate lines GA7 and GA8 respectively. The first column of sub-pixels (spx) is electrically connected to the corresponding data line DA1. The second column of sub-pixels (spx) is electrically connected to the corresponding data line DA2. The third column of sub-pixels (spx) is electrically connected to the corresponding data line DA2. The fourth column of sub-pixels (spx) is electrically connected to the corresponding data line DA3. The fifth column of sub-pixels (spx) is electrically connected to the corresponding data line DA3. The sixth column of sub-pixels (spx) is electrically connected to the corresponding data line DA4. The seventh column of sub-pixels (spx) is electrically connected to the corresponding data line DA4. The eighth column of sub-pixels (spx) is electrically connected to the corresponding data line DA5. The ninth column of sub-pixels (spx) is electrically connected to the corresponding data line DA5. The tenth column of sub-pixels (spx) is electrically connected to the corresponding data line DA6. The eleventh column of sub-pixels (spx) is electrically connected to the corresponding data line DA6. The twelfth column of sub-pixels (spx) is electrically connected to the corresponding data line DA7.
[0073] In some embodiments of this disclosure, odd-numbered columns of subpixels in each row are connected to the same gate line, and even-numbered columns of subpixels are connected to the same gate line.
[0074] For example, as shown in Figure 8, the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels spx in the first row are electrically connected to gate line GA1, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels spx in the first row are electrically connected to gate line GA2; the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels spx in the second row are electrically connected to gate line GA3, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels spx in the second row are electrically connected to gate line GA2. A4 is electrically connected; the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels in the 3rd row are electrically connected to the grid line GA5, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels in the 3rd row are electrically connected to the grid line GA6; the 1st, 3rd, 5th, 7th, 9th, and 11th sub-pixels in the 4th row are electrically connected to the grid line GA7, and the 2nd, 4th, 6th, 8th, 10th, and 12th sub-pixels in the 4th row are electrically connected to the grid line GA8.
[0075] For example, as shown in Figures 7 and 8, each sub-pixel spx may include a transistor 01 and a pixel electrode 02. The gate of transistor 01 is electrically connected to the corresponding gate line, the source of transistor 01 is electrically connected to the corresponding data line, and the drain of transistor 01 is electrically connected to the pixel electrode 02.
[0076] As exemplified by the display panel structure shown in Figures 7 and 8, after multiple frame flips, the change in polarity exacerbates the insufficient charging of pixel electrodes in the upstream and downstream sub-pixels due to the polarity change. For example, the pixel electrode of the sub-pixel corresponding to the first row of gate lines is poorly charged compared to the pixel electrodes of the sub-pixels corresponding to the next three rows of gate lines, resulting in monochrome, color mixing, and grayscale stripe problems in the display panel.
[0077] In some embodiments of this disclosure, the timing controller 200 is further configured to output the first operating instruction.
[0078] In this embodiment, by having the timing controller output a first working command, the delay circuit in the level conversion circuit responds to the first working command by delaying the initial clock signal and transmitting it to the level output circuit. The level output circuit then outputs a target clock signal based on the clock signal output by the delay circuit. The timing of the target clock signal can be adjusted as needed. Thus, by adjusting the target clock signal, the charging time of each row of sub-pixels can be adjusted, thereby avoiding the problem of insufficient charging of pixel electrodes in the upper and lower rows of sub-pixels due to polarity changes, and thus improving the monochrome, color mixing, and grayscale horizontal stripe problems of the display panel.
[0079] The following will use the structures shown in Figures 3 and 7 as examples, combined with the signal timing diagram shown in Figure 9, for a detailed explanation.
[0080] As shown in Figure 9, cpv1 represents the first clock reference signal of the clock reference signal terminal CPV1, cpv2 represents the second clock reference signal of the clock reference signal terminal CPV2, cpv3 represents the first clock reference signal of the clock reference signal terminal CPV3, cpv4 represents the second clock reference signal of the clock reference signal terminal CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, vclk3 represents the initial clock signal, vclk4 represents the initial clock signal, clk1 represents the target clock signal, clk2 represents the target clock signal, clk3 represents the target clock signal, clk4 represents the target clock signal, and data represents the data signal.
[0081] The timing controller 200 acquires the display data from the display panel 100 and outputs first clock reference signals cpv1 and cpv3, second clock reference signals cpv2 and cpv4, and a first working instruction based on the display data. The logic processing circuit 10 generates initial clock signals vclk1 and vclk3 based on the first clock reference signal cpv1 and the second clock reference signal cpv2, and generates initial clock signals vclk2 and vclk4 based on the first clock reference signal cpv3 and the second clock reference signal cpv4. The delay circuit 20, according to the first working instruction, delays the rising edge of the initial clock signal vclk1 for a delay duration of t1, delays the rising edge of the initial clock signal vclk2 for a delay duration of t2, delays the rising edge of the initial clock signal vclk3 for a delay duration of t3, and does not delay the rising edge of the initial clock signal vclk4. When the duration is 0, where t1 > t2 > t3 > 0; then the level output circuit 30 outputs target clock signals clk1, clk2, clk3, and clk4 based on the clock signal output after delay processing by the delay circuit 10; target clock signal clk1 is loaded on gate line GA1, target clock signal clk2 is loaded on gate line GA2, target clock signal clk3 is loaded on gate line GA3, and target clock signal clk4 is loaded on gate line GA4. Then the charging time of the sub-pixel corresponding to the first row of gate lines is T1, the charging time of the sub-pixel corresponding to the second row of gate lines is T2, the charging time of the sub-pixel corresponding to the third row of gate lines is T3, and the charging time of the sub-pixel corresponding to the fourth row of gate lines is T4, where T1 > T2 > T3 > T4; then, the pixel electrode charging time of the sub-pixel corresponding to the first row of gate lines is longer, and the pixel electrode charging time of the sub-pixel corresponding to the last three rows of gate lines is shorter, which can avoid the problems of monochrome, mixed colors, and grayscale horizontal stripes on the display panel.
[0082] In some embodiments of this disclosure, each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row; two adjacent sub-pixels in each row are electrically connected to the same data line.
[0083] For example, as shown in Figure 10, the first row of sub-pixels spx corresponds to the gate lines GA1 and GA2, and two adjacent sub-pixels spx in the first row are electrically connected to the gate lines GA1 and GA2 respectively; the second row of sub-pixels spx corresponds to the gate lines GA3 and GA4, and two adjacent sub-pixels spx in the second row are electrically connected to the gate lines GA3 and GA4 respectively; the third row of sub-pixels spx corresponds to the gate lines GA5 and GA6, and two adjacent sub-pixels spx in the third row are electrically connected to the gate lines GA5 and GA6 respectively; the fourth row of sub-pixels spx corresponds to the gate lines GA7 and GA8, and two adjacent sub-pixels spx in the fourth row are electrically connected to the gate lines GA7 and GA8 respectively. The first column of sub-pixels (spx) is electrically connected to the corresponding data line DA1. The second column of sub-pixels (spx) is electrically connected to the corresponding data line DA2. The third column of sub-pixels (spx) is electrically connected to the corresponding data line DA2. The fourth column of sub-pixels (spx) is electrically connected to the corresponding data line DA3. The fifth column of sub-pixels (spx) is electrically connected to the corresponding data line DA3. The sixth column of sub-pixels (spx) is electrically connected to the corresponding data line DA4. The seventh column of sub-pixels (spx) is electrically connected to the corresponding data line DA4. The eighth column of sub-pixels (spx) is electrically connected to the corresponding data line DA5. The ninth column of sub-pixels (spx) is electrically connected to the corresponding data line DA5. The tenth column of sub-pixels (spx) is electrically connected to the corresponding data line DA6. The eleventh column of sub-pixels (spx) is electrically connected to the corresponding data line DA6. The twelfth column of sub-pixels (spx) is electrically connected to the corresponding data line DA7.
[0084] For example, as shown in Figure 10, for the first and second rows of sub-pixels, the first and second sub-pixels in these two rows are electrically connected to data line DA1; the third and fourth sub-pixels in these two rows are electrically connected to data line DA2; the fifth and sixth sub-pixels in these two rows are electrically connected to data line DA3; the seventh and eighth sub-pixels in these two rows are electrically connected to data line DA4; the ninth and tenth sub-pixels in these two rows are electrically connected to data line DA5; and the eleventh and twelfth sub-pixels in these two rows are electrically connected to data line D... A6 is electrically connected; for the sub-pixels in the 3rd and 4th rows, the 1st and 2nd sub-pixels in these two rows are electrically connected to data line DA2, the 3rd and 4th sub-pixels in these two rows are electrically connected to data line DA3, the 5th and 6th sub-pixels in these two rows are electrically connected to data line DA4, the 7th and 8th sub-pixels in these two rows are electrically connected to data line DA5, the 9th and 10th sub-pixels in these two rows are electrically connected to data line DA6, and the 11th and 12th sub-pixels in these two rows are electrically connected to data line DA7.
[0085] For example, as shown in Figure 10, in the hardware super-resolution mode, clock signals are sequentially applied to grid lines GA1, GA3, GA2, and GA4 in the display panel. This configuration avoids color mixing and ensures that adjacent rows of sub-pixels emit the same color. To achieve the sequential application of signals to grid lines GA1, GA3, GA2, and GA4 in the display panel, in this embodiment, the timing controller is further configured to output a first working instruction. That is, by causing the timing controller to output the first working instruction, the delay circuit in the level conversion circuit responds to the first working instruction, delays the initial clock signal, and transmits it to the level output circuit. The level output circuit then outputs a target clock signal based on the clock signal output by the delay circuit. The timing of this target clock signal can be adjusted as needed. This ensures that signals are sequentially applied to grid lines GA1, GA3, GA2, and GA4 in the display panel, avoiding color mixing and ensuring that adjacent rows of sub-pixels emit the same color, thereby improving the display effect.
[0086] The following will use the structures shown in Figures 3 and 10 as examples, combined with the signal timing diagram shown in Figure 11, to provide a detailed explanation.
[0087] As shown in Figure 11, cpv1 represents the first clock reference signal of the clock reference signal terminal CPV1, cpv2 represents the second clock reference signal of the clock reference signal terminal CPV2, cpv3 represents the first clock reference signal of the clock reference signal terminal CPV3, cpv4 represents the second clock reference signal of the clock reference signal terminal CPV4, vclk1 represents the initial clock signal, vclk2 represents the initial clock signal, vclk3 represents the initial clock signal, vclk4 represents the initial clock signal, clk1 represents the target clock signal, clk2 represents the target clock signal, clk3 represents the target clock signal, clk4 represents the target clock signal, and data represents the data signal.
[0088] The timing controller 200 acquires the display data from the display panel 100, and outputs first clock reference signals cpv1 and cpv3, second clock reference signals cpv2 and cpv4, and a first working instruction based on the display data. The logic processing circuit 10 generates initial clock signals vclk1 and vclk3 based on the first clock reference signal cpv1 and the second clock reference signal cpv2, and generates initial clock signals vclk2 and vclk4 based on the first clock reference signal cpv3 and the second clock reference signal cpv4. The delay circuit 20 delays the rising edge of the initial clock signal vclk1 for 1 hour and the rising edge of the initial clock signal vclk2 for 2 hours according to the first working instruction. The rising edge of k3 is not delayed, i.e., the delay duration is 0. The rising edge of the initial clock signal vclk4 is delayed for 1H. Then, the level output circuit 30 outputs the target clock signals clk1, clk3, clk2, and clk4 sequentially according to the clock signal output after the delay circuit 10. The target clock signal clk1 is loaded on the gate line GA1, the target clock signal clk2 is loaded on the gate line GA2, the target clock signal clk3 is loaded on the gate line GA3, and the target clock signal clk4 is loaded on the gate line GA4. By using the delay circuit, the target clock signals are sequentially loaded onto the gate lines GA1, GA3, GA2, and GA4 in the display panel, avoiding color mixing problems and ensuring that the light emission color of adjacent rows of sub-pixels is the same, thereby improving the display effect.
[0089] Based on the same inventive concept, this disclosure also provides a driving method for a display device, as shown in FIG12, including the following steps:
[0090] S100: Obtain the display data from the display panel, and based on the display data, output a first clock reference signal and a second clock reference signal, and output a first working instruction or a second working instruction;
[0091] S200 receives a first clock reference signal and a second clock reference signal, as well as a first working command or a second working command, and outputs a target clock signal to the display panel.
[0092] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0093] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0094] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.
[0095] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.
[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.
[0097] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0098] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. A level conversion circuit, wherein, include: Logic processing circuits, delay circuits, and level output circuits; The logic processing circuit is configured to generate at least one initial clock signal based on a first clock reference signal and a second clock reference signal. The delay circuit is electrically connected to the logic processing circuit and the level output circuit. The delay circuit is configured to delay the initial clock signal and transmit it to the level output circuit in response to the first working instruction. The level output circuit is configured to output a target clock signal based on the clock signal output by the delay circuit.
2. The level conversion circuit as described in claim 1, wherein, The delay circuit is further configured to delay at least one of the rising and falling edges of the initial clock signal in response to the first operating instruction.
3. The level conversion circuit as described in claim 1 or 2, wherein, The delay circuit is also configured to transmit the initial clock signal to the level output circuit in response to a second operating instruction.
4. A display device, wherein, include: The display panel, the timing controller, and the level conversion circuit as described in any one of claims 1-3; The timing controller is configured to acquire display data from the display panel, output a first clock reference signal and a second clock reference signal based on the display data, and output a first working instruction or a second working instruction. The level conversion circuit is connected to the timing controller and the display panel respectively, and is configured to receive a first clock reference signal and a second clock reference signal, as well as the first working instruction or the second working instruction, and output a target clock signal to the display panel.
5. The display device as claimed in claim 4, wherein, The display panel operates at multiple refresh rates, and the timing controller is further configured to: determine that the refresh rate of the display panel decreases, and output the first operating instruction.
6. The display device as claimed in claim 5, wherein, The timing controller is further configured to: determine that the current refresh rate of the display panel is less than the maximum refresh rate, and output the first working instruction.
7. The display device as claimed in claim 5 or 6, wherein, The timing controller is further configured to: determine that the current refresh rate of the display panel is the maximum refresh rate, and output the second working instruction.
8. The display device as claimed in claim 4, wherein, The display panel includes: multiple sub-pixels, multiple data lines, and multiple gate lines; Each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row of sub-pixels respectively. A column of sub-pixels is electrically connected to one of the data lines.
9. The display device as claimed in claim 8, wherein, In each row of sub-pixels, odd-numbered columns of sub-pixels are connected to the same gate line, and even-numbered columns of sub-pixels are connected to the same gate line.
10. The display device as claimed in claim 8, wherein, The timing controller is further configured to output the first operating instruction.
11. The display device as claimed in claim 4, wherein, The display panel includes: multiple sub-pixels, multiple data lines, and multiple gate lines; Each row of sub-pixels is provided with two gate lines, and two adjacent sub-pixels in each row are electrically connected to the two gate lines provided in that row of sub-pixels respectively. Two adjacent sub-pixels in each row are electrically connected to the same data line.
12. The display device as claimed in claim 11, wherein, The timing controller is further configured to output the first operating instruction.
13. A driving method for a display device, wherein, include: The display data of the display panel is acquired, and based on the display data, a first clock reference signal and a second clock reference signal are output, as well as a first working instruction or a second working instruction is output; The system receives a first clock reference signal and a second clock reference signal, as well as the first working instruction or the second working instruction, and outputs a target clock signal to the display panel.