A constant duty cycle high speed multi-voltage domain level shifting circuit
By designing a level shifting circuit that includes pull-up transistors, pull-down transistors, and cross-coupled timing correction circuits, the problem of large duty cycle variations in level shifting circuits under different power supply voltages was solved, achieving high-speed and constant output signals.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOTORCOMM (SHANGHAI) ELECTRONIC TECH CO LTD
- Filing Date
- 2023-01-09
- Publication Date
- 2026-06-05
AI Technical Summary
Existing level conversion circuits have large variations in output duty cycle under different power supply voltages, making it difficult to improve speed.
A level conversion module including pull-up and pull-down transistors is used, combined with the first and second pull-down modules, and a delay inverter and cross-coupled timing correction circuit are used to achieve a constant duty cycle of the output signal.
It maintains a constant duty cycle of the output signal under different power supply voltages, enabling high-speed operation.
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Figure CN116054809B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of level conversion technology, and in particular to a high-speed multi-voltage domain level conversion circuit with a constant duty cycle. Background Technology
[0002] In a circuit system, there are usually two or more power domains. Each power domain supplies power to its corresponding circuit. However, a circuit in one power domain inevitably needs to use signals from other power domains. For example, digital power and analog power supply power digital and analog circuits respectively, while the control signals of analog circuits come from the digital power domain. This requires a level shift circuit to realize the level conversion across power domains.
[0003] Existing level shift circuits have the following drawbacks: the output duty cycle varies greatly under different power supply voltages, making it difficult to improve the speed. Summary of the Invention
[0004] To address the above technical problems, this invention provides a high-speed multi-voltage domain level conversion circuit with a constant duty cycle.
[0005] The technical problem solved by this invention can be achieved by the following technical solutions:
[0006] A high-speed multi-voltage domain level conversion circuit with a constant duty cycle includes:
[0007] A level conversion module, comprising a pull-up transistor circuit and a pull-down transistor circuit; wherein the pull-up transistor circuit is connected between a high power supply voltage domain and an output node, and the pull-down transistor circuit is coupled to the output node, the output node being used to output a pair of high and low level output signals;
[0008] The first pull-down module is connected between the pull-down transistor circuit and the ground terminal to control the duty cycle of the output signal when the high power supply voltage is lower than a first preset value.
[0009] The second pull-down module is connected between the output node and the ground terminal to control the duty cycle of the output signal when the high power supply voltage domain is higher than a second preset value.
[0010] Wherein, the second preset value is greater than the first preset value.
[0011] In a preferred embodiment, the first drop-down module includes:
[0012] The first transistor is controllably connected between one of the pull-down transistors in the pull-down circuit and the ground terminal under the action of an odd-numbered delayed inverted signal of an input signal;
[0013] The second transistor is controllably connected to another pull-down transistor of the pull-down circuit under the action of an even-number delay inverted signal of an input signal;
[0014] The third transistor is controllably connected between the second transistor and the ground terminal under the action of a first set signal.
[0015] In a preferred embodiment, the second drop-down module includes:
[0016] The fourth transistor is controllably connected to one of the pull-up transistors in the pull-up circuit under the action of an odd-numbered delayed inverted signal of an input signal;
[0017] The fifth transistor is controllably connected between the fourth transistor and the ground terminal under the action of a first set signal;
[0018] The sixth transistor is controllably connected to another pull-up transistor in the pull-up circuit under the action of an even-number delay inverted signal of an input signal;
[0019] The seventh transistor is controllably connected between the sixth transistor and the ground terminal under the action of the first set signal.
[0020] In a preferred embodiment, it further includes: a delay-inverting circuit connected between the high power supply voltage domain and the ground terminal, the delay-inverting circuit comprising:
[0021] A first delay inverter, wherein the input of the first delay inverter is the input signal, and the output is an odd-order delayed and inverted signal of the input signal;
[0022] The second delay inverter has its input connected to the output of the first delay inverter, and its output is an even-numbered delayed and inverted signal of the input signal.
[0023] In a preferred embodiment, the threshold voltage of the first transistor is less than the threshold voltage of the fourth transistor;
[0024] The threshold voltage of the second transistor is less than the threshold voltage of the sixth transistor.
[0025] In a preferred embodiment, the pull-down transistor circuit includes:
[0026] The first pull-down transistor is controllably connected between a first output node and the first transistor under the action of a bias signal;
[0027] The second pull-down transistor is controllably connected between a second output node and the second transistor under the action of the bias signal;
[0028] The output nodes include the first output node and the second output node.
[0029] In a preferred embodiment, the pull-up transistor circuit includes:
[0030] The first pull-up transistor is controllably connected between the high power supply voltage domain and the first output node under the action of a signal from the second output node;
[0031] The second pull-up transistor is controllably connected between the high power supply voltage domain and the second output node under the action of the signal from the first output node;
[0032] The output nodes include the first output node and the second output node.
[0033] In a preferred embodiment, the first pull-up transistor is further connected in parallel with a switching transistor, which can be controlled to be turned on or off under the action of a second set signal.
[0034] In a preferred embodiment, it further includes:
[0035] A cross-coupled timing correction circuit, connected to the output node, is used to correct the duty cycle of the output signal when the duty cycle of the output signal exceeds a preset deviation range, so that the duty cycle remains within the preset deviation range.
[0036] In a preferred embodiment, the cross-coupled timing correction circuit includes a plurality of cross-coupled delay inverters.
[0037] The advantages or beneficial effects of the technical solution of this invention are as follows:
[0038] This invention uses two pull-down modules to maintain a constant output duty cycle in the high power supply voltage domain under different voltages, enabling it to operate at a high speed. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the overall circuit of a high-speed multi-voltage domain level conversion circuit with a constant duty cycle in a preferred embodiment of the present invention.
[0040] Figure 2 This is a schematic diagram of the structure of the two-way pull-down module in a preferred embodiment of the present invention;
[0041] Figure 3 This is a schematic diagram of a cross-coupling timing correction circuit in the prior art. Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0043] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0044] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0045] See Figure 1-3 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a high-speed multi-voltage domain level conversion circuit with constant duty cycle is provided, comprising:
[0046] The level conversion module includes a pull-up transistor circuit and a pull-down transistor circuit. The pull-up transistor circuit is connected between a high power supply voltage domain and an output node, and the pull-down transistor circuit is coupled to the output node. The output node is used to output a pair of high and low level output signals.
[0047] The first pull-down module is connected between the pull-down transistor circuit and the ground terminal to control the duty cycle of the output signal when the high power supply voltage is lower than a first preset value.
[0048] The second pull-down module is connected between the output node and the ground terminal to control the duty cycle of the output signal when the high power supply voltage is higher than a second preset value.
[0049] The second preset value is greater than the first preset value.
[0050] In a preferred embodiment, the first drop-down module includes:
[0051] The first transistor m1 is controllably connected between one of the pull-down transistors in the pull-down circuit and the ground terminal under the action of an odd-numbered delayed inverted signal inb of an input signal;
[0052] The second transistor m2 is controllably connected to another pull-down transistor in the pull-down circuit under the action of an even-number delay inverted signal inc of an input signal;
[0053] The third transistor m3 is controllably connected between the second transistor and the ground terminal under the action of a first set signal por.
[0054] In a preferred embodiment, the second drop-down module includes:
[0055] The fourth transistor m4 is controllably connected to one of the pull-up transistors in the pull-up circuit under the action of an odd-numbered delayed inverted signal inb of an input signal;
[0056] The fifth transistor m5 is controllably connected between the fourth transistor and the ground terminal under the action of a first set signal por;
[0057] The sixth transistor m6 is controllably connected to another pull-up transistor in the pull-up circuit under the action of an even-numbered delay inverted signal inc of an input signal;
[0058] The seventh transistor m7 is controllably connected between the sixth transistor and the ground terminal under the action of the first set signal por.
[0059] In a preferred embodiment, it further includes: a delay-inverting circuit connected between the high power supply voltage domain and the ground terminal, the delay-inverting circuit comprising:
[0060] The first delay inverter inv1 has the input signal in as its input and the output signal inb as the odd-numbered delayed inverted input signal.
[0061] The inputs of the second delay inverter inv2 and the second delay inverter inv3 are connected to the output of the first delay inverter inv1, and the output is the even-numbered delayed and inverted signal inc of the input signal.
[0062] In a preferred embodiment, the threshold voltage of the first transistor m1 is less than the threshold voltage of the fourth transistor m4.
[0063] The threshold voltage of the second transistor m2 is less than the threshold voltage of the sixth transistor m6.
[0064] In a preferred embodiment, the pull-down transistor circuit includes:
[0065] The first pull-down transistor m8 is controllably connected between a first output node and the first transistor m1 under the action of a bias signal;
[0066] The second pull-down transistor m9 is controllably connected between a second output node and the second transistor m2 under the action of a bias signal. The first pull-down transistor m8 and the second pull-down transistor m9 of this invention are NMOS constant biased, so that the high-speed duty cycle can be kept constant at 50%.
[0067] The output nodes include the first output node and the second output node.
[0068] In a preferred embodiment, the pull-up transistor circuit includes:
[0069] The first pull-up transistor m11 is controllably connected between the high power supply voltage domain VDDH and the first output node under the action of a signal from a second output node;
[0070] The second pull-up transistor m12 is controllably connected between the high power supply voltage domain VDDH and the second output node under the action of the signal from the first output node;
[0071] The output nodes include the first output node b and the second output node a.
[0072] In a preferred embodiment, the first pull-up transistor m11 is further connected in parallel with a switching transistor m10, which can be controlled to be turned on or off under the action of a second set signal por_b. Specifically, the output state of the level conversion is set by the first set signal por and the second set signal por_b.
[0073] In a preferred embodiment, it further includes:
[0074] A cross-coupled timing correction circuit is connected to the output node and is used to correct the duty cycle of the output signal when the duty cycle exceeds a preset deviation range, so that the duty cycle is kept within the preset deviation range. The preset deviation range is preferably 50%. When the duty cycle deviation between the first output node and the second output node is not 50%, differential correction is performed by this circuit to keep the duty cycle at 50%.
[0075] In a preferred embodiment, such as Figure 2 As shown, the cross-coupled timing correction circuit includes several cross-coupled delay inverters inv3-inv12, wherein delay inverters inv3, inv7, and inv11 are connected in series to the second output node, delay inverters inv4, inv8, and inv12 are connected in series to the first output node, and delay inverters inv5 and inv6, and delay inverters inv9 and inv10 are connected in parallel in opposite directions between the two delay inverters on the high and low level output signal lines.
[0076] This invention embodiment achieves a constant high-speed duty cycle by using a parallel two-channel pull-down circuit to adaptively switch under different voltage conditions, thus solving the problem of constant high-speed output duty cycle of RGMII under different IO power supply voltage conditions, without the need to design different level shift operations.
[0077] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.
Claims
1. A high-speed multi-voltage domain level conversion circuit with a constant duty cycle, characterized in that, include: A level conversion module, comprising a pull-up transistor circuit and a pull-down transistor circuit; wherein the pull-up transistor circuit is connected between a high power supply voltage domain and an output node, and the pull-down transistor circuit is coupled to the output node, the output node being used to output a pair of high and low level output signals; The first pull-down module is connected between the pull-down transistor circuit and the ground terminal to control the duty cycle of the output signal when the high power supply voltage domain is lower than a first preset value. The second pull-down module is connected between the output node and the ground terminal to control the duty cycle of the output signal when the high power supply voltage domain is higher than a second preset value. Wherein, the second preset value is greater than the first preset value; The first dropdown module includes: The first transistor is controllably connected between one of the pull-down transistors in the pull-down circuit and the ground terminal under the action of an odd-numbered delayed inverted signal of an input signal; The second transistor is controllably connected to another pull-down transistor of the pull-down circuit under the action of an even-number delay inverted signal of an input signal; The third transistor is controllably connected between the second transistor and the ground terminal under the action of a first set signal; The second dropdown module includes: The fourth transistor is controllably connected to one of the pull-up transistors in the pull-up circuit under the action of an odd-numbered delayed inverted signal of an input signal; The fifth transistor is controllably connected between the fourth transistor and the ground terminal under the action of a first set signal; The sixth transistor is controllably connected to another pull-up transistor in the pull-up circuit under the action of an even-number delay inverted signal of an input signal; The seventh transistor is controllably connected between the sixth transistor and the ground terminal under the action of the first set signal.
2. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 1, characterized in that, Also includes: A time-delay inverting circuit is connected between the high power supply voltage domain and the ground terminal, the time-delay inverting circuit comprising: A first delay inverter, wherein the input of the first delay inverter is the input signal, and the output is an odd-order delayed and inverted signal of the input signal; The second delay inverter has its input connected to the output of the first delay inverter, and its output is an even-numbered delayed and inverted signal of the input signal.
3. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 1, characterized in that, The threshold voltage of the first transistor is less than the threshold voltage of the fourth transistor; The threshold voltage of the second transistor is less than the threshold voltage of the sixth transistor.
4. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 1, characterized in that, The pull-down transistor circuit includes: The first pull-down transistor is controllably connected between a first output node and the first transistor under the action of a bias signal; The second pull-down transistor is controllably connected between a second output node and the second transistor under the action of the bias signal; The output nodes include the first output node and the second output node.
5. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 1, characterized in that, The pull-up transistor circuit includes: The first pull-up transistor is controllably connected between the high power supply voltage domain and the first output node under the action of a signal from the second output node; The second pull-up transistor is controllably connected between the high power supply voltage domain and the second output node under the action of the signal from the first output node; The output nodes include the first output node and the second output node.
6. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 5, characterized in that, The first pull-up transistor is also connected in parallel with a switching transistor, which can be controlled to be turned on or off under the action of a second set signal.
7. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 1, characterized in that, Also includes: A cross-coupled timing correction circuit, connected to the output node, is used to correct the duty cycle of the output signal when the duty cycle of the output signal exceeds a preset deviation range, so that the duty cycle remains within the preset deviation range.
8. The high-speed multi-voltage domain level conversion circuit with constant duty cycle according to claim 7, characterized in that, The cross-coupled timing correction circuit includes several cross-coupled delay inverters.