Low latency level shifting circuit with high cmti

Abstract

The application discloses a low-delay level shift circuit with high CMTI, comprising a V / C conversion circuit, wherein the V / C conversion circuit is connected with a C / V conversion circuit and a short-time pulse generation circuit respectively, the C / V conversion circuit is connected with a clamping circuit, a CLK generation circuit and a register circuit respectively, the short-time pulse generation circuit is connected with a high-frequency transient voltage zero elimination circuit, the high-frequency transient voltage zero elimination circuit is connected with the CLK generation circuit and the register circuit, and the CLK generation circuit is connected with the register circuit. The low-delay level shift circuit with high CMTI combines high-speed level shift technology with anti-common-mode noise technology; wherein, the high-speed level shift adopts a pre-storage technology, and the next output state is loaded in advance, so that the signal transmission delay of the level shift circuit is effectively reduced; on this basis, the circuit increases a common-mode noise compensation technology, and high-frequency transient common-mode noise can be collected to compensate the adverse effects of the common-mode noise on the level shift output signal.

Description

Technical Field

[0001] This invention belongs to the technical field of level shifting circuit structure, and relates to a low-delay level shifting circuit with high CMTI. Background Technology

[0002] With societal progress and the widespread adoption of 5G technology, electronic products are becoming increasingly important in our lives. Their core performance—power conversion—plays a decisive role in the overall system performance. As market demands for the functionality and performance of electronic products rise, designers are constantly seeking ways to improve product performance. Driver chips play a crucial role in signal amplification and isolation protection between the controller and power switching devices, and level shifting is the core circuit of the driver chip. Level shifting circuits are the "bridge connecting different voltage domains" in modern electronic systems. Their core value lies in achieving compatible communication between multiple chips or modules through precise level conversion, protecting devices from damage, and supporting low-power and high-speed transmission designs. Without level shifting circuits, multi-voltage domain electronic systems cannot function properly; they are the "invisible cornerstone" ensuring system stability, reliability, and functionality. In traditional half-bridge topology driver circuits, the rapid switching of power device states generates common-mode noise that floats and couples into the driver chip, causing transmission distortion in the level shift circuit and even shoot-through leading to device damage. Therefore, level shift circuits often require filtering circuits to remove common-mode noise. However, adding a filter increases the circuit's propagation delay. Furthermore, to prevent normal signals from being filtered out, the pulse width of the input signal needs to be increased, leading to increased conduction time and power consumption in LDMOS (Laterally Diffused Metal-Oxide-Semiconductor). Moreover, the maximum operating frequency of the gate driver chip for power devices in half-bridge topologies has become a significant factor limiting the high-frequency performance of power devices in high-frequency applications such as power supplies. Therefore, there is an urgent need to develop high-frequency power device driver chips. The operating frequency of traditional high-voltage driver chips is directly related to their propagation delay, and the filtering circuit after the high-voltage level shift circuit is the primary reason hindering the reduction of propagation delay in driver chips. Removing the filter circuit would reduce the driver chip's ability to suppress dv / dt (Derivative of Voltage with respect to Time) noise. How to resolve the contradiction between the two has become one of the key research areas.

[0003] In summary, existing technologies suffer from the problem that traditional level shifting circuits cannot simultaneously achieve both common-mode noise immunity and low latency. Summary of the Invention

[0004] The purpose of this invention is to provide a low-delay level shifting circuit with high CMTI, which solves the problem that traditional level shifting circuits in the prior art cannot simultaneously achieve common-mode noise immunity and low delay.

[0005] The technical solution adopted in this invention is a low-delay level shifting circuit with high CMTI, including a V / C conversion circuit. The V / C conversion circuit is connected to a C / V conversion circuit and a short-time pulse generation circuit. The C / V conversion circuit is connected to a clamping circuit, a CLK generation circuit, a register circuit, and a high-frequency transient voltage zero-clearing circuit. The short-time pulse generation circuit is connected to the high-frequency transient voltage zero-clearing circuit. The high-frequency transient voltage zero-clearing circuit is connected to the CLK generation circuit and the register circuit. The CLK generation circuit and the register circuit are connected.

[0006] The invention is further characterized by:

[0007] The V / C conversion circuit includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain of the transistor P in the C / V conversion circuit 1H Drain connection;

[0008] transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain of the transistor P in the C / V conversion circuit 2H Drain connection;

[0009] Inverter I O The input terminal and input signal V IN connect.

[0010] The C / V conversion circuit includes transistor P. 1H and transistor P 2H transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1H The drain connection of transistor P 1H The source and clamping circuit, the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit. A The input terminal is connected;

[0011] transistor P 2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 2H The drain connection of transistor P 2H The source and clamping circuit of transistor P2, the drain of transistor N2, and the inverter I in the CLK generation circuit. B The input terminal is connected.

[0012] The clamping circuit includes transistors N1, N2, P1, and P2. The gate of transistor N1 is connected to the gate of transistor P1, and the inverter I in the CLK generation circuit is connected to the gate of transistor P1. D The output terminal is connected, and the source of transistor N1 is connected to the floating ground of the high-voltage domain. V SSH Connections: the drain of transistor N1 and the drain of transistor P1, and transistor P in the C / V conversion circuit. 1H The source connection;

[0013] The gates of transistor N2 and P2, along with the inverter I in the CLK generation circuit, are connected. C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSH Connections: the drain of transistor N2 and the drain of transistor P2, and transistor P in the C / V conversion circuit. 2H The source connection;

[0014] The source of transistor P1, the source of transistor P2, and the power supply voltage of the high-voltage domain. V DDH connect.

[0015] The CLK generation circuit includes a NAND gate M3. The inputs of NAND gate M3 are connected to the inputs R and S of the SR flip-flop L1 in the register circuit, respectively. The output of NAND gate M3 is connected to the inverter I. E The input terminals of the SR flip-flop L2 in the register circuit are connected to the input terminal CLK, and the inverter I... E The output terminal is connected to the input CLK terminal of SR flip-flop L1 in the register circuit;

[0016] The CLK generation circuit also includes an inverter I. A Inverter I B Inverter I C Inverter I D and inverter I E .

[0017] Inverter IA The input terminal is connected to transistor P in the C / V conversion circuit. 1H The source, drain of transistor P1, and drain of transistor N1 in the clamping circuit are connected, and the inverter I... A The output terminal of inverter I C The input terminal of the transistor, the drain of transistor N5 in the high-frequency transient voltage zeroing circuit, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in the register circuit are connected.

[0018] Inverter I C The input terminal of inverter I A The output terminal, the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in the register circuit are connected, and the inverter I is connected. C The output terminal is connected to the gate of transistor N2 and the gate of transistor P2 in the clamping circuit.

[0019] Inverter I B The input terminal is connected to transistor P in the C / V conversion circuit. 2H The source, drain of transistor P2, and drain of transistor N2 in the clamping circuit are connected, and the inverter I... B The output terminal of inverter I D The input terminal of the transistor, the drain of transistor N4 in the high-frequency transient voltage zeroing circuit, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in the register circuit are connected.

[0020] Inverter I D The input terminal of inverter I B The output terminal, the drain of transistor N4 in the high-frequency transient voltage zero-suppression circuit, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in the register circuit are connected; inverter I D The output terminal is connected to the gate of transistor N1 and the gate of transistor P1 in the clamping circuit.

[0021] The register circuit includes SR flip-flops L1 and L2. The input CLK terminal of SR flip-flop L1 is connected to the inverter I in the CLK generation circuit. E Connect the output terminal;

[0022] The input S terminal of SR flip-flop L1 is connected to the inverter I in the CLK generation circuit. A The output terminal of inverter I C The input terminal of the transistor, the drain of transistor N5 in the high-frequency transient voltage zeroing circuit, and the input terminal of NAND gate M3 are connected.

[0023] The input R terminal of SR flip-flop L1 is connected to the inverter I in the CLK generation circuit. B The output terminal of inverter I DThe input terminal of the gate is connected to the drain of transistor N4 in the high-frequency transient voltage zeroing circuit and the input terminal of NAND gate M3.

[0024] The output Q of SR flip-flop L1 is connected to the input S of SR flip-flop L2, and the output of SR flip-flop L1 is... The terminal is connected to the input R terminal of the SR flip-flop L2;

[0025] The input CLK terminal of SR flip-flop L2 is connected to the output terminal of NAND gate M3 in the CLK generation circuit; the output of SR flip-flop L2... The terminal is the output signal OUT.

[0026] The high-frequency transient voltage zero-suppression circuit includes transistor N. 3H transistor P 3H Clamping diode D1, AND gate M1, AND gate M2, transistor N3, transistor N4, transistor N5, and transistors P3 and P4, transistor N 3H The gate of transistor N is connected to the output terminal of the short-time pulse generation circuit. 3H The source of transistor N is grounded. 3H The drain and transistor P 3H Drain connection;

[0027] transistor P 3H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 3H The source of transistor P3 is connected to the drain of transistor P3, the gate of transistor P3, the gate of transistor P4, and the output terminal of clamping diode D1.

[0028] The input terminal of clamping diode D1 is connected to the floating ground of the high-voltage domain. V SSH connect.

[0029] The drain and gate of transistor P3, the gate of transistor P4, the output of clamping diode D1, and transistor P... 3H The source of transistor P3 is connected to the power supply voltage of the high-voltage domain. V DDH connect;

[0030] The gate of transistor P4 and the drain of transistor P3, the gate of transistor P3, the output terminal of clamping diode D1, and transistor P 3H The source of transistor P4 is connected to the power supply voltage of the high-voltage domain. V DDHThe connections are as follows: the drain of transistor P4 is connected to the gate of transistor N3, the drain of transistor N3, one input of AND gate M1, and one input of AND gate M2; the other input of AND gate M1 is connected to the drain of transistor N4, and the inverter I in the CLK generation circuit. B Output terminal, inverter I D The input terminal of the AND gate M3 is connected to the input terminal of the AND gate M2, the input terminal R of the SR flip-flop L1 in the register circuit, and the other input terminal of the AND gate M2 is connected to the output signal OUT.

[0031] The gate of transistor N3 is connected to the drain of transistor N3, the drain of transistor P4, one input of AND gate M1, and one input of AND gate M2. The source of transistor N3 is connected to the floating ground of the high-voltage domain. V SSH connect;

[0032] The output of AND gate M1 is connected to the gate of transistor N5, and the source of transistor N5 is connected to the floating ground of the high-voltage domain. V SSH The connection is made between the drain of transistor N5 and the inverter I in the CLK generation circuit. A Output terminal, inverter I C The input terminal of the SR flip-flop L1 in the register circuit is connected to the input terminal of the NAND gate M3.

[0033] The output of AND gate M2 is connected to the gate of transistor N4, and the source of transistor N4 is connected to the floating ground of the high-voltage domain. V SSH The connection is made between the drain of transistor N4 and the inverter I in the CLK generation circuit. B Output terminal, inverter I D The input terminal of the gate is connected to the input terminal of the NAND gate M3 and the input terminal R of the SR flip-flop L1 in the register circuit.

[0034] The beneficial effects of this invention are as follows: This invention combines high-speed level shifting technology with common-mode noise suppression technology; wherein, the high-speed level shifting adopts pre-storage technology, which effectively reduces the signal transmission delay of the level shifting circuit by loading the next output state in advance; on this basis, the circuit adds common-mode noise compensation technology, which can collect high-frequency transient common-mode noise to compensate for the adverse effects of common-mode noise on the level shifting output signal; since this invention does not use the RC (Resistance-Capacitance) filter circuit in traditional level shifting, the signal transmission delay is effectively reduced; at the same time, the high-frequency transient voltage zero-suppression circuit will be turned off when there is no noise, which will not affect the signal transmission delay and can further reduce the power consumption of the circuit. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the high CMTI low delay level shifting circuit of the present invention;

[0036] Figure 2 This is a schematic diagram of the connection structure of the high CMTI low delay level shifting circuit of the present invention.

[0037] In the diagram, 1 is the V / C conversion circuit; 2 is the C / V conversion circuit; 3 is the clamping circuit; 4 is the CLK generation circuit; 5 is the register circuit; 6 is the high-frequency transient voltage zeroing circuit; and 7 is the short-time pulse generation circuit. Detailed Implementation

[0038] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0039] High CMTI low delay level shifting circuits, such as Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0040] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P 1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P 2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0041] C / V conversion circuit 2 includes transistor P 1H and transistor P 2H transistor P 1HThe gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1 1H The drain connection of transistor P 1H The source and clamping circuit 3 includes the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit 4. A Input terminal connection; transistor P 2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 1 2H The drain connection of transistor P 2H The source and clamping circuit 3, the drain of transistor P2, the drain of transistor N2, and the inverter I in CLK generation circuit 4. B The input terminal is connected.

[0042] Clamping circuit 3 includes transistors N1, N2, P1, and P2. The gate of transistor N1 is connected to the gate of transistor P1, and the inverter I in CLK generation circuit 4 is connected to the gate of transistor P1. D The output terminal is connected, and the source of transistor N1 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N1 and the drain of transistor P1, and between transistor P1 in the C / V conversion circuit 2. 1H The source connection of transistor N2 is connected to the gate of transistor P2 and the inverter I in circuit 4 of CLK generation circuit. C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N2 and the drain of transistor P2, and between transistor P in the C / V conversion circuit 2. 2H The source connections of transistors P1 and P2 are connected to the power supply voltage of the high-voltage domain. V DDH connect.

[0043] CLK generation circuit 4 includes NAND gate M3. The input terminals of NAND gate M3 are connected to the input R terminal and input S terminal of SR flip-flop L1 in register circuit 5, respectively. The output terminal of NAND gate M3 is connected to inverter I. E The input terminal of the inverter is connected to the input CLK terminal of the SR flip-flop L2 in register circuit 5, and the inverter I is connected to the input terminal of the register circuit 5. E The output terminal is connected to the input CLK terminal of SR flip-flop L1 in register circuit 5; CLK generation circuit 4 also includes inverter I. A Inverter I BInverter I C Inverter I D and inverter I E Inverter I A The input terminal is connected to transistor P in C / V conversion circuit 2. 1H The source, drain of transistor P1 in clamping circuit 3, and drain of transistor N1 are connected, and inverter I... A The output terminal of inverter I C The input terminal of the inverter is connected to the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5; inverter I C The input terminal of inverter I A The output terminal, the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5 are connected, and inverter I is connected. C The output terminal is connected to the gate of transistor N2 and the gate of transistor P2 in clamping circuit 3. Inverter I B The input terminal is connected to transistor P in C / V conversion circuit 2. 2H The source, drain of transistor P2 in clamping circuit 3, and drain of transistor N2 are connected, and inverter I... B The output terminal of inverter I D The input terminal of the inverter is connected to the drain of transistor N4 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5; inverter I D The input terminal of inverter I B The output terminal, the drain of transistor N4 in the high-frequency transient voltage zeroing circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5 are connected; inverter I D The output terminal is connected to the gate of transistor N1 and the gate of transistor P1 in clamping circuit 3.

[0044] Register circuit 5 includes SR flip-flop L1 and SR flip-flop L2. The input CLK terminal of SR flip-flop L1 is connected to inverter I in CLK generation circuit 4. E The output terminal is connected; the input S terminal of SR flip-flop L1 is connected to the inverter I in CLK generation circuit 4. A The output terminal of inverter I C The input terminal of the high-frequency transient voltage zero-suppression circuit 6, the drain of transistor N5, and the input terminal of NAND gate M3 are connected; the input R terminal of SR flip-flop L1 is connected to inverter I in CLK generation circuit 4. B The output terminal of inverter I DThe input terminal of the high-frequency transient voltage zero-suppression circuit 6, the drain of transistor N4, and the input terminal of NAND gate M3 are connected; the output Q terminal of SR flip-flop L1 is connected to the input S terminal of SR flip-flop L2, and the output of SR flip-flop L1 is connected to the input S terminal of SR flip-flop L2. The input terminal R of SR flip-flop L2 is connected to the input terminal R; the input terminal CLK of SR flip-flop L2 is connected to the output terminal of NAND gate M3 in CLK generation circuit 4; the output of SR flip-flop L2... The terminal is the output signal OUT.

[0045] The high-frequency transient voltage zero-suppression circuit 6 includes transistor N. 3H transistor P 3H Clamping diode D1, AND gate M1, AND gate M2, transistor N3, transistor N4, transistor N5, and transistors P3 and P4, transistor N 3H The gate of transistor N is connected to the output terminal of short-time pulse generation circuit 7. 3H The source of transistor N is grounded. 3H The drain and transistor P 3H Drain connection; transistor P 3H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 3H The source of transistor P4 is connected to the drain of transistor P3, the gate of transistor P3, the gate of transistor P4, and the output of clamping diode D1; the input of clamping diode D1 is connected to the floating ground of the high-voltage domain. V SSH connect.

[0046] The drain and gate of transistor P3, the gate of transistor P4, the output of clamping diode D1, and transistor P... 3H The source of transistor P3 is connected to the power supply voltage of the high-voltage domain. V DDH Connections: Gate of transistor P4 to drain of transistor P3, gate of transistor P3, output of clamping diode D1, transistor P... 3H The source of transistor P4 is connected to the power supply voltage of the high-voltage domain. V DDH The connections are as follows: the drain of transistor P4 is connected to the gate of transistor N3, the drain of transistor N3, one input of AND gate M1, and one input of AND gate M2; the other input of AND gate M1 is connected to the drain of transistor N4 and the inverter I in CLK generation circuit 4. B Output terminal, inverter I DThe input terminal of the NAND gate M3 is connected to the input terminal of the SR flip-flop L1 in register circuit 5, and the other input terminal of the AND gate M2 is connected to the output signal OUT; the gate of transistor N3 is connected to the drain of transistor N3, the drain of transistor P4, one input terminal of AND gate M1, and one input terminal of AND gate M2; the source of transistor N3 is connected to the floating ground of the high voltage domain. V SSH Connections: The output of AND gate M1 is connected to the gate of transistor N5, and the source of transistor N5 is connected to the floating ground of the high-voltage domain. V SSH The connection is made between the drain of transistor N5 and the inverter I in circuit 4 of CLK generation. A Output terminal, inverter I C The input terminal of the AND gate M2 is connected to the input terminal of the NAND gate M3, and the input S terminal of the SR flip-flop L1 in register circuit 5; the output terminal of the AND gate M2 is connected to the gate of transistor N4, and the source of transistor N4 is connected to the floating ground of the high voltage domain. V SSH The connection is made between the drain of transistor N4 and the inverter I in circuit 4 of CLK generation. B Output terminal, inverter I D The input terminal of the gate is connected to the input terminal of the NAND gate M3 and the input terminal R of the SR flip-flop L1 in register circuit 5.

[0047] This invention ensures low propagation delay in the level shifting circuit while maintaining strong immunity to transient noise, thus increasing the circuit's CMTI (Common Mode Transient Immunity). In this invention, the V / C (Voltage / Current) conversion circuit 1 employs an HV-NMOS (High-Voltage N-type Metal-Oxide-Semiconductor) transistor. 1H / N 2H Input signal V IN Converted to its drain current; C / V (Current / Voltage) conversion circuit 2 uses HV-PMOS (High Voltage P-channel Metal Oxide Semiconductor) transistor P 1H / P 2H The drain current is transferred to the voltage, isolating the high drain voltage and protecting devices in the high voltage domain; the clamping circuit 3 uses NMOS (N-type Metal-Oxide-Semiconductor) transistors N1 / N2 to clamp the voltage.V A / V B Not less than V SSH CLK (Clock) generation circuit 4 is used to generate control signals. V CK1 and V CK2 This puts Pre-Reg (Pre-Register) and Read-Reg (Read-Register) into latch or transfer mode; Register circuit 5 is used to preload the next output state in the pre-register when the read register outputs a state, reducing the transmission delay of the level shift circuit.

[0048] like Figure 1 and Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O V / C conversion circuit 1 converts the input signal V IN Converted to its drain current, when the input is low, transistor N 1H Off, transistor N 2H When the input is high, transistor N is on. 2H Off, transistor N 1H open.

[0049] C / V conversion circuit 2 includes transistor P 1H transistor P 2H The C / V conversion circuit 2 transfers the drain current transmitted by the V / C conversion circuit 1 to the voltage, isolates the high drain voltage, and protects the devices in the high voltage domain.

[0050] Clamping circuit 3 includes transistor N1 and transistor N2. Clamping circuit 3 is used for clamping. V A / V B The voltage must not be lower than V SSH .

[0051] CLK generation circuit 4 includes NAND gate M3 and inverter I. A Inverter I B Inverter I C Inverter I D Inverter I E The two inputs of NAND gate M3 are connected to the S and R terminals of SR flip-flop L1, respectively, and one of its outputs is connected to inverter I. E One without an inverter is used to generate control signals.V CK1 and V CK2 This puts Pre-Reg and Read-Reg in latch or transfer mode.

[0052] Register circuit 5 includes SR (Set-Reset) flip-flops L1 and L2. Each SR flip-flop internally consists of two OR gates and two NAND gates. The inputs of the two OR gates are connected to the R, S, and CLK terminals respectively, and their outputs are connected to the inputs of the NAND gates. Furthermore, the inputs and outputs of the NAND gates are cross-coupled. In register circuit 5, when the register is in an output state, the pre-register preloads the next output state, reducing the propagation delay of the level shift circuit.

[0053] The high-frequency transient voltage zero-suppression circuit 6 includes transistor N. 3H transistor P 3H The current mirror is composed of clamping diode D1, AND gate M1, AND gate M2, transistors N3, N4, and N5, as well as transistors P3 and P4. When common-mode noise occurs, the high-frequency transient voltage zeroing circuit 6 compensates for the potentials at points S and R, and clamps the potentials at either point R or S to prevent erroneous signal reversals due to common-mode noise.

[0054] Example 1

[0055] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0056] Example 2

[0057] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0058] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P 1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P 2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0059] Example 3

[0060] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0061] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P 1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0062] C / V conversion circuit 2 includes transistor P 1H and transistor P 2H transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1 1H The drain connection of transistor P 1H The source and clamping circuit 3 includes the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit 4. A Input terminal connection; transistor P 2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 1 2H The drain connection of transistor P 2H The source and clamping circuit 3, the drain of transistor P2, the drain of transistor N2, and the inverter I in CLK generation circuit 4. B The input terminal is connected.

[0063] Example 4

[0064] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0065] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P 2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0066] C / V conversion circuit 2 includes transistor P 1H and transistor P 2H transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1 1H The drain connection of transistor P 1H The source and clamping circuit 3 includes the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit 4. A Input terminal connection; transistor P 2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 1 2H The drain connection of transistor P 2H The source and clamping circuit 3, the drain of transistor P2, the drain of transistor N2, and the inverter I in CLK generation circuit 4. B The input terminal is connected.

[0067] Clamping circuit 3 includes transistors N1, N2, P1, and P2. The gate of transistor N1 is connected to the gate of transistor P1, and the inverter I in CLK generation circuit 4 is connected to the gate of transistor P1. D The output terminal is connected, and the source of transistor N1 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N1 and the drain of transistor P1, and between transistor P1 in the C / V conversion circuit 2. 1H The source connection of transistor N2 is connected to the gate of transistor P2 and the inverter I in circuit 4 of CLK generation circuit. C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N2 and the drain of transistor P2, and between transistor P in the C / V conversion circuit 2. 2HThe source connections of transistors P1 and P2 are connected to the power supply voltage of the high-voltage domain. V DDH connect.

[0068] Example 5

[0069] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0070] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N 1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P 1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P 2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0071] C / V conversion circuit 2 includes transistor P 1H and transistor P 2H transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1 1H The drain connection of transistor P 1H The source and clamping circuit 3 includes the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit 4. A Input terminal connection; transistor P2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 1 2H The drain connection of transistor P 2H The source and clamping circuit 3, the drain of transistor P2, the drain of transistor N2, and the inverter I in CLK generation circuit 4. B The input terminal is connected.

[0072] Clamping circuit 3 includes transistors N1, N2, P1, and P2. The gate of transistor N1 is connected to the gate of transistor P1, and the inverter I in CLK generation circuit 4 is connected to the gate of transistor P1. D The output terminal is connected, and the source of transistor N1 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N1 and the drain of transistor P1, and between transistor P1 in the C / V conversion circuit 2. 1H The source connection of transistor N2 is connected to the gate of transistor P2 and the inverter I in circuit 4 of CLK generation circuit. C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N2 and the drain of transistor P2, and between transistor P in the C / V conversion circuit 2. 2H The source connections of transistors P1 and P2 are connected to the power supply voltage of the high-voltage domain. V DDH connect.

[0073] CLK generation circuit 4 includes NAND gate M3. The input terminals of NAND gate M3 are connected to the input R terminal and input S terminal of SR flip-flop L1 in register circuit 5, respectively. The output terminal of NAND gate M3 is connected to inverter I. E The input terminal of the inverter is connected to the input CLK terminal of the SR flip-flop L2 in register circuit 5, and the inverter I is connected to the input terminal of the register circuit 5. E The output terminal is connected to the input CLK terminal of SR flip-flop L1 in register circuit 5; CLK generation circuit 4 also includes inverter I. A Inverter I B Inverter I C Inverter I D and inverter I E .

[0074] Inverter I A The input terminal is connected to transistor P in C / V conversion circuit 2. 1H The source, drain of transistor P1 in clamping circuit 3, and drain of transistor N1 are connected, and inverter I... AThe output terminal of inverter I C The input terminal of the inverter is connected to the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5; inverter I C The input terminal of inverter I A The output terminal, the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5 are connected, and inverter I is connected. C The output terminal is connected to the gate of transistor N2 and the gate of transistor P2 in clamping circuit 3.

[0075] Inverter I B The input terminal is connected to transistor P in C / V conversion circuit 2. 2H The source, drain of transistor P2 in clamping circuit 3, and drain of transistor N2 are connected, and inverter I... B The output terminal of inverter I D The input terminal of the inverter is connected to the drain of transistor N4 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5; inverter I D The input terminal of inverter I B The output terminal, the drain of transistor N4 in the high-frequency transient voltage zeroing circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5 are connected; inverter I D The output terminal is connected to the gate of transistor N1 and the gate of transistor P1 in clamping circuit 3.

[0076] Example 6

[0077] This embodiment proposes a low-delay level shifting circuit with high CMTI, such as... Figure 1 As shown, it includes a V / C conversion circuit 1, which is connected to a C / V conversion circuit 2 and a short-time pulse generation circuit 7. The C / V conversion circuit 2 is connected to a clamping circuit 3, a CLK generation circuit 4, a register circuit 5, and a high-frequency transient voltage zero-elimination circuit 6. The short-time pulse generation circuit 7 is connected to the high-frequency transient voltage zero-elimination circuit 6, which is connected to the CLK generation circuit 4 and the register circuit 5. The CLK generation circuit 4 and the register circuit 5 are also connected.

[0078] Combination Figure 2 As shown, the V / C conversion circuit 1 includes transistor N. 1H transistor N 2H and inverter I O transistor N 1H gate and input signal V IN Connection, transistor N1H The source is grounded, N 1H The drain and C / V conversion circuit 2 of transistor P 1H Drain connection; transistor N 2H The gate and inverter I O The output terminal is connected to transistor N. 2H The source of transistor N is grounded. 2H The drain and C / V conversion circuit 2 of transistor P 2H Drain connection; Inverter I O The input terminal and input signal V IN connect.

[0079] C / V conversion circuit 2 includes transistor P 1H and transistor P 2H transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 1H The drain of the transistor N in the V / C conversion circuit 1 1H The drain connection of transistor P 1H The source and clamping circuit 3 includes the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit 4. A Input terminal connection; transistor P 2H The gate and the floating ground of the high voltage domain V SSH Connection, transistor P 2H The drain of the transistor N in the V / C conversion circuit 1 2H The drain connection of transistor P 2H The source and clamping circuit 3, the drain of transistor P2, the drain of transistor N2, and the inverter I in CLK generation circuit 4. B The input terminal is connected.

[0080] Clamping circuit 3 includes transistors N1, N2, P1, and P2. The gate of transistor N1 is connected to the gate of transistor P1, and the inverter I in CLK generation circuit 4 is connected to the gate of transistor P1. D The output terminal is connected, and the source of transistor N1 is connected to the floating ground of the high-voltage domain. V SSH The connections are made between the drain of transistor N1 and the drain of transistor P1, and between transistor P1 in the C / V conversion circuit 2. 1H The source connection of transistor N2 is connected to the gate of transistor P2 and the inverter I in circuit 4 of CLK generation circuit. C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSHThe connections are made between the drain of transistor N2 and the drain of transistor P2, and between transistor P in the C / V conversion circuit 2. 2H The source connections of transistors P1 and P2 are connected to the power supply voltage of the high-voltage domain. V DDH connect.

[0081] CLK generation circuit 4 includes NAND gate M3. The input terminals of NAND gate M3 are connected to the input R terminal and input S terminal of SR flip-flop L1 in register circuit 5, respectively. The output terminal of NAND gate M3 is connected to inverter I. E The input terminal of the inverter is connected to the input CLK terminal of the SR flip-flop L2 in register circuit 5, and the inverter I is connected to the input terminal of the register circuit 5. E The output terminal is connected to the input CLK terminal of SR flip-flop L1 in register circuit 5; CLK generation circuit 4 also includes inverter I. A Inverter I B Inverter I C Inverter I D and inverter I E Inverter I A The input terminal is connected to transistor P in C / V conversion circuit 2. 1H The source, drain of transistor P1 in clamping circuit 3, and drain of transistor N1 are connected, and inverter I... A The output terminal of inverter I C The input terminal of the inverter is connected to the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5; inverter I C The input terminal of inverter I A The output terminal, the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input S terminal of SR flip-flop L1 in register circuit 5 are connected, and inverter I is connected. C The output terminal is connected to the gate of transistor N2 and the gate of transistor P2 in clamping circuit 3. Inverter I B The input terminal is connected to transistor P in C / V conversion circuit 2. 2H The source, drain of transistor P2 in clamping circuit 3, and drain of transistor N2 are connected, and inverter I... B The output terminal of inverter I D The input terminal of the inverter is connected to the drain of transistor N4 in the high-frequency transient voltage zero-suppression circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5; inverter I D The input terminal of inverter I B The output terminal, the drain of transistor N4 in the high-frequency transient voltage zeroing circuit 6, the input terminal of NAND gate M3, and the input R terminal of SR flip-flop L1 in register circuit 5 are connected; inverter ID The output terminal is connected to the gate of transistor N1 and the gate of transistor P1 in clamping circuit 3.

[0082] Register circuit 5 includes SR flip-flop L1 and SR flip-flop L2. The input CLK terminal of SR flip-flop L1 is connected to inverter I in CLK generation circuit 4. E The output terminal is connected; the input S terminal of SR flip-flop L1 is connected to the inverter I in CLK generation circuit 4. A The output terminal of inverter I C The input terminal of the high-frequency transient voltage zero-suppression circuit 6, the drain of transistor N5, and the input terminal of NAND gate M3 are connected; the input R terminal of SR flip-flop L1 is connected to inverter I in CLK generation circuit 4. B The output terminal of inverter I D The input terminal of the high-frequency transient voltage zero-suppression circuit 6, the drain of transistor N4, and the input terminal of NAND gate M3 are connected; the output Q terminal of SR flip-flop L1 is connected to the input S terminal of SR flip-flop L2, and the output of SR flip-flop L1 is connected to the input S terminal of SR flip-flop L2. The input terminal R of SR flip-flop L2 is connected to the input terminal R; the input terminal CLK of SR flip-flop L2 is connected to the output terminal of NAND gate M3 in CLK generation circuit 4; the output of SR flip-flop L2... The terminal is the output signal OUT.

[0083] In V / C conversion circuit 1, transistor N 1H The gate is configured to receive the input signal. V IN transistor N 1H The source of transistor N is configured to be grounded. 1H The drain is configured to be connected to transistor P in C / V conversion circuit 2. 1H The drain of the transistor; N 2H The gate is configured to be connected to inverter I O The output of transistor N 2H The source of transistor N is configured to be grounded. 2H The drain is configured to be connected to transistor P in C / V conversion circuit 2. 2H Drain; Inverter I O The input is configured to receive the input signal. V IN .

[0084] V / C converter circuit 1 is used to convert the input signal V IN Converted to its drain current; V / C conversion circuit 1 through input signal V IN and inverter I O Control transistor N 1H transistor N 2HThe circuit switches on and off, converting voltage signals into current signals and transmitting them to the C / V conversion circuit 2. When the input signal... V IN When it is low, transistor N 1H When closed, the input signal passes through inverter I. O Then comes high, transistor N 2H Therefore, transistor N is turned on. 1H There is no current in the branch, transistor N 2H Current flows through the branch in which it is located, transistor N 2H Input signal V IN It is converted into its drain current, and the current signal is transmitted to C / V conversion circuit 2.

[0085] Transistor P in C / V conversion circuit 2 1H The gate is configured to be connected to a floating ground in the high-voltage domain. V SSH transistor P 1H The drain is configured to be connected to transistor N. 1H The drain of the transistor P 1H The source is configured to be connected to the drain of transistor P1, the drain of transistor N1, and the inverter I in clamping circuit 3. A Input; transistor P 2H The gate is configured to be connected to a floating ground in the high-voltage domain. V SSH transistor P 2H The drain is configured to be connected to transistor N. 2H The drain of the transistor P 2H The source is configured to be connected to the drain of transistor P2, the drain of transistor N2, and inverter I in clamping circuit 3. B The input. C / V conversion circuit 2 is used to transfer the drain current conducted from V / C conversion circuit 1 to voltage, isolating high drain voltage and protecting devices in the high-voltage domain; transistor P 1H transistor P 2H The gate is connected to the floating ground of the high voltage domain. V SSH It acts as a bridge connecting the low-voltage and high-voltage domains. When the input signal is low, transistor N... 2H On, transistor N 2H The drain and transistor P 2H The drain of transistor P is at a low level GND, due to the low level GND. 2H The gate is connected to the high voltage domain V SSH transistor P 2H Conduction, at this time V B When the voltage is low, similarly, when the input signal is high, transistor N...1H and transistor P 1H Conduction, V A Since the voltage is low, the C / V conversion circuit 2 transfers the drain current conducted from the V / C conversion circuit 1 to the voltage, thus realizing the connection between the low voltage domain and the high voltage domain.

[0086] In clamping circuit 3, the gate of transistor N1 is configured to be connected to the gate of transistor P1 and inverter I. D The source of transistor N1 is configured to be connected to a floating ground in the high-voltage domain at the output. V SSH The gate of transistor N2 is configured to be connected to the gate of transistor P2 and inverter I. C The output of transistor N2 is configured such that the source of transistor N2 is connected to a floating ground in the high-voltage domain. V SSH The source of transistor P1 is configured to be connected to a high-voltage domain. V DDH The source of transistor P2 is configured to be connected to a high-voltage domain. V DDH Clamping circuit 3 is used for clamping. V A / V B The voltage must not be lower than V SSH ;when V IN For low, transistor N 2H and transistor P 2H When both are conducting simultaneously, at this time V B It will be instantly pulled low to GND, but at this time transistor N2 will immediately turn on, making V B Floating ground clamped in high-voltage domain V SSH Therefore, the voltage in the high-voltage domain will not be lower than the floating ground voltage in the high-voltage domain. V SSH .

[0087] Inverter I in CLK generation circuit 4 A The output is configured to connect to inverter I. C The input of the inverter, one input terminal of the NAND gate M3, the input S terminal of the SR flip-flop L1 in register circuit 5, and the drain of transistor N5 in the high-frequency transient voltage zero-suppression circuit 6; inverter I B The output is configured to connect to inverter I. D The inputs of the NAND gate M3, the other input of the NAND gate M3, the input R of the SR flip-flop L1 in register circuit 5, and the drain of transistor N4 in high-frequency transient voltage zero-suppression circuit 6; the output of the NAND gate M3 is configured to connect to inverter I.E The input terminals of the register circuit 5 and the input terminal CLK of the SR flip-flop L2; inverter I E The output is configured to be connected to the input CLK terminal of the SR flip-flop L1 in register circuit 5. CLK generation circuit 4 is used to generate control signals. V CK1 and V CK2 This puts the pre-register and read register into latch or transfer mode; the CLK generation circuit 4 includes a NAND gate M3 and an inverter I. A Inverter I B Inverter I C Inverter I D Inverter I E Through inverter I A Inverter I B Inverter I C Inverter I D Inverter I E The related logic circuit composed of AND and NAND gates M3 outputs two opposite CLK signals to control the transmission and latching of the register. When CLK1=0 and CLK2=1, SR flip-flop L1 is in the transmission state and SR flip-flop L2 is in the latching state; when CLK1=1 and CLK2=0, SR flip-flop L1 is in the latching state and SR flip-flop L2 is in the transmission state.

[0088] when V IN From GND rapid changes to V DD First, transistor N is turned on. 1H This allows it to operate in saturation, and then it is turned off after a delay of the inverter Io. To ensure the normal operation of the high-side logic circuit, it is essential to successfully... V A Control at inverter I A Below the threshold. V A Below inverter I A Before the threshold, the current N 1H / N 2H The current is greater than the current of transistor P1 / transistor P2. When the voltage V A Below I A When the threshold is reached, inverter I A The output state is reversed. Therefore, transistor P2 is pulled up by the voltage. V B At the beginning, V B Below inverter I B The threshold, VA = V B =1, within this critical time interval V CK1 =1, V CK2 =0. When the voltage V B Higher than inverter I B When the threshold is reached, V B =0. Transistor P1 is off. V A The conducting transistor N1 is clamped to floating ground. V SSH Then transistor N 1H Entering the linear region, reducing transistor N 1H The drain current at this time V CK1 =0, V CK2 =1.

[0089] In register circuit 5, the output port Q of SR flip-flop L1 is configured to connect to the input port S of SR flip-flop L2, and the output port... Configured to connect to the input port R of SR flip-flop L2; the output port of SR flip-flop L2 Configured as output OUT. Register circuit 5 is used to preload the next output state in the pre-register when reading the register output state, reducing the propagation delay of the level shift circuit; when... V IN From GND rapid changes to V DD At that time, within this critical time interval, V CK1 =1, V CK2 =0, the preregister operates in latch mode, and the read register operates in jump mode. The data stored in the preregister... V IN The state = 1 transitions to the output of the read register. Therefore, V OH =1. The current input state can be considered as... V IN =1 was transmitted during this period. V OH When the voltage V B Higher than inverter I B When the threshold is reached, V B =0. Transistor P1 is off. V AThe conducting transistor N1 is clamped to floating ground. V SSH Then transistor N 1H Entering the linear region, reducing transistor N 1H The drain current. Due to V CK1 =0, V CK2 =1, the preregister operates in transfer mode, and the read register operates in latch mode. The input to the preregister is... V A1 =1, V B1 =0, the output Q1 of the preregister is 0. The preregister has been reloaded. V IN The next state is then determined, and the system waits for the falling edge to complete the level shifting function.

[0090] High-frequency transient voltage zero-suppression circuit 6, transistor N 3H The gate of transistor N is configured to be connected to the output of short-time pulse generation circuit 7. 3H The source of transistor N is configured to be connected to GND. 3H The drain is configured to be connected to transistor P 3H The drain of the transistor; P 3H The gate is configured to be connected to a floating ground in the high-voltage domain. V SSH transistor P 3H The source is configured to be connected to the drain and gate of transistor P3, the gate of transistor P4, and the output of clamping diode D1; the input of clamping diode D1 is configured to be connected to the floating ground of the high-voltage domain. V SSH One input of AND gate M1 is configured to be connected to port R in CLK generation circuit 4, and the other input is configured to be connected to the gate and drain of transistor N3, the drain of transistor P4, and one input port of AND gate M2. The output of AND gate M1 is configured to be connected to the gate of transistor N5. The other input of AND gate M2 is configured to be connected to the output signal OUT, and the output of AND gate M1 is configured to be connected to the gate of transistor N4. The source of transistor N3 is configured to be connected to the floating ground of the high-voltage domain. V SSH The source of transistor N4 is configured to be connected to a floating ground in the high-voltage domain. V SSH The drain of transistor N4 is configured to be connected to port R in CLK generation circuit 4; the source of transistor N5 is configured to be connected to the floating ground of the high-voltage domain. V SSH The drain of transistor N5 is configured to be connected to the S port in CLK generation circuit 4; the source of transistor P3 is configured to be connected to the high-voltage domain. VDDH The source of transistor P4 is configured to be connected to a high-voltage domain. V DDH .

[0091] The high-frequency transient voltage zero-suppression circuit 6 is used to suppress the effects of common-mode noise. When the common-mode noise originates from... V SSH When coupled into the circuit, because LDMOS has a large parasitic capacitance, therefore V A , V B The potential at two points can reverse incorrectly, generating an incorrect clock signal, which in turn causes the register to be read incorrectly, resulting in an incorrect output signal. During the conduction period of the power device, common-mode noise affects the output, causing... V B A drop in point potential causes an erroneous signal flip at point R, generating an additional CLK signal and thus outputting an incorrect signal. During the power device's turn-off period, common-mode noise affects the output, causing... V A When the potential at point S decreases, an erroneous signal flip occurs at point S, generating an additional CLK signal and consequently outputting an incorrect signal. Therefore, a high-frequency transient voltage zero-sweeping circuit is used to compensate for the potentials of S and R, clamping the potentials of either point R or S to prevent erroneous signal inversions caused by common-mode noise.

[0092] The high-frequency transient voltage zero-suppression circuit 6 only activates when common-mode noise is present and shuts off when there is no noise, thus not affecting signal transmission delay. By using common-mode noise to compensate for erroneous signals generated by it, the circuit maintains strong transient noise immunity while ensuring low transmission delay, thereby increasing the circuit's CMTI (Common Mode Transmission Time Intake).

Claims

1. A low latency level shifting circuit with high CMTI, characterized in that, The application relates to a V / C conversion circuit (1) connected with a C / V conversion circuit (2), a short-time pulse generation circuit (7), a clamping circuit (3), a CLK generation circuit (4), a register circuit (5) and a high-frequency transient voltage zero elimination circuit (6), wherein the C / V conversion circuit (2) is connected with the clamping circuit (3), the CLK generation circuit (4), the register circuit (5) and the high-frequency transient voltage zero elimination circuit (6), the short-time pulse generation circuit (7) is connected with the high-frequency transient voltage zero elimination circuit (6), the high-frequency transient voltage zero elimination circuit (6) is connected with the CLK generation circuit (4) and the register circuit (5), and the CLK generation circuit (4) is connected with the register circuit (5). The register circuit (5) comprises an SR flip-flop L1 and an SR flip-flop L2, an input CLK terminal of the SR flip-flop L1 being connected with an output terminal of an inverter I E in the CLK generating circuit (4). The input S end of the SR flip-flop L1 is connected with the output end of the inverter I A in the CLK generating circuit (4), the input end of the inverter I C , the drain of the transistor N5 in the high-frequency transient voltage zeroing circuit (6), and one input end of the NAND gate M3. The input R end of the SR flip-flop L1 is connected with the output end of the inverter I B in the CLK generating circuit (4), the input end of the inverter I D , the drain of the transistor N4 in the high-frequency transient voltage zeroing circuit (6), and the other input end of the NAND gate M3. The output Q end of the SR flip-flop L1 is connected with the input S end of the SR flip-flop L2, and the output Q end of the SR flip-flop L1 is connected with the input R end of the SR flip-flop L2. The output Q end of the SR flip-flop L1 is connected with the input S end of the SR flip-flop L2, and the output Q end of the SR flip-flop L1 is connected with the input R end of the The input CLK terminal of the SR flip-flop L2 is connected to the output terminal of the NAND gate M3 in the CLK generation circuit (4); the output of the SR flip-flop L2... The terminal is the output signal OUT; The high-frequency transient voltage zeroing circuit (6) comprises a transistor N 3H , a transistor P 3H , a clamping diode D1, an AND gate M1, an AND gate M2, a transistor N3, a transistor N4, a transistor N5, and a transistor P3 and a transistor P4, a gate of the transistor N 3H is connected with an output end of a short-time pulse generating circuit (7), a source of the transistor N 3H is grounded, and a drain of the transistor N 3H is connected with a drain of the transistor P 3H . The gate of the transistor P 3H is connected to the floating ground of the high voltage domain V SSH The source of the transistor P 3H is connected to the drain of the transistor P3, the gate of the transistor P3, the gate of the transistor P4, and the output of the clamping diode D1. An input terminal of the clamp diode D1 is connected to a floating ground of a high voltage domain V SSH Connection; source of the transistor P3 to a high voltage domain supply voltage V DDH connect The source of the transistor P4 is connected to the power supply voltage of the high voltage domain V DDH The drain of the transistor P4 is connected to the gate of the transistor N3, the drain of the transistor N3, one input of the AND gate Ml, one input of the AND gate M2, the other input of the AND gate M2 being connected to the output signal OUT. a source of the transistor N3 to a floating ground of a high voltage domain V SSH connect The output end of the AND gate M1 is connected with the gate of a transistor N5, the source of the transistor N5 is connected with the floating ground of the high voltage domain V SSH Connection; The output end of the AND gate M2 is connected with the gate of a transistor N4, the source of the transistor N4 is connected with the floating ground of the high voltage domain V SSH Connection.

2. The high CMTI low latency level shifting circuit of claim 1, wherein, The V / C conversion circuit (1) comprises a transistor N 1H , a transistor N 2H and an inverter I O , a gate of the transistor N 1H is connected with an input signal V IN , a source of the transistor N 1H is grounded, and a drain of the N 1H is connected with a drain of a transistor P 1H in a C / V conversion circuit (2). The gate of the transistor N 2H is connected to the output of the inverter I O , the source of the transistor N 2H is connected to ground, and the drain of the transistor N 2H is connected to the drain of the transistor P 2H in the C / V conversion circuit (2). The input of the inverter I O is connected to the input signal V IN .

3. The high CMTI low latency level shifting circuit of claim 2, wherein, The C / V conversion circuit (2) includes transistor P 1H and transistor P 2H The transistor P 1H The gate and the floating ground of the high voltage domain V SSH Connection, the transistor P 1H The drain of the transistor N in the V / C conversion circuit (1) 1H The drain connection of the transistor P 1H The source and clamping circuit (3) contains the drain of transistor P1, the drain of transistor N1, and the inverter I in the CLK generation circuit (4). A The input terminal is connected; the gate of the transistor P 2H is connected to the floating ground of the high voltage domain V SSH , the drain of the transistor P 2H is connected to the drain of the transistor N 2H in the V / C conversion circuit (1), the source of the transistor P 2H is connected to the drain of the transistor P2 and the drain of the transistor N2 in the clamping circuit (3) and to the input of the inverter I B in the CLK generation circuit (4).

4. The high CMTI low latency level shifting circuit of claim 3, wherein, The clamping circuit (3) comprises a transistor N1, a transistor N2, a transistor P1 and a transistor P2, the gate of the transistor N1 is connected with the gate of the transistor P1 and the output end of the inverter I D of the CLK generating circuit (4), the source of the transistor N1 is connected with the floating ground of the high voltage domain V SSH ; The gate of transistor N2 is connected to the gate of transistor P2 and the inverter I in the CLK generation circuit (4). C The output terminal is connected, and the source of transistor N2 is connected to the floating ground of the high-voltage domain. V SSH connect; source of the transistor P1, source of the transistor P2 and power supply voltage of the high voltage domain V DDH Connection.

5. The high CMTI low latency level shifting circuit of claim 1, wherein, The CLK generating circuit (4) comprises a NAND gate M3, the input ends of which are connected with the input R end and the input S end of the SR flip-flop L1 in the register circuit (5) respectively, the output end of which is connected with the input end of an inverter I E and the input CLK end of the SR flip-flop L2 in the register circuit (5) respectively, the output end of the inverter I E and the input CLK end of the SR flip-flop L1 in the register circuit (5) respectively. The CLK generating circuit (4) further comprises an inverter I A , an inverter I B , an inverter I C , an inverter I D , and an inverter I E .

6. The high CMTI low latency level shifting circuit of claim 5, wherein, The output of the inverter I C is connected to the gate of the transistor N2 and to the gate of the transistor P2 in the clamping circuit (3).

7. The high CMTI low latency level shifting circuit of claim 6, wherein, The output of the inverter I D is connected to the gate of the transistor N1 and to the gate of the transistor P1 in the clamping circuit (3).

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