High-speed level shift circuit and high-voltage half-bridge driver

Abstract

The invention relates to the technical field of level shift, and discloses a high-speed level shift circuit and a high-voltage half-bridge driver, and the level shift circuit comprises a control signal generation unit, a first pull-down unit, a second pull-down unit, a first signal conversion unit, a second signal conversion unit and an RS trigger. The first signal conversion unit and the second signal conversion unit comprise signal output ends; in actual use, the whole circuit is of a symmetrical structure, and good transmission delay matching can be achieved; in addition, for the first pull-down unit and the second pull-down unit, whether the corresponding pull-down units are conducted or not can be controlled by arranging pull-down switch tubes, and the grid voltage of MOS tubes in the pull-down current mirrors can be always very high by arranging the positions of the pull-down switch tubes and the pull-down current mirrors. And the gate-source voltage of the MOS tube in the pull-down current mirror can be quickly improved, so that the transmission delay of the level shift circuit can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of level shifting, and in particular to a high-speed level shifting circuit and a high-voltage half-bridge driver. Background Art

[0002] In modern electronic devices, integrated high-side and low-side power switches are usually implemented with parallel thin-gate oxide high-voltage transistors that can withstand high drain-source voltages up to the input supply and low gate-source voltages below 6V.

[0003] For the gate drivers of integrated high-side and low-side power switches, the level shift circuit is an essential key module as a bridge between the low-voltage logic control signal and the high-voltage gate drive signal, while keeping the signal swing within the safe range of the thin gate oxide switch; the main performance indicators of the level shift circuit are transmission delay, power consumption and noise immunity.

[0004] An existing technical solution published in IEEE Transactions on Power Electronics, titled "A High-Voltage DC-DC Buck Converter With Dynamic Level Shifter for Bootstrapped High-Side Gate Driver and Diode Emulator" is as follows Figure 1 shown.

[0005] for Figure 1 In the circuit shown in the figure, when it is actually used, as the input voltage VSH increases, the presence of parasitic capacitance in the circuit will cause a large transmission delay on the rising edge. Figure 1 The circuit shown has a large mismatch in propagation delays. Summary of the invention

[0006] In view of the shortcomings of the background technology, the present invention provides a high-speed level shift circuit and a high-voltage half-bridge driver. The technical problem to be solved is that the transmission delay of the rising edge of the existing level shift circuit is large and the transmission delay has a large mismatch.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: a high-speed level shift circuit, comprising a control signal generating unit, a first pull-down unit, a second pull-down unit, a first signal conversion unit, a second signal conversion unit and an RS trigger; the first signal conversion unit and the second signal conversion unit include a signal output terminal;

[0008] The control signal generating unit generates a first control signal and a second control signal based on an input signal VIN, wherein the first control signal is the same as the input signal VIN, and the second control signal is opposite to the input signal VIN;

[0009] The first pull-down unit and the second pull-down unit respectively include a pull-down switch tube, a pull-down current mirror, a pull-down resistor and a pull-down high-voltage transistor; the output end of the pull-down switch tube is grounded, the first control signal is input to the control end of the pull-down switch tube of the first pull-down unit to control the on-off of the pull-down switch tube of the first pull-down unit, and the second control signal is input to the control end of the pull-down switch tube of the second pull-down unit to control the on-off of the pull-down switch tube of the second pull-down unit; the input end of the pull-down switch tube is electrically connected to the output end of the main current mirror branch of the pull-down current mirror and the output end of the slave current mirror branch of the pull-down current mirror, the input end of the main current mirror branch of the pull-down current mirror is electrically connected to the output end of the pull-down high-voltage transistor, the input end of the slave current mirror of the pull-down current mirror is electrically connected to the control end of the pull-down high-voltage transistor through the pull-down resistor, and the control end of the pull-down high-voltage transistor is used to input a signal VDDL;

[0010] The first signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the first pull-down unit, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the second signal conversion unit when the pull-down switch tube of the first pull-down unit is turned on;

[0011] The second signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the second pull-down unit, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the first signal conversion unit when the pull-down switch tube of the second pull-down unit is turned on;

[0012] The R input terminal of the RS trigger is electrically connected to the signal output terminal of the first signal conversion unit, and the S input terminal of the RS trigger is electrically connected to the signal output terminal of the second signal conversion unit.

[0013] In a certain embodiment, the control signal generating unit includes an inverter INV1, an inverter INV2 and an inverter INV3; the input end of the inverter INV1 is electrically connected to the input end of the inverter INV3, and is used to input the input signal VIN, the output end of the inverter INV1 is electrically connected to the input end of the inverter INV2, the output end of the inverter INV2 is used to output the first control signal, and the output end of the inverter INV3 is used to output the second control signal.

[0014] In a certain embodiment, the pull-down current mirror includes a MOS tube M2 and a MOS tube M1, the source of the MOS tube M2 is the output end of the main current mirror branch of the pull-down current mirror, the source of the MOS tube M1 is the output end of the slave current mirror branch of the pull-down current mirror, the drain of the MOS tube M1 is electrically connected to the gate of the MOS tube M1 and the gate of the MOS tube M2, respectively, and is the input end of the slave current mirror branch of the pull-down current mirror, and the drain of the MOS tube M2 is the input end of the main current mirror branch of the pull-down current mirror.

[0015] In a certain embodiment, the first pull-down unit and the second pull-down unit further include a pull-down clamping transistor, respectively, the input end of the pull-down clamping transistor is electrically connected to the control end of the pull-down high-voltage transistor, and the output end of the pull-down high-voltage transistor is electrically connected to the control end of the pull-down clamping transistor and the output end of the pull-down clamping transistor, respectively.

[0016] In a certain embodiment, the first signal conversion unit and the second signal conversion unit both include a first current mirror, a second current mirror, a third current mirror and a conversion switch tube; for one of the first signal conversion unit and the second signal conversion unit, the slave current mirror branch of the first current mirror is electrically connected to the input end of the corresponding pull-down high-voltage transistor, the main current mirror branch of the first current mirror is electrically connected to the slave current mirror branch of the second current mirror and the control end of its own conversion switch tube, respectively, the main current mirror branch of the second current mirror is electrically connected to the slave current mirror branch of the third current mirror, the main branch of the third current mirror is electrically connected to the input end of the conversion switch tube of another signal conversion unit, and the output end of the conversion switch tube is used to access the voltage VS.

[0017] In a certain implementation manner, the main current mirror branch of the first current mirror includes a MOS tube M8, and the slave current mirror branch of the first current mirror includes a MOS tube M7; the main current mirror branch of the second current mirror includes a MOS tube M10, and the slave current mirror branch of the second current mirror includes a MOS tube M9; the main current mirror branch of the third current mirror includes a MOS tube M17, and the slave current mirror branch of the third current mirror includes a MOS tube M11;

[0018] The source of the MOS tube M17 is electrically connected to the source of the MOS tube M8, the source of the MOS tube M11 and the source of the MOS tube M17 respectively, and is used to access the voltage VBST; the gate of the MOS tube M7 is electrically connected to the drain of the MOS tube M7, the input end of the corresponding pull-down high-voltage transistor and the gate of the MOS tube M8 respectively, the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9, the gate of the MOS tube M9, the gate of the MOS tube M10 and the control end of its own conversion switch tube respectively, the source of the MOS tube M9 and the source of the MOS tube M10 are used to access the voltage VS; the drain of the MOS tube M10 is electrically connected to the drain of the MOS tube M11, the gate of the MOS tube M11 and the gate of the MOS tube M17 respectively, the drain of the MOS tube M17 is the signal output end of its own signal conversion unit, and is electrically connected to the input end of the conversion switch tube of another signal conversion unit.

[0019] In a certain embodiment, the present invention also includes a MOS tube M21, a MOS tube M22, a MOS tube M23 and a MOS tube M24, the source of the MOS tube M21 and the source of the MOS tube M23 are used for input voltage VBST, the gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M24, the drain of the MOS tube M24 and the input end of the pull-down high-voltage transistor of the second pull-down unit, the gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M22, the drain of the MOS tube M22 and the input end of the pull-down high-voltage transistor of the first pull-down unit, the drain of the MOS tube M21 is electrically connected to the source of the MOS tube M22, and the drain of the MOS tube M23 is electrically connected to the source of the MOS tube M24.

[0020] In a certain embodiment, the first signal conversion unit and the second signal conversion unit further include a conversion clamping transistor, respectively, the input end of the conversion clamping transistor is electrically connected to the gate of the MOS tube M7 of the first current mirror, and the control end and the output end of the conversion clamping transistor are both used for the input voltage VS.

[0021] In some implementations, the signal output end of the first signal conversion unit and the signal output end of the second signal conversion unit are electrically connected to the RS trigger via a common mode noise suppression unit.

[0022] In a certain embodiment, the common-mode noise suppression unit includes an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; the input end of the inverter INV4 is electrically connected to the signal output end of the first signal conversion unit and the first input end of the AND gate AND2, respectively, and the output end of the inverter INV4 is electrically connected to the first input end of the AND gate AND1; the input end of the inverter INV5 is electrically connected to the signal output end of the second signal conversion unit and the second input end of the AND gate AND1, respectively, and the output end of the inverter INV5 is electrically connected to the second input end of the AND gate AND2; the output end of the AND gate AND1 is electrically connected to the R input end of the RS trigger, and the output end of the AND gate AND2 is electrically connected to the S input end of the RS trigger.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] First, the circuit of the present invention has a symmetrical structure as a whole, which can achieve good transmission delay matching;

[0025] Secondly, for the first pull-down unit and the second pull-down unit of the present invention, by setting the pull-down switch tube, it is possible to control whether the corresponding pull-down unit is turned on, and by setting the position of the pull-down switch tube and the pull-down current mirror, the gate voltage of the MOS tube in the pull-down current mirror can be always high, which helps to quickly increase the gate-source voltage of the MOS tube in the pull-down current mirror, thereby significantly reducing the transmission delay of the level shift circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a circuit diagram of an existing level shift circuit;

[0027] Figure 2 is a circuit diagram of a level shift circuit of the present invention in Embodiment 1;

[0028] Figure 3 FIG. 1 is a schematic diagram of the structure of a high-voltage half-bridge driver of the present invention in Embodiment 2. DETAILED DESCRIPTION

[0029] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0030] like Figure 2 As shown, a high-speed level shift circuit includes a control signal generating unit 1, a first pull-down unit 2, a second pull-down unit 3, a first signal conversion unit 4, a second signal conversion unit 5 and an RS trigger 6; the first signal conversion unit 4 and the second signal conversion unit 5 include a signal output terminal;

[0031] The control signal generating unit 1 generates a first control signal CON1 and a second control signal CON2 based on an input signal VIN, wherein the first control signal CON1 is the same as the input signal VIN, and the second control signal CON2 is opposite to the input signal VIN;

[0032] In this embodiment, the circuits of the first pull-down unit 2 and the second pull-down unit 3 are the same. Taking the first pull-down unit 2 as an example, they respectively include a pull-down switch tube M5, a pull-down current mirror 20, a pull-down resistor R1 and a pull-down high-voltage transistor MHV1; the output end of the pull-down switch tube M5 is grounded, the first control signal CON1 is input to the control end of the pull-down switch tube M5 of the first pull-down unit 2 to control the on-off of the pull-down switch tube M5 of the first pull-down unit 2, and the second control signal CON2 is input to the control end of the pull-down switch tube M6 of the second pull-down unit 3 to control the on-off of the pull-down switch tube M6 of the second pull-down unit 3;

[0033] Continuing to take the first pull-down unit 2 as an example, the input end of the pull-down switch tube M5 is electrically connected to the output end of the main current mirror branch of the pull-down current mirror 20 and the output end of the slave current mirror branch of the pull-down current mirror, respectively, the input end of the main current mirror branch of the pull-down current mirror is electrically connected to the output end of the pull-down high-voltage transistor MHV1, the input end of the slave current mirror of the pull-down current mirror is electrically connected to the control end of the pull-down high-voltage transistor MHV1 through the pull-down resistor R1, and the control end of the pull-down high-voltage transistor MHV1 is used to input the signal VDDL;

[0034] The first signal conversion unit 4 is electrically connected to the input end of the pull-down high-voltage transistor MHV1 of the first pull-down unit 2, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the second signal conversion unit 5 when the pull-down switch tube M5 of the first pull-down unit 2 is turned on;

[0035] The second signal conversion unit 5 is electrically connected to the input end of the pull-down high-voltage transistor MHV2 of the second pull-down unit 3, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the first signal conversion unit 4 when the pull-down switch tube M6 of the second pull-down unit 3 is turned on;

[0036] The R input terminal of the RS flip-flop 6 is electrically connected to the signal output terminal of the first signal conversion unit, and the S input terminal of the RS flip-flop is electrically connected to the signal output terminal of the second signal conversion unit.

[0037] Specifically, in this embodiment, Figure 2As shown, the control signal generating unit 1 includes an inverter INV1, an inverter INV2 and an inverter INV3; the input end of the inverter INV1 is electrically connected to the input end of the inverter INV3 for inputting the input signal VIN, the output end of the inverter INV1 is electrically connected to the input end of the inverter INV2, the output end of the inverter INV2 is used to output the first control signal CON1, and the output end of the inverter INV3 is used to output the second control signal CON2.

[0038] In addition, Figure 1 In the figure, taking the first pull-down unit 2 as an example, the pull-down current mirror 20 of the first pull-down unit 2 includes a MOS tube M2 and a MOS tube M1, the source of the MOS tube M2 is the output end of the main current mirror branch of the pull-down current mirror, the source of the MOS tube M1 is the output end of the slave current mirror branch of the pull-down current mirror, the drain of the MOS tube M1 is electrically connected to the gate of the MOS tube M1 and the gate of the MOS tube M2, respectively, and is the input end of the slave current mirror branch of the pull-down current mirror, and the drain of the MOS tube M2 is the input end of the main current mirror branch of the pull-down current mirror.

[0039] exist Figure 1 In the figure, the pull-down high-voltage transistor MHV1, MOS tube M1, MOS tube M2 and MOS tube M5 are all NMOS tubes. For the NMOS tube, the gate of the NMOS tube is its own control terminal, the source of the NMOS tube is its own output terminal, and the drain of the NMOS tube is its own input terminal.

[0040] In actual use, firstly, the circuit of the present invention has a symmetrical structure as a whole, which can achieve good transmission delay matching;

[0041] Secondly, for the first pull-down unit 2 and the second pull-down unit 3 of the present invention, by setting the pull-down switch tube, it is possible to control whether the corresponding pull-down unit is turned on, and by setting the position of the pull-down switch tube and the pull-down current mirror, the gate voltage of the MOS tube in the pull-down current mirror can be always high, which helps to quickly increase the gate-source voltage of the MOS tube in the pull-down current mirror, thereby significantly reducing the transmission delay of the level shift circuit.

[0042] In addition, in this embodiment, Figure 2 As shown, the first pull-down unit 2 and the second pull-down unit 3 further include pull-down clamp transistors, respectively. Taking the first pull-down unit 2 as an example, the input end of the pull-down clamp transistor MQ1 of the first pull-down unit 2 is electrically connected to the control end of the pull-down high-voltage transistor MHV1, and the output end of the pull-down high-voltage transistor MHV1 is electrically connected to the control end of the pull-down clamp transistor MQ1 and the output end of the pull-down clamp transistor MQ1, respectively. Among them, the pull-down clamp transistor MQ1 is also an NMOS tube.

[0043] Taking the first pull-down unit 2 as an example, in actual use, the gate-source voltage of the pull-down high-voltage transistor MHV1 can be clamped by the pull-down clamping transistor MQ1 to prevent the pull-down high-voltage transistor MHV1 from being broken down.

[0044] In this embodiment, the circuits of the first signal conversion unit 4 and the second signal conversion unit 5 are the same and both include a first current mirror, a second current mirror, a third current mirror and a conversion switch tube; for the first signal conversion unit 4 in the first signal conversion unit 4 and the second signal conversion unit 5, the slave current mirror branch of the first current mirror 40 is electrically connected to the input end of the corresponding pull-down high-voltage transistor MHV1, the main current mirror branch of the first current mirror 40 is electrically connected to the slave current mirror branch of the second current mirror 41 and the control end of its own conversion switch tube M18, respectively, the main current mirror branch of the second current mirror 41 is electrically connected to the slave current mirror branch of the third current mirror 42, the main branch of the third current mirror 42 is electrically connected to the input end of the conversion switch tube M20 of the second signal conversion unit 5, and the output end of the conversion switch tube M18 is used to access the voltage VS.

[0045] More specifically, in Figure 2 In the embodiment, taking the first signal conversion unit 4 as an example, the main current mirror branch of the first current mirror 40 includes a MOS tube M8, and the slave current mirror branch of the first current mirror 40 includes a MOS tube M7; the main current mirror branch of the second current mirror 41 includes a MOS tube M10, and the slave current mirror branch of the second current mirror 41 includes a MOS tube M9; the main current mirror branch of the third current mirror 42 includes a MOS tube M17, and the slave current mirror branch of the third current mirror 42 includes a MOS tube M11;

[0046] The source of the MOS tube M17 is electrically connected to the source of the MOS tube M8, the source of the MOS tube M11 and the source of the MOS tube M17 respectively, and is used to access the voltage VBST; the gate of the MOS tube M7 is electrically connected to the drain of the MOS tube M7, the input end of the corresponding pull-down high-voltage transistor MHV1 and the gate of the MOS tube M8 respectively, the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9, the gate of the MOS tube M9, the gate of the MOS tube M10 and the control end of its own conversion switch tube M18 respectively, the source of the MOS tube M9 and the source of the MOS tube M10 are used to access the voltage VS; the drain of the MOS tube M10 is electrically connected to the drain of the MOS tube M11, the gate of the MOS tube M11 and the gate of the MOS tube M17 respectively, the drain of the MOS tube M17 is the signal output end N1 of its own signal conversion unit, and is electrically connected to the input end of the conversion switch tube M20 of the second signal conversion unit 5.

[0047] It should be noted that, in order to distinguish, the names of the MOS transistors in the second signal conversion unit 5 are marked differently. In addition, the conversion switch transistor M18 is also an NMOS transistor.

[0048] In addition, in this embodiment, Figure 2 As shown, the present invention also includes a MOS tube M21, a MOS tube M22, a MOS tube M23 and a MOS tube M24. The source of the MOS tube M21 and the source of the MOS tube M23 are used for inputting the voltage VBST. The gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M24, the drain of the MOS tube M24 and the input end of the pull-down high-voltage transistor MHV2 of the second pull-down unit 3, respectively. The gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M22, the drain of the MOS tube M22 and the input end of the pull-down high-voltage transistor MHV1 of the first pull-down unit 2, respectively. The drain of the MOS tube M21 is electrically connected to the source of the MOS tube M22, and the drain of the MOS tube M23 is electrically connected to the source of the MOS tube M24.

[0049] In addition, in this embodiment, MOS tube M21, MOS tube M22, MOS tube M23 and MOS tube M24 are all PMOS tubes. For the PMOS tube, the source of the PMOS tube is its own input terminal, the gate of the PMOS tube is its own control terminal, and the drain of the PMOS tube is its own output terminal.

[0050] For the present invention Figure 2 In the circuit shown, when there are no MOS tubes M21, M22, M23 and M24, ideally, the voltage at the node A2 rises synchronously with the voltage VBST. However, in fact, due to the effect of the parasitic capacitance at the node A2, the voltage rise at the node A2 lags behind the rise of the voltage VBST, which will produce a large voltage drop, which will cause the MOS tube M12 to turn on, and then the MOS tube M19 and the MOS tube M20 to turn on through the current mirror image; and the turning on of the MOS tube M19 will increase the voltage of the node N2, and the turning on of the MOS tube M20 will reduce the voltage of the node N1, which will eventually cause the output VOUT of the level shift circuit to become a low level, causing the high-side power tube of the half-bridge circuit to be mistakenly shut down; the working process of the node A1 changes in the same way, which will not be described here.

[0051] After the MOS tube M21, MOS tube M22, MOS tube M23 and MOS tube M24 are arranged, in actual use, the MOS tube M21, MOS tube M22, MOS tube M23 and MOS tube M24 constitute two dynamic branches. When the voltage VS changes, the dynamic branch generates a transient current, which can help stabilize the voltage of the node A1 and the node A2 by providing a transient current path that responds quickly to the change in the voltage VS. By stabilizing the voltage of the node A1 and the node A2, the high-side power tube of the half-bridge circuit can be prevented from being accidentally shut down.

[0052] Specifically, in this embodiment, Figure 2As shown, the first signal conversion unit 4 and the second signal conversion unit 5 further include conversion clamp transistors, respectively. Taking the first signal conversion unit 4 as an example, the input end of the conversion clamp transistor MQ3 is electrically connected to the gate of the MOS tube M7 of the first current mirror 40, and the control end and the output end of the conversion clamp transistor MQ3 are both used for the input voltage VS.

[0053] In actual use, the voltage of the node A1 can be clamped by switching the clamp transistor MQ3, thereby protecting the low-voltage device connected to the node A1.

[0054] In addition, for the level shift circuit, if its noise suppression capability is weak, it will directly affect the reliability of signal transmission, causing the circuit to malfunction. Based on this, in this embodiment, the signal output terminal N1 of the first signal conversion unit 4 and the signal output terminal N2 of the second signal conversion unit 5 are electrically connected to the RS trigger 6 through the common mode noise suppression unit 7.

[0055] exist Figure 2 In the embodiment, the common-mode noise suppression unit 7 includes an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; the input end of the inverter INV4 is electrically connected to the signal output end N1 of the first signal conversion unit 4 and the first input end of the AND gate AND2, respectively, and the output end of the inverter INV4 is electrically connected to the first input end of the AND gate AND1; the input end of the inverter INV5 is electrically connected to the signal output end N2 of the second signal conversion unit 5 and the second input end of the AND gate AND1, respectively, and the output end of the inverter INV5 is electrically connected to the second input end of the AND gate AND2; the output end of the AND gate AND1 is electrically connected to the R input end of the RS trigger, and the output end of the AND gate AND2 is electrically connected to the S input end of the RS trigger.

[0056] In the actual signal transmission process, the logic states of the signal output terminal N1 of the first signal conversion unit 4 and the signal output terminal N2 of the second signal conversion unit 5 are opposite, and the logic states of the signal output terminal N1 and the signal output terminal N2 are quickly transmitted to the RS output device through the common mode noise suppression unit 7, thereby changing the output logic state, wherein the truth table of the common mode noise suppression unit 7 is shown in Table 1:

[0057] Table 1

[0058] <![CDATA[N1]]> <![CDATA[N2]]> R S <![CDATA[V OUT ]]> 0 1 1 0 0 1 0 0 1 1 1 1 0 0 hold 0 0 0 0 hold

[0059] It can be seen from Table 1 that during the rapid voltage conversion, even if the logic states of the signal output terminal N1 and the signal output terminal N2 are the same and switch between 0 and 1, the logic states of the nodes R and S always remain at 0, and the output does not change, always maintaining the logic state before the voltage conversion. Therefore, the common-mode noise suppression unit significantly improves noise immunity without increasing the circuit delay too much.

[0060] Embodiment 2

[0061] like Figure 3 As shown, this embodiment provides a high-voltage half-bridge driver, including a driving chip 8, the driving chip 8 includes a logic and dead time control unit, a delay matching unit, a high-voltage driving unit, a low-voltage driving unit, a high-voltage switch tube MH and a low-voltage switch tube ML, the driving chip 8 is provided with a VDDL pin, a VBST pin, a VBUS pin, a VS pin, a GND pin, an INH pin and an INL pin, and the driving chip 8 is also provided with the level shift circuit in the first embodiment;

[0062] Pin INH and pin INL are electrically connected to the logic and dead time control unit, respectively, for inputting high-voltage control signals and low-voltage control signals to the logic and dead time control unit; the VDDL pin is electrically connected to the logic and dead time control unit, the level shift circuit, the delay matching unit and the low-voltage drive circuit, respectively, for inputting the signal VDDL, and the VBST pin is electrically connected to the level shift circuit and the high-voltage drive unit, respectively, for inputting the voltage VBST; the logic and dead time control unit is electrically connected to the level shift circuit and the delay matching unit, respectively, the level shift circuit is electrically connected to the high-voltage drive unit, the delay matching unit is electrically connected to the low-voltage matching unit, the high-voltage drive unit is electrically connected to the control end of the high-voltage switch tube MH, the low-voltage drive unit is electrically connected to the control end of the low-voltage switch tube ML, the output end of the high-voltage switch tube MH and the input end of the low-voltage switch tube ML are electrically connected to the VS pin, respectively, the output end of the low-voltage switch tube ML is electrically connected to the GND pin, and the input end of the high-voltage switch tube MH is electrically connected to the VBUS pin;

[0063] The VS pin is also electrically connected to one end of the inductor L10 and one end of the capacitor C10 respectively. The other end of the inductor L10 is also electrically connected to the GND pin through the capacitor C11 and the resistor R10 respectively. The other end of the capacitor C10 is electrically connected to the VBST pin and the cathode of the diode D10 respectively. The anode of the diode D10 is electrically connected to the VDDL pin.

[0064] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A high-speed level shift circuit, characterized in that: It includes a control signal generating unit, a first pull-down unit, a second pull-down unit, a first signal converting unit, a second signal converting unit and an RS trigger; the first signal converting unit and the second signal converting unit include a signal output terminal; The control signal generating unit generates a first control signal and a second control signal based on an input signal VIN, wherein the first control signal is the same as the input signal VIN, and the second control signal is opposite to the input signal VIN; The first pull-down unit and the second pull-down unit respectively include a pull-down switch tube, a pull-down current mirror, a pull-down resistor and a pull-down high-voltage transistor; the output end of the pull-down switch tube is grounded, the first control signal is input to the control end of the pull-down switch tube of the first pull-down unit to control the on-off of the pull-down switch tube of the first pull-down unit, and the second control signal is input to the control end of the pull-down switch tube of the second pull-down unit to control the on-off of the pull-down switch tube of the second pull-down unit; the input end of the pull-down switch tube is electrically connected to the output end of the main current mirror branch of the pull-down current mirror and the output end of the slave current mirror branch of the pull-down current mirror, the input end of the main current mirror branch of the pull-down current mirror is electrically connected to the output end of the pull-down high-voltage transistor, the input end of the slave current mirror of the pull-down current mirror is electrically connected to the control end of the pull-down high-voltage transistor through the pull-down resistor, and the control end of the pull-down high-voltage transistor is used to input a signal VDDL; The first signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the first pull-down unit, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the second signal conversion unit when the pull-down switch tube of the first pull-down unit is turned on; The second signal conversion unit is electrically connected to the input end of the pull-down high-voltage transistor of the second pull-down unit, and is used to pull up the output of its own signal output end and pull down the output of the signal output end of the first signal conversion unit when the pull-down switch tube of the second pull-down unit is turned on; The R input terminal of the RS trigger is electrically connected to the signal output terminal of the first signal conversion unit, and the S input terminal of the RS trigger is electrically connected to the signal output terminal of the second signal conversion unit.

2. A high-speed level shift circuit according to claim 1, characterized in that: The control signal generating unit includes an inverter INV1, an inverter INV2 and an inverter INV3; the input end of the inverter INV1 is electrically connected to the input end of the inverter INV3, and is used to input the input signal VIN; the output end of the inverter INV1 is electrically connected to the input end of the inverter INV2; the output end of the inverter INV2 is used to output the first control signal; and the output end of the inverter INV3 is used to output the second control signal.

3. A high-speed level shift circuit according to claim 1, characterized in that: The pull-down current mirror comprises a MOS tube M2 and a MOS tube M1, wherein the source of the MOS tube M2 is the output end of the main current mirror branch of the pull-down current mirror, the source of the MOS tube M1 is the output end of the slave current mirror branch of the pull-down current mirror, the drain of the MOS tube M1 is electrically connected to the gate of the MOS tube M1 and the gate of the MOS tube M2 respectively, and is the input end of the slave current mirror branch of the pull-down current mirror, and the drain of the MOS tube M2 is the input end of the main current mirror branch of the pull-down current mirror.

4. A high-speed level shift circuit according to claim 3, characterized in that: The first pull-down unit and the second pull-down unit further include a pull-down clamping transistor, respectively, the input end of the pull-down clamping transistor is electrically connected to the control end of the pull-down high-voltage transistor, and the output end of the pull-down high-voltage transistor is electrically connected to the control end of the pull-down clamping transistor and the output end of the pull-down clamping transistor, respectively.

5. The high-speed level shift circuit according to claim 1, characterized in that: The first signal conversion unit and the second signal conversion unit both include a first current mirror, a second current mirror, a third current mirror and a conversion switch tube; for one of the first signal conversion unit and the second signal conversion unit, the slave current mirror branch of the first current mirror is electrically connected to the input end of the corresponding pull-down high-voltage transistor, the main current mirror branch of the first current mirror is electrically connected to the slave current mirror branch of the second current mirror and the control end of its own conversion switch tube, respectively, the main current mirror branch of the second current mirror is electrically connected to the slave current mirror branch of the third current mirror, the main branch of the third current mirror is electrically connected to the input end of the conversion switch tube of another signal conversion unit, and the output end of the conversion switch tube is used to access the voltage VS.

6. A high-speed level shift circuit according to claim 5, characterized in that: The main current mirror branch of the first current mirror includes a MOS tube M8, and the slave current mirror branch of the first current mirror includes a MOS tube M7; the main current mirror branch of the second current mirror includes a MOS tube M10, and the slave current mirror branch of the second current mirror includes a MOS tube M9; the main current mirror branch of the third current mirror includes a MOS tube M17, and the slave current mirror branch of the third current mirror includes a MOS tube M11; The source of the MOS tube M17 is electrically connected to the source of the MOS tube M8, the source of the MOS tube M11 and the source of the MOS tube M17 respectively, and is used to access the voltage VBST; the gate of the MOS tube M7 is electrically connected to the drain of the MOS tube M7, the input end of the corresponding pull-down high-voltage transistor and the gate of the MOS tube M8 respectively, the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9, the gate of the MOS tube M9, the gate of the MOS tube M10 and the control end of its own conversion switch tube respectively, the source of the MOS tube M9 and the source of the MOS tube M10 are used to access the voltage VS; the drain of the MOS tube M10 is electrically connected to the drain of the MOS tube M11, the gate of the MOS tube M11 and the gate of the MOS tube M17 respectively, the drain of the MOS tube M17 is the signal output end of its own signal conversion unit, and is electrically connected to the input end of the conversion switch tube of another signal conversion unit.

7. A high-speed level shift circuit according to claim 6, characterized in that: It also includes a MOS tube M21, a MOS tube M22, a MOS tube M23 and a MOS tube M24. The source of the MOS tube M21 and the source of the MOS tube M23 are used for inputting a voltage VBST. The gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M24, the drain of the MOS tube M24 and the input end of the pull-down high-voltage transistor of the second pull-down unit, respectively. The gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M22, the drain of the MOS tube M22 and the input end of the pull-down high-voltage transistor of the first pull-down unit, respectively. The drain of the MOS tube M21 is electrically connected to the source of the MOS tube M22, and the drain of the MOS tube M23 is electrically connected to the source of the MOS tube M24.

8. A high-speed level shift circuit according to claim 7, characterized in that: The first signal conversion unit and the second signal conversion unit further include a conversion clamp transistor respectively, the input end of the conversion clamp transistor is electrically connected to the gate of the MOS tube M7 of the first current mirror, and the control end and output end of the conversion clamp transistor are both used for input voltage VS.

9. A high-speed level shift circuit according to any one of claims 1 to 8, characterized in that: The signal output end of the first signal conversion unit and the signal output end of the second signal conversion unit are electrically connected to the RS trigger through the common mode noise suppression unit; The common-mode noise suppression unit includes an inverter INV4, an inverter INV5, an AND gate AND1 and an AND gate AND2; the input end of the inverter INV4 is electrically connected to the signal output end of the first signal conversion unit and the first input end of the AND gate AND2, respectively, and the output end of the inverter INV4 is electrically connected to the first input end of the AND gate AND1; the input end of the inverter INV5 is electrically connected to the signal output end of the second signal conversion unit and the second input end of the AND gate AND1, respectively, and the output end of the inverter INV5 is electrically connected to the second input end of the AND gate AND2; the output end of the AND gate AND1 is electrically connected to the R input end of the RS trigger, and the output end of the AND gate AND2 is electrically connected to the S input end of the RS trigger.

10. A high-voltage half-bridge driver, comprising a driver chip, the driver chip comprising a logic and dead time control unit, a delay matching unit, a high-voltage drive unit, a low-voltage drive unit, a high-voltage switch tube and a low-voltage switch tube, the driver chip is provided with a VDDL pin, a VBST pin, a VBUS pin, a VS pin, a GND pin, an INH pin and an INL pin, characterized in that: The driver chip is also provided with a level shift circuit according to any one of claims 1 to 9; The pin INH and the pin INL are electrically connected to the logic and dead time control unit, respectively, for inputting a high voltage control signal and a low voltage control signal to the logic and dead time control unit; the VDDL pin is electrically connected to the logic and dead time control unit, the level shift circuit, the delay matching unit and the low voltage drive circuit, respectively, for inputting a signal VDDL, and the VBST pin is electrically connected to the level shift circuit and the high voltage drive unit, respectively, for inputting a voltage VBST; the logic and dead time control unit is electrically connected to the level shift circuit and the delay matching unit, respectively, the level shift circuit is electrically connected to the high voltage drive unit, the delay matching unit is electrically connected to the low voltage matching unit, the high voltage drive unit is electrically connected to the control end of the high voltage switch tube, the low voltage drive unit is electrically connected to the control end of the low voltage switch tube, the output end of the high voltage switch tube and the input end of the low voltage switch tube are electrically connected to the VS pin, respectively, the output end of the low voltage switch tube is electrically connected to the GND pin, and the input end of the high voltage switch tube is electrically connected to the VBUS pin; The VS pin is also electrically connected to one end of the inductor L10 and one end of the capacitor C10 respectively. The other end of the inductor L10 is also electrically connected to the GND pin through the capacitor C11 and the resistor R10 respectively. The other end of the capacitor C10 is electrically connected to the VBST pin and the cathode of the diode D10 respectively. The anode of the diode D10 is electrically connected to the VDDL pin.

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