Front-end circuit for data receiver and related systems, methods and devices

Abstract

The present invention discloses a front-end circuit for a data receiver and related systems, methods and devices. The front-end circuit includes a passive equalizer, the passive equalizer including a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits a behavior substantially opposite to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain a balanced output signal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 027,152, filed on May 19, 2020, and entitled “PROGRAMMABLE DATA RECEIVER FRONT ENDS HAVING PASSIVE EQUALIZERS AND RELATED SYSTEMS, METHODS, AND DEVICES,” under 35 U.S.C. §119(e), the entire disclosure of which is hereby incorporated by reference into this document. Technical Field

[0003] The present disclosure relates generally to programmable data receiver front ends, and more particularly to programmable data receivers having passive equalizers and programmable amplifier circuits. Background Art

[0004] As data rates increase, backplane channels in SerDes systems exhibit increased attenuation compared to serializer / deserializer (SerDes) systems using lower data rates, which results in the need for more equalization of the received data signal to prevent inter-symbol interference and eye closure. A typical data channel may have more than twenty to thirty-five decibels (20dB-35dB) of loss at the Nyquist frequency (half the baud rate). The result is "eye closure" at the receiver input. As a result, "zeros" and "ones" may not be distinguishable in the received signal.

[0005] One approach to achieving channel equalization involves a programmable attenuator followed by one or more stages of a continuous time linear equalizer (CTLE) based on a differential pair amplifier with configurable resistor-capacitor (RC) degeneration, or an analog finite impulse response (aFIR) equalizer. However, the inventors of the present disclosure have recognized that active equalizers such as CTLEs require a pre-programmable attenuator that utilizes a switch, which compromises signal integrity. For example, short channels require pre-attenuation to prevent the CTLE from overloading. Additionally, active equalizers have different properties at various equalizer settings, complicating design and system modeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0007] Figure 1 This is the circuit diagram of the Zobel network;

[0008] Figure 2 It is the circuit diagram of the second-order Zobel network;

[0009] Figure 3 is shown in response to the input signal, Figure 2 A frequency response curve diagram of the top voltage potential VTOP and the bottom voltage potential VBOT of the second-order Zobel network;

[0010] Figure 4 is a block diagram of a data receiver according to some embodiments;

[0011] Figure 5 According to some embodiments, Figure 4 A circuit diagram of a passive equalizer of a data receiver;

[0012] Figure 6 According to some embodiments, Figure 4 A circuit diagram of an alternative passive equalizer for a data receiver;

[0013] Figure 7 According to some embodiments, Figure 4 A circuit diagram of a programmable amplifier circuit of a data receiver;

[0014] Figure 8 is shown plotted against frequency from Figure 4 800 is a graph of an example of an equalized signal of a front-end circuit of FIG. 1 , wherein a signal input of the front-end circuit is electrically connected to a relatively short physical channel;

[0015] Fig. 9 is shown plotted against frequency from Figure 4 A graph of an example of an equalized signal of a front-end circuit of FIG. 1 , wherein a signal input of the front-end circuit is electrically connected to a physical channel of medium length;

[0016] Fig.10 is a graph showing examples of a channel input signal curve, a channel output signal curve, and an equalized signal curve;

[0017] Fig.11 Shown with Fig.10 The eye diagram curves corresponding to the channel input signal curve, the channel output signal curve and the equalized signal curve; and

[0018] Fig.12 is a diagram showing the use of some embodiments Figure 4 A flow chart of a method for a front-end circuit to equalize an input signal. DETAILED DESCRIPTION

[0019] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure and in which are shown by way of example specific examples of embodiments in which the present disclosure may be implemented. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments enabled herein may be utilized and structural, material and process changes may be made without departing from the scope of the present disclosure.

[0020] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity of numbering does not necessarily mean that the structures or components are identical in size, composition, construction, or any other attribute.

[0021] The following description may include examples to help those skilled in the art practice the disclosed embodiments of the present invention. The use of the terms "exemplary", "such as" and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the embodiments or the present disclosure to the specified components, steps, features, functions, etc.

[0022] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in many different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of these embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0023] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0024] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For clarity of presentation and description, some figures may show signals as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0025] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general purpose processor (also referred to herein as a "host processor" or simply "host") may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code, but not limited thereto) associated with the embodiments disclosed herein.

[0026] Embodiment can be described according to the process that is depicted as flow chart, flow diagram, structure diagram or block diagram.Although flow chart can describe operation action as continuous process, many actions in these actions can be performed in accordance with another sequence, in parallel or substantially simultaneously.In addition, the order of action can be rearranged.The process herein can correspond to method, thread, function, process (procedure), subroutine, subprogram, other structure or their combination.In addition, the method disclosed herein can be implemented by hardware, software or both.If realized in software, these functions can be stored or transmitted to computer-readable medium as one or more instructions or codes.Computer-readable medium includes both computer storage medium and communication medium, and this communication medium includes any medium that is conducive to transferring computer program from one position to another position.

[0027] Any reference to an element herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0028] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition means and includes to the extent that one of ordinary skill in the art would understand that the given parameter, attribute, or condition is achieved with minor variations (such as, for example, within acceptable manufacturing tolerances). By way of example, depending on the specific parameter, attribute, or condition that is substantially met, the parameter, attribute, or condition may be at least 90%, at least 95%, or even at least 99%.

[0029] The receiver front end may be used to handle high transmission transmit amplitudes that may be greater than one volt differential peak-to-peak (1 Vppd). Given that the transmit signals exceed one volt (1 Vppd), active equalizers implemented in low voltage technologies that operate in a range below these amplitudes have difficulty handling the dynamic peak-to-peak voltage potential range when determining the outer envelope of the received data eye. The receiver front end, which may include a passive attenuator or equalizer, may be used to attenuate the data eye envelope. It is desirable that such a passive attenuator or equalizer accommodate multiple channels, however, it is challenging to make such a passive attenuator or equalizer programmable at frequencies exceeding ten thousand megahertz (10 GHz) to accommodate multiple channels. If the passive front end circuit is made reconfigurable, then above 10 GHz, signal integrity is easily compromised. For example, channel loss (e.g., attenuation in the conductive trace that delivers the signal to the receiver front end, but not limited to this) is low at low frequencies (e.g., typically below 100 MHz in serial communications, but not limited to this), but increases with frequency (e.g., substantially proportional to frequency). The SerDes receiver front end should preferably compensate for the channel losses that increase with frequency, which may be greater than twenty to thirty-five decibels (20dB-35dB) at the Nyquist rate, so that the receiver front end (e.g., passive attenuator or equalizer) combined with the channel has an overall frequency response that is largely consistent with frequency. For a typical SerDes receiver known to the inventors of the present disclosure, the data eye envelope provided by the receiver front end may be no greater than about 400mVppd. Larger envelopes may cause the receiver circuit to enter a nonlinear region (e.g., saturation, clipping, but not limited thereto), which may cause distortion.

[0030] Disclosed herein is a front-end circuit having a passive equalizer and a programmable amplifier circuit. The front-end circuit disclosed herein can be particularly used for high-speed (e.g., substantially 10 GHz or greater channel frequency) data receivers (e.g., SerDes, but not limited thereto). The passive equalizer may include a fixed Zobel constant resistance bridge (sometimes referred to herein as a "Zobel network"). The impedance compensation arm of the fixed Zobel constant resistance bridge, which is not usually used in most applications, is used as a secondary signal path in addition to the main signal path of the fixed Zobel constant resistance bridge. The secondary signal path exhibits a complementary frequency response relative to the main signal path. By combining the signal from the main signal path and the signal from the secondary signal path in a programmable amplifier circuit (which may include a programmable dual-input summing amplifier), a flat and fully balanced frequency response can be obtained. Both inputs of the programmable dual-input summing amplifier receive a signal having a data envelope attenuated by a fixed amount of low-frequency de-emphasis of the fixed Zobel constant resistance bridge, and are therefore protected from the influence of excessive input voltage potential levels. At the same time, since the two signal paths of the fixed Zobel constant resistance bridge are properly terminated by the programmable dual-input summing amplifier, and since the fixed Zobel constant resistance bridge itself is fixed, the input return loss and signal integrity of the receiving path are ensured.

[0031] In some embodiments, the passive equalizer includes a fixed dual-path passive equalizer based on a fixed Zobel constant resistance bridge, and the programmable amplifier circuit includes a programmable gain summing amplifier that linearly combines two outputs from the fixed Zobel constant resistance bridge. The fixed Zobel constant resistance bridge includes two signal paths. The first signal path of the fixed Zobel constant resistance bridge represents a balanced response. The second signal path of the fixed Zobel constant resistance bridge represents the complement of the balanced response of the first signal path. The input impedances of the first signal path and the second signal path are complementary. In other words, the first signal path and the second signal path together represent a substantially constant resistance regardless of the frequency of the input signal applied thereto, because the reactive components of the impedances of the first signal path and the second signal path cancel each other. This ensures proper high-speed termination of the high-speed data receiver.

[0032] Typically, the first signal path and the second signal path are implemented by creating two parallel impedances. The first signal path may be formed by a series combination of a first terminal resistor having an impedance Zo (e.g., 50 ohms, but not limited thereto) and a frequency-dependent impedance Z. The second signal path may be formed by a series combination of a second terminal resistor having an impedance Zo and an impedance Z′ set to Z′=(Zo^2) / Z. When a fixed Zobel constant resistance bridge is implemented as a balanced bridge, because the output impedance is equal to the input impedance, the sensitivity to the downstream terminal is reduced, and therefore secondary reflections are greatly reduced.

[0033] Compared to using a programmable attenuator in front of an active equalizer (e.g., a CTLE, but not limited thereto) to bring the data envelope within the linear input range of the equalizer, the embodiments disclosed herein include a passive equalizer with a de-emphasis (peak) amount based on the longest channel used in the system (e.g., the longest length of conductive trace that delivers the input signal to the passive equalizer, but not limited thereto). The sum of the de-emphasis and the equivalent decision feedback equalizer (DFE) equalization is equal to the Nyquist channel loss, i.e., the absorption loss experienced by the signal transmitted along the communication channel at the Nyquist frequency. Therefore, the data envelope entering the programmable amplifier circuit (the active part of the receiver front end) is reduced to below its linearity limit, while the attenuation at the Nyquist frequency is kept to a minimum. No switches are required inside the passive equalizer. Instead, the effective amount of de-emphasis is determined by the programmable amplifier circuit. It is much easier to implement a programmable amplifier circuit than to implement a programmable passive attenuator or equalizer.

[0034] In some embodiments, several (eg, approximately 10) fixed Zobel constant resistance bridges may be constructed for each path. 2 or 10 3 , such as forty, but not limited to) amplifier slices (e.g., each slice includes a differential pair amplifier, but not limited to this). Gain adjustment is achieved by selectively turning the slices on or off. Since the input capacitance of the amplifier slices is largely constant, broadband matching is achieved regardless of the equalizer settings.

[0035] The front-end circuit disclosed herein counteracts the frequency-dependent losses of physical channels between computer servers, network cards, and / or chips that run serial data at high speeds (e.g., tens of thousands of megabytes per second, but not limited thereto). The losses that increase as the channel frequency increases are compensated by increasing the gain of the programmable amplifier with frequency, thereby obtaining a "flat" response and an "open eye." In addition, the front-end circuit system disclosed herein overcomes the often conflicting requirements of linearity, signal integrity, and programmability by using a dual-path passive equalizer (linearity) with complementary responses in front and a programmable amplifier circuit that combines the two responses, preferably in a linear manner.

[0036] The embodiments disclosed herein reduce the large transmit signal envelope entering the active device by using a passive equalizer front end to alleviate the linearity requirements. The embodiments disclosed herein decouple the programmability requirements of the passive equalizer and / or attenuator from the terminal requirements by using a fixed, constant resistance equalizer with dual outputs. The embodiments disclosed herein also separate the equalizer function from the gain function. Each (equalizer and gain) can be optimized and modeled without damaging each other. The summing circuit preferably implemented with a linear summing amplifier has a flat, wideband response, which is suitable for modeling by design tools.

[0037] Figure 1 is a circuit diagram of a Zobel network 100. The Zobel network 100 includes an impedance Z, an impedance Z′, a bridging impedance ZB, and a pair of reference impedances Z0. Impedance Z′ is substantially equal to the dual impedance of impedance Z relative to the reference impedance Z0: Z′=Z0^2 / Z. In addition, the reactive portion of the dual impedance Z′ cancels the reactive portion of impedance Z. The reference impedances are substantially equal to each other (Z0=Z0). The Zobel network 100 also includes an input 102 across a first node 106 and a fourth node 112, and an output 104 across a third node 110 and a fourth node 112. A first reference impedance and a dual impedance Z′ in the reference impedance Z0 are electrically connected in series across the input 102. In other words, the first reference impedance Z0 is electrically connected from the first node 106 to the second node 108, and the dual impedance Z′ is electrically connected from the second node 108 to the fourth node 112. A second reference impedance in the reference impedance Z0 is electrically connected across the output 104. In other words, the second reference impedance in the reference impedance Z0 is electrically connected from the third node 110 to the fourth node 112. Impedance Z is electrically connected from the first node 106 to the third node 110, and thus impedance Z and the second reference impedance in the reference impedance Z0 are thus electrically connected in series across the input 102. The bridging impedance ZB is electrically connected between the first reference impedance in the reference impedance Z0 and the dual impedance Z′, i.e., between impedance Z and the second reference impedance in the reference impedance Z0 from the second node 108. In other words, the bridging impedance ZB is electrically connected from the second node 108 to the third node 110.

[0038] The input impedance looking toward the input 102 of the Zobel network 100 is represented by ZIN. The output impedance looking toward the output 104 of the Zobel network 100 is represented by ZOUT. The values ​​of Z, Z′, and Z0 may be selected such that the Zobel network 100 is balanced (“balanced Zobel network”). As used herein, the term “balanced” when referring to an impedance network refers to a situation where the input impedance looking toward the input of the impedance network is substantially equal to the output impedance looking toward the output of the impedance network. Figure 1In the case of the Zobel network 100, when the input impedance ZIN is substantially equal to the output impedance ZOUT, the Zobel network 100 is balanced. In particular, the Zobel network 100 is balanced if the following relationship is substantially satisfied:

[0039]

[0040] The inverse of the input impedance ZIN (ie, input admittance) of the Zobel network 100 is given by the following formula:

[0041]

[0042] The dual impedance Z′ can be given by the following formula:

[0043]

[0044] When the Zobel network 100 is balanced, the input impedance ZIN of the Zobel network 100 may be substantially equal to the reference impedance Z0. If the reference impedance Z0 is selected to include substantially only active components (substantially no reactive components), the input impedance ZIN is substantially resistive.

[0045] The dual impedance Z' may be selected to be dual to the impedance Z. As used herein, the term "dual" when referring to a first impedance and a second impedance indicates that the second impedance is substantially a reference impedance squared divided by the first impedance (e.g., a balanced condition, or In the case of impedance Z and dual impedance Z′, if Z′ is substantially equal to Z0 2 / Z, then Z and Z' can be selected to be dual. If Z and Z' are dual, the Zobel network 100 is balanced, and the input impedance ZIN of the Zobel network 100 is substantially equal to the reference impedance Z0. The impedance Z and the dual impedance Z' can be first-order, second-order, or any order impedance network. The bridging impedance ZB can optionally be selected to be substantially equal to the reference impedance Z0. In such cases, the Zobel network 100 can be symmetrical.

[0046] As used herein, the term "complementary," when referring to a first frequency response and a second frequency response, indicates that the second frequency response exhibits substantially opposite behavior to the first frequency response over a frequency range of interest (e.g., 100 MHz to 100 GHz, but not limited thereto). For example, where the first frequency response is characteristic of a bandpass filter having a particular passband, the second frequency response would be characteristic of a bandstop filter having a particular stopband that is substantially the same as the particular passband of the first frequency response. Additionally, at frequencies where the first frequency response has a peak, the second frequency response has a valley. "Complementary" does not necessarily imply that the second frequency response exhibits exactly opposite behavior to the first frequency response. Rather, "complementary" indicates that adding the second frequency response to the first frequency response results in an overall frequency response that is flatter than the first frequency response alone.

[0047] Figure 2 is a circuit diagram of a second-order Zobel network 200. The second-order Zobel network 200 is Figure 1 For example, the second-order Zobel network 200 includes an impedance Z, a dual impedance Z′, a reference impedance Z0, and a bridge impedance ZB. In the second-order Zobel network 200, the impedance Z and the dual impedance Z′ are second-order impedance networks. For example, in Figure 2 In the second-order Zobel network 200, the impedance Z includes a first resistor R1 connected in parallel with a series combination of a capacitor C1 and an inductor L1, and the dual impedance Z′ includes a parallel combination of a capacitor C2 and an inductor L2 connected in series with a second resistor R2. The reference impedance and the bridge impedance of the second-order Zobel network 200 are each a reference resistor R0. Since the bridge impedance ZB is equal to the reference impedance Z0, Figure 2 The second-order Zobel network 200 is symmetrical.

[0048] Figure 2 The dual impedance Z′ is dual to the impedance Z with respect to the reference impedance Z0. In other words, therefore, Figure 2 The second-order Zobel network 200 is balanced. To achieve this, the value of the first resistor may be R1=N*R0 (where "*" is a multiplication operator), and the value of the second resistor may be R2=R0 / N (satisfying the balance condition), where N is a positive real number. In this example, the balance condition requires substantially achieving the following formula:

[0049] L2=Z0 2 *C1 and

[0050]

[0051] The transfer function of the second order Zobel network 200 following these conditions is given by the following formula:

[0052]

[0053] Where ω0 is 2πf0, f0 is the resonant frequency of the second-order Zobel network 200 (given by Given), ω is 2πf, f is the frequency of the input voltage potential VIN, s is jω, Q = ω0R0C2, and N is a positive real number. The input voltage potential VIN and the output voltage potential VO are each defined with respect to the reference voltage potential VREF. As long as the condition is satisfied The constant input resistance and balance of the second-order Zobel network 200 can be designed.

[0054] The top voltage potential VTOP and the bottom voltage potential VBOT may be made above the parallel combination of L2 and C2 and below the parallel combination of L2 and C2, respectively, relative to a reference voltage potential VREF (e.g., ground or other specified voltage, but not limited thereto). Note that the VTOP voltage potential is substantially equal to the output voltage potential VO due to the aforementioned equilibrium condition being satisfied. The frequency response of the bottom voltage potential VBOT may be substantially complementary to the frequency response of the top voltage potential VTOP. One way to ensure that the frequency response of the bottom voltage potential VBOT is substantially complementary or opposite to the frequency response of the top voltage potential VTOP is to set Z and Z′ to be dual. In other words, the transfer function HTOP=VTOP / VIN of the top voltage potential VTOP relative to the input voltage potential VIN may have a peak at substantially the same frequency at which the transfer function HBOT=VBOT / VIN of the bottom voltage potential VBOT relative to the input voltage potential VIN has a valley. In addition, HTOP may have a valley at a frequency at which HBOT has a peak. It can be shown that the transfer functions HTOP and HBOT are complementary as functions of the complex frequency s when HBOT is weighted by N: HTOP(s)+N*HBOT(s)=1. Figure 2 For a second-order Zobel network 200, the transfer functions HTOP and HBOT are given by the following formulas:

[0055] and

[0056]

[0057] Figure 3 is a graph showing the input voltage signal VIN (in response to the value of N being set to one (N=1) Figure 2 )of Figure 2 A graph 300 is shown of the frequency response of the top voltage potential VTOP and the bottom voltage potential VBOT of the second-order Zobel network 200. The graph 300 includes the frequency (in Hertz) plotted against the frequency (in Hertz) and the frequency (in Hertz) of the top voltage potential VTOP and the bottom voltage potential VBOT, respectively. Figure 2 300 . The top voltage potential VTOP curve 302 and the bottom voltage potential VBOT curve 304 are plotted in units of voltage potential magnitude, or in other words, in units of volts (V). As can be seen in the curve 300 , the bottom voltage potential VBOT curve 304 exhibits a frequency response that is substantially opposite to the frequency response of the top voltage potential VTOP curve 302 . It should be noted that although the weighted vector sum of HTOP and N*HBOT is equal to one, this is not necessarily true for the magnitudes |HTOP and |HBOT|. Therefore, the two curves |HTOP and |HBOT| corresponding to the top voltage potential VTOP curve 302 and the bottom voltage potential VBOT curve 304 , respectively, do not add up to one, but |HTOP+HBOT| does equal one.

[0058] Since the bottom voltage potential VBOT curve 304 has a frequency response that is substantially opposite to the frequency response of the top voltage potential VTOP curve 302, a linear combination of the top voltage potential VTOP curve 302 and the bottom voltage potential VBOT curve 304 will correspond to a substantially flat frequency response of the passive equalizer. Therefore, embodiments of the present disclosure utilize a passive equalizer including complementary signal paths and a programmable amplifier circuit that is programmed to cancel the frequency dependence of the channel, thereby providing a substantially flat frequency response for the combination of the channel and the receiver front end.

[0059] Figure 4 4 is a block diagram of a data receiver 400 according to some embodiments. The data receiver 400 includes a front end circuit 406 configured to utilize a passive equalizer 402 including complementary signal paths (a first signal path 410 and a second signal path 412) and an amplifier circuit 404 configured to add signals (a first equalizer output signal VAO and a second equalizer output signal VBO) from the first signal path 410 and the second signal path 412, preferably linearly, to provide a substantially flat frequency response of an equalized output signal VEQZ in response to an input signal VIN.

[0060] As previously mentioned, the first signal path 410 and the second signal path 412 are complementary. Therefore, the impedance of the second signal path 412 is dual to the impedance of the first signal path 410. Therefore, in response to the input signal VIN, the frequency response of the second equalizer output signal VBO is substantially opposite to the frequency response of the first equalizer output signal VAO. As a non-limiting example, the frequency response of the first signal path 410 may have a peak at the Nyquist frequency, and the frequency response of the second signal path 412 may have a notch at the Nyquist frequency. The passive equalizer 402 can compensate for the large signal envelope of the input signal VIN by reducing the signal envelopes of the first equalizer output signal VAO and the second equalizer output signal VBO to within the linear input range of the amplifier circuit 404 using passive circuits, without the need for programmability of the passive equalizer 402. Reference is made below to Figure 5 and Figure 6 A more detailed example of a passive equalizer is discussed.

[0061] The amplifier circuit 404 includes a first amplifier 414, a second amplifier 416, and an adding circuit 418. The first amplifier 414 and the second amplifier 416 are configured to receive a first equalizer output signal VAO and a second equalizer output signal VAO, respectively. The first amplifier 414 is configured to amplify the first equalizer output signal VAO by a gain A to generate a first amplified signal VAA. The second amplifier 416 is configured to amplify the second equalizer output signal VBO by a gain 1-A (one minus the gain of the first amplifier 414) to generate a second amplified signal VAB. It should be noted that the gain of the second amplifier 416 can be selected to be different from 1-A and can even be independent of A. However, by using the gain of the second amplifier 416, the gain is a function of the gain A of the first amplifier 414, so only a single variable A is introduced to determine the gains of both the first amplifier 414 and the second amplifier 416. The adding circuit 418 is configured to add the first amplified signal VAA and the second amplified signal VAB to generate the equalized signal VEQZ. Thus, the amplifier circuit 404 is configured to combine the responses of the first signal path 410 and the second signal path 412. Figure 7 Further details regarding examples of amplifier circuit 404 are discussed.

[0062] The amplifier circuit 404 is a programmable amplifier circuit. The data receiver 400 also includes a control circuit 408 configured to provide a control signal 420 to control the gain of the first amplifier 414 and the second amplifier 416, which may be programmable gain amplifiers. As a non-limiting example, the control signal 420 may be configured to control the value of A of the first amplifier 414 and the second amplifier 416.

[0063] The configuration of the front end circuit 406 separates the equalization function (performed by the passive equalizer 402) from the gain function (performed by the amplifier circuit 404). Therefore, the passive equalizer 402 and the amplifier circuit 404 can be optimized separately without compromising each other.

[0064] Figure 5 is a circuit diagram of a passive equalizer 500 according to some embodiments, which can be used as Figure 4 4. The passive equalizer 402 of the data receiver 400 of FIG. 4 is a schematic diagram of a passive equalizer 402 of FIG. 4. The passive equalizer 500 includes a signal input 512 (e.g., a conductive pin, a connector, a trace, or a wire, but not limited thereto) and an equalizer output 510. The equalizer output 510 includes a first equalizer output 506 and a second equalizer output 508 (e.g., a conductive pin, a connector, a trace, or a wire, but not limited thereto). The passive equalizer 500 also includes a first signal path 502 between the signal input 512 and the first equalizer output 506. The passive equalizer 500 also includes a second signal path 504 between the signal input 512 and the second equalizer output 508.

[0065] Passive Equalizer 500 with Figure 2 The second-order Zobel network 200 has some similarities. For example, the impedance Z of the first signal path 502 is dual to the impedance ZA′ of the second signal path 504. Also by way of example, the passive equalizer 500 includes a circuit similar to Figure 2 The impedance Z and the dual impedance Z' of the impedance Z and the dual impedance ZA'. Similar to Figure 2 The impedance Z and the dual impedance Z' are second-order impedance networks. However, it should be noted that the impedance Z and the dual impedance ZA' can be alternatively implemented as first-order, third-order, fourth-order or any other order impedance network without exceeding the scope of the present disclosure. In addition, Figure 5 The impedance Z of comprises a first resistor R1 in parallel with a series combination of capacitor C1 and inductor L1, and the dual impedance ZA′ comprises a parallel combination of capacitor C2 and inductor L2 in series with a second resistor R2A. Figure 2 The first resistor R1, Figure 5 The value of the first resistor R1 may be the reference resistor R0 multiplied by N (R1=R0*N). Figure 5 The value of the second resistor R2A is the reference resistor R0 divided by N-1 In contrast, Figure 2 The value of the second resistor R2 is R2 = R0 / N. The passive equalizer 500 and Figure 2 Another difference between the second-order Zobel network 200 and the passive equalizer 500 is that the passive equalizer 500 does not include a reference resistor R0 between the first equalizer output 506 and the reference voltage potential VREF, but an amplifier circuit (eg, Figure 4 The input impedance of the amplifier circuit 404 (but not limited to this) can be set to be substantially equal to R0 so that the passive equalizer 500 is similar to Figure 2 The selection of the value of N, and by extension the values ​​of R1 and R2A, may be based at least in part on the length of the physical channel (e.g., a conductive trace in an integrated circuit chip including the passive equalizer 500, but not limited thereto) that carries the input signal VIN to the signal input 512, as shown in FIG. Figure 8 and Fig. 9 discussed.

[0066] Passive Equalizer 500 with Figure 2 These differences between the second order Zobel network 200 can compensate for the input impedance equal to the reference resistance R0, which looks to the first amplifier electrically connected to the first equalizer output 506 and the second amplifier electrically connected to the second equalizer output 508 (e.g., Figure 4 Assuming that an amplifier having R0 as its input impedance is electrically connected to the first equalizer output 506 and the second equalizer output 508, the passive equalizer 500 is equivalent to Figure 2 The second-order Zobel network 200. In such a case, the passive equalizer 500 is balanced.

[0067] The passive equalizer 500 includes a signal input 512 and a Figure 2 The passive equalizer 500 further includes a bridging impedance 514 that bridges the first signal path 502 to the second signal path 504. The bridging impedance 514 is set to have an impedance equal to the reference resistor R0, similar to Figure 2 The bridging impedance ZB of the second-order Zobel network 200 is.

[0068] In operation, an input signal VIN is provided to the passive equalizer 500 and is applied to a first signal path 502 and a second signal path 504. In response, the first signal path 502 provides a first equalizer output signal VBO to a first equalizer output 506, and the second signal path 504 provides a second equalizer output signal VAB to a second equalizer output 508. The second equalizer output signal VBO exhibits a frequency response that is substantially opposite to the frequency response of the first equalizer input signal VAO.

[0069] The passive equalizer 500 attenuates the envelopes of the first and second equalizer output signals VAO and VBO compared to the envelope of the input signal VIN. The passive equalizer 500 also provides termination (eg, appropriate frequency response, but not limited thereto) to the input signal VIN to reduce return loss.

[0070] It should be noted that the values ​​of the first resistor R1 and the second resistor R2A are fixed. Therefore, the passive equalizer 500 is implemented without variable resistors, which can simplify the design, implementation, and operation of the passive equalizer 500 compared to an equalizer circuit using variable resistors (e.g., electrically controlled potentiometers, which may include switching elements in integrated circuit implementations, but are not limited thereto).

[0071] Figure 6 is a circuit diagram of an alternative passive equalizer 600 according to some embodiments, which may be used as Figure 4 The passive equalizer 402 of the data receiver 400 is shown in FIG. 6 . The alternative passive equalizer 600 includes a signal input 612 and an equalizer output 610, the equalizer output including a first equalizer output 606 and a second equalizer output 608. The signal input 612, the equalizer output 610, the first equalizer output 606 and the second equalizer output 608 are similar to Figure 5 The passive equalizer 500 includes a signal input 512 , an equalizer output 510 , a first equalizer output 506 , and a second equalizer output 508 .

[0072] The alternative passive equalizer 600 also includes a first signal path 602 and a second signal path 604. Although the first signal path 602 and the second signal path 604 are complementary, the alternative passive equalizer 600 does not include a bridging impedance that bridges the first signal path 602 to the second signal path 604, in contrast to the passive equalizer 500 that includes a bridging impedance 514 that bridges the first signal path 502 to the second signal path 504 ( Figure 5 ). The first signal path 602 includes an impedance Z, and the second signal path 604 includes a dual impedance ZB′, similar to Figure 5 The impedance Z and the dual impedance ZA′. Similar to Figure 5 The impedance Z and the dual impedance ZA′, Figure 6 The impedance Z and the dual impedance ZB′ are second-order impedance networks. However, it should be noted that the impedance Z and the dual impedance ZB′ may alternatively be implemented as first-order, third-order, fourth-order, or any other order impedance networks. In addition, Figure 6 The impedance Z of comprises a first resistor R1 in parallel with a series combination of capacitor C1 and inductor L1, and the dual impedance ZB′ comprises a parallel combination of capacitor C2 and inductor L2 in series with a second resistor R2B. Figure 2and Figure 5 The first resistor R1, Figure 6 The value of the first resistor R1 may be the reference resistor R0 multiplied by N (R1=R0*N). Figure 6 The value of the second resistor R2B is N+1 multiplied by the reference resistance R0, divided by N-1 In contrast, Figure 5 The value of the second resistor R2A is The alternative passive equalizer 600 further includes a resistor R1 (value R1 =N*R0) electrically connected from between the parallel combination of the second inductor L2 and the second capacitor C2 and the second resistor R2B to the second equalizer output 608 .

[0073] In operation, an input signal VIN is provided to the signal input 612, and thus to the first signal path 602 and the second signal path 604. The first signal path 602 provides a first equalizer output signal VAO to the first equalizer output 606 in response to the input signal VIN. The second signal path 604 provides a second equalizer output signal VBO to the second equalizer output 608 in response to the input signal VIN. The second equalizer output signal VBO exhibits a frequency-dependent behavior that is opposite to the frequency-dependent behavior of the first equalizer output signal VAO.

[0074] In the case of an alternative passive equalizer 600 configured as discussed above, the resistance value of the second resistor R2B may be selected to be generally relatively higher than Figure 5 The resistance value of the second resistor R2A ( compared to ). This is because the resistance value of the second resistor R2B is in the same order of magnitude as the reference resistance value R0 regardless of the value of N (assuming that N is not equal to 1), even if the value of N is selected to be relatively high (for example, N>3, but not limited thereto). As a non-limiting example, if N=4, then R2B=(5 / 3)*R0. Also as a non-limiting example, if N=10, then R2B=(11 / 9)*R0. In contrast, if N is relatively large, then Figure 5 The resistance value of the second resistor R2A may be much smaller than the resistance value of the reference resistor R0. As a non-limiting example, if N=4, then R2A=(1 / 3)*R0. Also as a non-limiting example, if N=10, then R2A=(1 / 9)*R0. It may be relatively difficult to implement very small resistors on an integrated circuit chip because implementing very small resistors may involve placing several larger resistors in parallel, which consumes a relatively large chip area to implement. Therefore, with Figure 5Compared to the passive equalizer 500 , the alternative passive equalizer 600 has an advantage in that, since the resistance value of the second resistor R2B is in the same order of magnitude as the reference resistor R0 , its chip area can be reduced compared to the chip area of ​​the passive equalizer 500 .

[0075] However, Figure 5 The passive equalizer 500 also has its advantages. As a non-limiting example, since the passive equalizer 500 includes a bridge impedance 514 ( Figure 5 ), so the passive equalizer 500 can be balanced (i.e., the output impedance of the passive equalizer 500 can be substantially equal to the input impedance of the passive equalizer 500). When the signals (i.e., the first equalizer output signal VAO and the second equalizer output signal VBO) are provided to the amplifier circuit (e.g., Figure 4 When the passive equalizer 500 is used with the amplifier circuit 404 (but not limited to the amplifier circuit 404), the passive equalizer 500 may experience fewer reflections compared to the alternative passive equalizer 600.

[0076] Figure 7 According to some embodiments, Figure 4 The programmable amplifier circuit 700 of the amplifier circuit 404 of the data receiver 400 is a circuit diagram of the programmable amplifier circuit 700. The programmable amplifier circuit 700 may be Figure 4 4. The programmable amplifier circuit 700 includes a first amplifier input 712, a second amplifier input 714, a first impedance matching network 708, a second impedance matching network 710, a first programmable gain amplifier 702, a second programmable gain amplifier 704, a summing circuit 706, and an amplifier output 716. The first amplifier input 712 and the second amplifier input 714 are configured to receive a signal from a passive equalizer (e.g., Figure 4 Passive equalizer 402, Figure 5 Passive equalizer 500, Figure 6 The alternative passive equalizer 600 (e.g., but not limited to) receives the first equalizer output signal VAO and the second equalizer output signal VBO respectively. Therefore, the first amplifier input 712 and the second amplifier input 714 can be electrically connected to the passive equalizer (e.g., electrically connected to Figure 5 The first equalizer output 506 and the second equalizer output 508 are electrically connected to Figure 6 The first equalizer output 606 and the second equalizer output 608 are, but not limited to, those of the embodiment of the present invention.

[0077] The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are programmable amplifiers having gains (a gain of A for the first programmable gain amplifier 702 and a gain of 1-A for the second programmable gain amplifier 704). As a non-limiting example, the gains (i.e., the values ​​of A) of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 are responsive to a control signal from a control circuit (e.g., Figure 4 The control signal 420 of the control circuit 408 (but not limited thereto) may be electrically programmable. The control circuit 408 is used to change the gain in response to the frequency of VIN and information about the channel length to provide compensation for the channel.

[0078] In some embodiments, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can each be implemented using multiple amplifiers (e.g., complementary metal oxide semiconductor (CMOS) differential pair amplifiers, but not limited thereto), which can be individually controlled to enable or disable. Therefore, the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be increased by enabling a larger number of amplifiers thereof. Similarly, the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be reduced by disabling a larger number of amplifiers thereof. In other embodiments, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 can be implemented using an operational amplifier circuit including an electrically controlled resistor to adjust the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704.

[0079] It may be assumed that an ideal amplifier has infinite input impedance and zero output impedance. However, in practice, all amplifiers have finite input impedance and non-zero output impedance. Then, as a result, in practice, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 have finite input impedance and non-zero output impedance. Therefore, the first impedance matching network 708 and the second impedance matching network 710 are configured to provide appropriate impedance termination to the passive equalizer electrically connected to the first impedance matching network 708 and the second impedance matching network 710. As a non-limiting example, Figure 5 The passive equalizer 500 and Figure 6 The alternative passive equalizer 600 is designed for termination substantially equal to the reference resistor R0. Thus, the first impedance matching network 708 and the second impedance matching network 710 may be configured such that the input impedance looking into the first amplifier input 712 and the second amplifier input 714 is substantially equal to the reference resistor R0.

[0080] In an embodiment where the first programmable gain amplifier 702 and the second programmable gain amplifier 704 are implemented using a plurality of CMOS differential pair amplifiers that can be controllably enabled or disabled to adjust the gain of the first programmable gain amplifier 702 and the second programmable gain amplifier 704, the input impedance of the first programmable gain amplifier 702 and the second programmable gain amplifier 704 may have a relatively large capacitive component. In such an embodiment, the first impedance matching network 708 and the second impedance matching network 710 are configured to compensate for these large capacitive components. As a non-limiting example, the first impedance matching network 708 and the second impedance matching network 710 may include a bridged t-coil network to compensate for the large capacitive component.

[0081] The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are configured to amplify the first equalizer output signal VAO and the second equalizer output signal VBO to generate a first amplified signal VAA and a second amplified signal VAB, respectively. More specifically, the first programmable gain amplifier 702 is configured to amplify the first equalizer output signal VAO by a gain A to generate a first amplified signal VAA. In addition, the second programmable gain amplifier 704 is configured to amplify the second equalizer output signal VBO by a gain 1-A to generate a second amplified signal VAB. In the programmable amplifier circuit 700 and Figure 5 Passive equalizer 500 or Figure 6 In some embodiments of the alternative passive equalizer 600, the value of A may be 1 / (N+1), where N is the value of Figure 5 and Figure 6 The same N discussed. The first programmable gain amplifier 702 and the second programmable gain amplifier 704 are electrically connected to the summing circuit 706. Therefore, the first programmable gain amplifier 702 and the second programmable gain amplifier 704 are configured to provide the first amplified signal VAA and the second amplified signal VAB to the summing circuit 706.

[0082] The adding circuit 706 is configured to receive the first amplified signal VAA and the second amplified signal VAB, and generate an equalized signal VEQZ based on the sum of the first amplified signal VAA and the second amplified signal VAB, which is preferably linear. In some embodiments, the adding circuit 706 may include a linear adding amplifier (for example, implemented using an operational amplifier, but not limited thereto). Assume that the programmable amplifier circuit 700 is configured to have the above-mentioned Figure 4 The passive equalizer 402 of the passive equalizer is used together with the properties discussed above, and assuming that the first impedance matching network 708 and the second impedance matching network 710 provide impedance matching, the equalized signal VEQZ provided at the amplifier output 716 is relative to the source signal (i.e., the signal injected into the channel, and its output is Figure 4 , Figure 5 and Figure 6 The VIN in the output has a flat frequency response.

[0083] Figure 8 is shown plotted against frequency from Figure 4 Graph 800 is an example of an equalized signal VEQZ of a front-end circuit 406, wherein the signal input of the front-end circuit 406 is electrically connected to a relatively short physical channel (e.g., a relatively short conductive trace of an integrated circuit device that delivers an input signal VIN from a source signal to the front-end circuit 406, but is not limited thereto). The equalized signal VEQZ of graph 800 is shown in decibel volts (dB V). Specifically, graph 800 includes A=0.1 curve 802, A=0.2 curve 804, A=0.3 curve 806, A=0.4 curve 808, A=0.5 curve 810, A=0.6 curve 812, A=0.7 curve 814, A=0.8 curve 816, A=0.9 curve 818, and A=1.0 curve 820, where A is the A=0.1 curve 802, A=0.2 curve 804, A=0.3 curve 806, A=0.4 curve 808, A=0.5 curve 810, A=0.6 curve 812, A=0.7 curve 814, A=0.8 curve 816, A=0.9 curve 818, and A=1.0 curve 820, wherein ... Figure 4 and Figure 7 The A in question (i.e. Figure 4 The first amplifier 414 or Figure 7 The value of N=4 for the passive equalizer 402 (see above for reference) Figure 5 and Figure 6 The discussed N) is used to generate the graph 800.

[0084] When examining graph 800, A=0.2 curve 804 may show a flatter frequency response than A=0.1 curve 802, A=0.3 curve 806, A=0.4 curve 808, A=0.5 curve 810, A=0.6 curve 812, A=0.7 curve 814, A=0.8 curve 816, A=0.9 curve 818, or A=1.0 curve 820. Thus, in a relatively short physical channel electrically connected to front-end circuit 406 ( Figure 4 ), N=4 and A=0.2 may be appropriate design choices for implementing the front-end circuit 406. Note that for short physical channels, an appropriate relationship between A and N may be given by A=1 / (N+1).

[0085] Fig. 9 is shown plotted against frequency from Figure 4Graph 900 is an example of an equalized signal VEQZ of a front-end circuit 406 of a device, wherein the signal input of the front-end circuit 406 is electrically connected to a medium-length physical channel (e.g., a medium-length conductive trace of an integrated circuit device that delivers an input signal VIN from a source signal to the front-end circuit 406, but is not limited thereto). The equalized signal VEQZ of graph 900 is shown in dB V. Specifically, graph 900 includes A=0.1 curve 902, A=0.2 curve 904, A=0.3 curve 906, A=0.4 curve 908, A=0.5 curve 910, A=0.6 curve 912, A=0.7 curve 914, A=0.8 curve 916, A=0.9 curve 918, and A=1.0 curve 920, where A is the value of the A=0.1 curve 902, A=0.2 curve 904, A=0.3 curve 906, A=0.4 curve 908, A=0.5 curve 910, A=0.6 curve 912, A=0.7 curve 914, A=0.8 curve 916, A=0.9 curve 918, and A=1.0 curve 920, wherein ... Figure 4 and Figure 7 The A in question (i.e. Figure 4 The first amplifier 414 or Figure 7 The gain of the first programmable gain amplifier 702 is similar to Figure 8 800, the value of N=4 for the passive equalizer 402 (see above for reference Figure 5 and Figure 6 The discussed N) is used to generate the curve graph 900.

[0086] When examining graph 900, A=0.8 curve 916 may show a flatter frequency response than A=0.1 curve 902, A=0.2 curve 904, A=0.3 curve 906, A=0.4 curve 908, A=0.5 curve 910, A=0.6 curve 912, A=0.7 curve 914, A=0.9 curve 918, or A=1.0 curve 920. Thus, in the case of a medium length physical channel electrically connected to front end circuitry 406 ( Figure 4 ), N=4 and A=0.8 may be appropriate design choices for implementing the front-end circuit 406. Note that in some embodiments, the values ​​of N, A, or both may be selected based at least in part on the length of the channel electrically connected to the signal input of the front-end circuit 406.

[0087] Fig.10 1 is a graph 1000 showing an example of a channel input signal curve 1002, a channel output signal curve 1004, and an equalized signal VEQZ curve 1006. The channel input signal curve 1002 is a signal at the input to a physical channel (e.g., a conductive trace, but not limited thereto), the output of which is electrically connected to a Figure 4 The channel output signal curve 1004 is the signal at the output of the physical channel in response to the channel input signal curve 1002 applied to the physical channel, or in other words, the channel output signal curve 1004 is the input signal VIN ( Figure 4 ). Equalized signal VEQZ curve 1006 is an equalized signal VEQZ obtained from the output of the front end circuit 406 in response to the channel output signal curve 1004 applied to the signal input of the front end circuit 406.

[0088] It is evident from the channel input signal curve 1002 and the channel output signal curve 1004 that the physical channel attenuates the signal applied to its input, and that this attenuation generally increases with frequency. While the channel output signal curve 1004 decreases steadily with frequency, the equalized signal VEQZ curve 1006 exhibits a substantially flat response through a passband 1010 ending at a cutoff frequency 1008 (at -3 dB attenuation) of substantially 12.8 GHz.

[0089] Fig.11 Shown with Fig.10 100. Specifically, the eye diagram graph 1100 includes the channel input signal eye diagram 1102, the channel output signal eye diagram 1104, and the equalized signal VEQZ eye diagram 1106. As can be seen in the eye diagram graph 1100, any opening that exists in the channel input signal eye diagram 1102 is closed in the channel output signal eye diagram 1104. As can also be seen in the eye diagram graph 1100, the eye is open in the equalized signal VEQZ eye diagram 1106. Therefore, even if the signal transmitted to the front-end circuit 406 ( Figure 4 ) input signal VIN( Figure 4 ) Due to the physical channel, the eye is closed, and the front end circuit 406 still provides an equalized signal VEQZ with an open eye ( Figure 4 ).

[0090] Fig.12 is a diagram showing the use of some embodiments Figure 4 Flowchart of a method 1200 for equalizing an input signal in a front-end circuit 406 of a first embodiment. In operation 1202, the method 1200 generates a first equalizer output signal in response to an input signal applied to a first signal path. The first signal path has a first frequency response. In operation 1204, the method 1200 generates a second equalizer output signal in response to an input signal applied to a second signal path. The second signal path has a second frequency response. The second frequency response is substantially opposite to the first frequency response. In operation 1206, the method 1200 amplifies the first equalizer output signal with a first gain to generate a first amplified signal. In operation 1208, the method 1200 amplifies the second equalizer output signal with a second gain to generate a second amplified signal. In operation 1210, the method 1200 adds the first amplified signal to the second amplified signal to generate a balanced output signal.

[0091] Example

[0092] The following is a non-exhaustive, non-limiting list of exemplary embodiments. Not every one of the exemplary embodiments listed below is clearly and individually indicated as combinable with all other embodiments in the exemplary embodiments listed below and the above-described embodiments. However, it is intended that these exemplary embodiments can be combined with all other exemplary embodiments and the above-described embodiments unless it is obvious to one of ordinary skill in the art that these embodiments cannot be combined.

[0093] Embodiment 1: A passive equalizer, comprising: a signal input; an equalizer output, the equalizer output comprising a first equalizer output and a second equalizer output; a first signal path, the first signal path being between the signal input and the first equalizer output, the first signal path having a first frequency response in response to an input signal provided to the signal input; and a second signal path, the second signal path being between the signal input and the second equalizer output, the second signal path having a second frequency response in response to the input signal provided to the signal input, the second frequency response exhibiting a behavior substantially opposite to that of the first frequency response.

[0094] Embodiment 2: The passive equalizer according to embodiment 1, wherein the first signal path and the second signal path form respective parts of a Zobel network.

[0095] Embodiment 3: The passive equalizer according to embodiment 2, wherein the Zobel network is implemented as a balanced Zobel network.

[0096] Embodiment 4: The passive equalizer according to any one of Embodiments 1 to 3, wherein the first signal path and the second signal path include a second-order impedance network.

[0097] Embodiment 5: The passive equalizer according to any one of Embodiments 1 to 4 further comprises a bridging impedance, wherein the bridging impedance bridges the first signal path and the second signal path.

[0098] Embodiment 6: The passive equalizer according to any one of Embodiments 1 to 4, wherein the first signal path and the second signal path are substantially free of a bridging element bridging the first signal path and the second signal path.

[0099] Embodiment 7: A passive equalizer according to any one of Embodiments 1 to 6, wherein: the first signal path includes a first impedance network, the first impedance network includes a first resistor connected in parallel with a series combination of a first capacitor and a first inductor; and the second signal path includes a parallel combination of a second capacitor and a second inductor, the parallel combination of the second capacitor and the second inductor is connected in series with a second resistor.

[0100] Embodiment 8: A passive equalizer according to any one of Embodiments 1 to 7, wherein: the first equalizer output is configured to provide a first equalizer output signal to a programmable amplifier circuit; the second equalizer output is configured to provide a second equalizer output signal to the programmable amplifier circuit; and the programmable amplifier circuit is configured to amplify and add the first equalizer output signal and the second equalizer output signal to provide a balanced output signal.

[0101] Embodiment 9: A front-end circuit for a data receiver, the front-end circuit comprising: a passive equalizer, the passive equalizer being configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, the impedance of the first signal path and the impedance of the second signal path being dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit, the programmable amplifier circuit being configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier, the first programmable gain amplifier being configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier, the second programmable gain amplifier being configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and an adding circuit, the adding circuit being configured to add the first amplified signal and the second amplified signal to provide a balanced output signal.

[0102] Embodiment 10: The front-end circuit according to embodiment 9, wherein the second gain is equal to the difference between one and the first gain.

[0103] Embodiment 11: A front-end circuit according to any one of Embodiments 9 and 10, wherein the programmable amplifier circuit further comprises: a first impedance matching network, which is configured to terminate the first signal path; and a second impedance matching network, which is configured to terminate the second signal path.

[0104] Embodiment 12: The front-end circuit according to any one of Embodiments 9 to 11 further includes a control circuit configured to provide a control signal to the programmable amplifier circuit to control the first gain and the second gain.

[0105] Embodiment 13: A front-end circuit according to any one of embodiments 9 to 12, wherein the programmable amplifier circuit comprises a programmable gain adding amplifier.

[0106] Embodiment 14: The front-end circuit according to any one of embodiments 9 to 13, wherein the adding circuit comprises a linear adding amplifier.

[0107] Embodiment 15: A front-end circuit according to any one of Embodiments 9 to 14, wherein at least one of the first programmable gain amplifier and the second programmable gain amplifier includes an amplifier slice, each amplifier slice includes a differential pair amplifier, and gain adjustment of the at least one of the first programmable gain amplifier and the second programmable gain amplifier is achieved by selectively opening or closing the amplifier slice.

[0108] Embodiment 16: A data receiver comprises a front-end circuit, the front-end circuit comprising: a passive equalizer, the passive equalizer being configured to receive an input signal, the passive equalizer comprising a first signal path and a second signal path, the impedance of the first signal path and the impedance of the second signal path being dual to each other, the first signal path being configured to provide a first equalizer output signal in response to the received input signal, the second signal path being configured to provide a second equalizer output signal in response to the received input signal; and a programmable amplifier circuit, the programmable amplifier circuit being configured to receive the first equalizer output signal and the second equalizer output signal from the passive equalizer, the programmable amplifier circuit comprising: a first programmable gain amplifier, the first programmable gain amplifier being configured to amplify the first equalizer output signal with a first gain to provide a first amplified signal; a second programmable gain amplifier, the second programmable gain amplifier being configured to amplify the second equalizer output signal with a second gain to provide a second amplified signal; and an adding circuit, the adding circuit being configured to add the first amplified signal and the second amplified signal to provide a balanced output signal.

[0109] Embodiment 17: The data receiver of Embodiment 16, wherein the data receiver is implemented as a serializer / deserializer.

[0110] Embodiment 18: The data receiver according to any one of Embodiments 16 and 17 further includes a control circuit configured to control the first gain of the first programmable gain amplifier and the second gain of the second programmable gain amplifier.

[0111] Embodiment 19: A method for equalizing an input signal, the method comprising: generating a first equalizer output signal in response to the input signal applied to a first signal path, the first signal path having a first frequency response; generating a second equalizer output signal in response to the input signal applied to a second signal path, the second signal path having a second frequency response, the second frequency response being substantially opposite to the first frequency response; amplifying the first equalizer output signal with a first gain to generate a first amplified signal; amplifying the second equalizer output signal with a second gain to generate a second amplified signal; and adding the first amplified signal to the second amplified signal to generate a balanced output signal.

[0112] Embodiment 20: A method according to Embodiment 19, wherein generating the first equalizer output signal in response to the input signal applied to the first signal path and generating the second equalizer output signal in response to the input signal applied to the second signal path includes applying the input signal to a second-order impedance network.

[0113] Embodiment 21: A method according to any one of Embodiments 19 and 20, wherein generating the second equalizer output signal in response to the input signal applied to the second signal path includes generating the second equalizer output signal in response to the input signal applied to a second impedance, which is dual to the first impedance of the first signal path.

[0114] Embodiment 22: A method according to any one of Embodiments 19 to 21, wherein amplifying the second equalizer output signal with the second gain includes amplifying the second equalizer output signal with the second gain minus the first gain.

[0115] Embodiment 23: A method according to any one of Embodiments 19 to 22, wherein: amplifying the first equalizer output signal includes applying the first equalizer output signal to a first programmable gain amplifier; and amplifying the second equalizer output signal includes applying the second equalizer output signal to a second programmable gain amplifier.

[0116] Conclusion

[0117] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads, etc., but not limited thereto). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0118] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or any of various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0119] The terms used in this disclosure, especially in the appended claims (e.g., the subject matter of the appended claims, but not limited thereto) are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” and the term “comprising” should be interpreted as “including but not limited to,” but not limited thereto).

[0120] Additionally, if a specific number of an introduced claim recitation is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an embodiment containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more", but not limited thereto); the same is true when a claim recitation is introduced using a definite article.

[0121] Furthermore, even if a specific number of an introduced claim expression is explicitly recited, one skilled in the art will recognize that such expression should be interpreted to mean at least the recited number (e.g., the unmodified expression "two expressions" means at least two expressions, or two or more expressions, without limitation, in the absence of other modifying elements). Furthermore, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0122] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0123] Although the present invention is described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features of another embodiment while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A front-end circuit, comprising: A passive equalizer, the passive equalizer comprising: a signal input for receiving an input signal on a channel; equalizer outputs, the equalizer outputs comprising a first equalizer output for providing a first equalizer output signal and a second equalizer output for providing a second equalizer output signal; a first signal path between the signal input and the first equalizer output, the first signal path having a first frequency response in response to a received input signal; and a second signal path between the signal input and the second equalizer output, the second signal path having a second frequency response in response to a received input signal, the second frequency response exhibiting behavior substantially opposite to that of the first frequency response to provide a substantially flat frequency response to the passive equalizer; and A programmable amplifier circuit, the programmable amplifier circuit being configured to: receiving the first equalizer output signal and amplifying the first equalizer output signal with a first gain; receiving the second equalizer output signal and amplifying the second equalizer output signal with a second gain; and adding the amplified first equalizer output signal and the amplified second equalizer output signal to provide an equalized output signal, Wherein the programmable amplifier circuit is programmable to provide a substantially flat frequency response for a combination of the channel and the front end circuit. 2 . The front-end circuit of claim 1 , wherein the first signal path and the second signal path form respective parts of a Zobel network. 3 . The front-end circuit according to claim 2 , wherein the Zobel network is implemented as a balanced Zobel network. 4 . The front-end circuit of claim 1 , wherein the first signal path and the second signal path comprise second-order impedance networks. 5 . The front-end circuit of claim 1 , further comprising a bridging impedance that bridges the first signal path with the second signal path. 6 . The front-end circuit of claim 1 , wherein the first signal path and the second signal path are substantially free of a bridging element bridging the first signal path and the second signal path.

7. The front-end circuit according to claim 1, wherein: The first signal path includes a first impedance network including a first resistor connected in parallel with a series combination of a first capacitor and a first inductor; And the second signal path includes a parallel combination of a second capacitor and a second inductor, the parallel combination of the second capacitor and the second inductor being connected in series with a second resistor.

8. The front-end circuit according to claim 1, wherein: the programmable amplifier circuit amplifies the first equalizer output signal with the first gain, the first gain comprising a gain A; and The programmable amplifier circuit amplifies the second equalizer output signal with the second gain, and the second gain includes a gain of (1-A).

9. A method of equalizing an input signal received on a channel, the method comprising: The following operations are performed at the passive equalizer of the front-end circuit: generating a first equalizer output signal in response to a received input signal applied to a first signal path, the first signal path having a first frequency response; generating a second equalizer output signal in response to a received input signal applied to a second signal path, the second signal path having a second frequency response that is substantially opposite to the first frequency response to provide a substantially flat frequency response to the passive equalizer; The following operations are performed at the programmable amplifier circuit of the front-end circuit: amplifying the first equalizer output signal with a first gain to generate a first amplified signal; amplifying the second equalizer output signal with a second gain to generate a second amplified signal; as well as adding the first amplified signal to the second amplified signal to generate a balanced output signal, Wherein the programmable amplifier circuit is programmed to have the first gain and the second gain to provide a substantially flat frequency response for a combination of the channel and the front end circuit.

10. The method of claim 9, wherein generating the first equalizer output signal in response to the input signal applied to the first signal path and generating the second equalizer output signal in response to the input signal applied to the second signal path includes applying the input signal to a second-order impedance network.

11. The method of claim 9, wherein generating the second equalizer output signal in response to the input signal applied to the second signal path comprises generating the second equalizer output signal in response to the input signal applied to a second impedance that is dual to the first impedance of the first signal path.

12. The method of claim 9, wherein amplifying the second equalizer output signal with the second gain comprises amplifying the second equalizer output signal with the second gain being one minus the first gain.

13. The method according to claim 9, wherein: amplifying the first equalizer output signal comprises applying the first equalizer output signal to a first programmable gain amplifier of the programmable amplifier circuit; and Amplifying the second equalizer output signal includes applying the second equalizer output signal to a second programmable gain amplifier of the programmable amplifier circuit.

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