Wafer yield loss determination, wafer yield pass / fail determination method and apparatus

Abstract

This application provides a method and apparatus for determining wafer yield loss and judging wafer yield compliance based on sampling inspection. The method for determining wafer yield loss includes at least the following steps: constructing a catastrophic defect database, wherein the catastrophic defect database consists of the total catastrophic defect data of various defect types in various regions when the test wafer passes through each process station; obtaining a defect distribution map of the wafer passing through a certain process station, and determining the defect density of at least one defect type based on the defect distribution map; and obtaining the wafer yield loss rate based on the defect density and the total catastrophic defect data of the corresponding regions in the catastrophic defect database. This application can more accurately determine the wafer yield loss rate, thereby achieving a more accurate judgment of wafer product compliance.

Description

Technical Field

[0001] This application relates to a wafer product, and more particularly to a method and apparatus for determining wafer yield loss and judging wafer yield compliance. Background Technology

[0002] Defects in the wafer manufacturing process can significantly impact the final yield of wafers. Low-yield products not only lead to customer rejection but also damage the company's image and cause economic losses. Therefore, final electrical testing is typically performed before shipment to determine whether the yield requirements are met. However, relying solely on final testing to decide whether a product can be shipped is not only time-consuming but also wasteful of resources. To address this, yield inspection stations are usually added to intermediate process steps to prevent losses as soon as anomalies are detected. However, when defects are detected in intermediate processes, because the overall process is not yet complete, it is not possible to directly determine whether they affect the final yield as easily as with final electrical testing.

[0003] For defects detected in intermediate processes, the current approach is to first collect data on different types of defects (i.e., their destructive power) in each process, and then determine the destructive power of each type of defect on the wafer by the final yield loss.

[0004] Defect impact density × Defect lethality = Yield loss rate Table 1 AA-ET Chemical residues 10% 25% 2.5% POLY-DEP stain 20% 10% 2.0% CT-CMP Mechanical damage 30% 35% 10.5% TM-ET Metal wire broken 40% 40% 16.0% Suppose a wafer composed of 1000 chips is found to have chemical residue defects after a certain process. After defect scanning, it is found that 100 chips are affected, with an impact density of 10%. After final testing, it is found that the yield loss due to chemical residue is 2.5%, as shown in Table 1. Therefore, it can be concluded that the destructive power of chemical residue in this process is 25%. After obtaining the average destructive power from multiple data points, it is not necessary to wait for the final test. Instead, the final yield loss can be estimated by multiplying the impact density by the average destructive power.

[0005] While the method of directly determining whether a product meets shipping standards using the final calculated yield loss rate is convenient, current calculations of the destructive power of various defect types are rather general. In reality, chips contain many different regions, and the same defect in the same process will result in different yield losses depending on the region on the chip. Therefore, the yield loss rate calculated using current technology is not very accurate. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method and apparatus for determining wafer yield loss and judging wafer yield qualification based on sampling inspection, so as to solve the problem of inaccurate wafer qualification judgment in the prior art.

[0007] To achieve the above and other related objectives, this application provides a method for determining wafer yield loss, the method comprising at least the following steps: A lethality database is constructed, which is the total lethality data of various defect types in each region when the test wafer passes through each process station; Obtain a defect distribution map of the wafer at a certain process station, and determine the defect density of at least one defect type based on the defect distribution map. The wafer yield loss rate is obtained based on the defect density and the total lethality data of each region in the lethality database.

[0008] Preferably, the method for obtaining the total destructive power data of a certain type of defect in various regions when a test wafer passes through a certain process station includes: The chip on the test wafer is divided into at least two regions using a set method to obtain a chip region map; The defect distribution map of the test wafer after passing through a certain process station is obtained by scanning, and the scanning defect situation is determined according to the chip area map and the defect distribution map; Obtain the test result image of the test wafer, and determine the yield loss based on the chip area image and the test result image; The total destructive power data of the test wafer in each region is determined based on the scan defect situation and the yield loss situation.

[0009] Preferably, determining the density of at least one type of defect based on the defect distribution map includes: The wafer is divided into at least two regions using the aforementioned method to obtain a chip region map; A defect matching map is obtained by processing the defect distribution map based on the chip region map; Defect density is determined using a defect matching map.

[0010] Preferably, the setting method is that different regions of the chip have different functions.

[0011] Preferably, the step of obtaining the wafer yield loss rate based on the defect density and the corresponding lethality data in the lethality database includes: Retrieve the total lethality data of the corresponding defect type of the test wafer in each region from the lethality database; Calculate the yield loss rate caused by defects in each area of ​​the wafer based on the total destructive power data of each area. The wafer yield loss rate is obtained by calculating the yield loss rate caused by defects in different areas of the wafer.

[0012] Preferably, the wafer yield loss rate is obtained by summing the yield loss rates caused by defects in various regions of the wafer.

[0013] To achieve the above and other related objectives, this application also provides an apparatus for determining wafer yield loss, the apparatus comprising: processor; A memory on which computer programs that can run on the processor are stored; The computer program, when executed by the processor, implements the aforementioned method for determining wafer yield loss.

[0014] To achieve the above and other related objectives, this application also provides a method for determining wafer yield based on random sampling, the method comprising: Determine the wafer yield loss; the wafer yield loss is obtained using the method described above for determining wafer yield loss. The wafer's quality is determined based on the wafer yield loss rate.

[0015] Preferably, the determination of whether a wafer is qualified is based on the wafer yield loss rate; When the wafer yield loss rate is greater than or equal to the set value, the wafer is directly judged as unqualified; When the wafer yield loss rate is less than the set value, it is necessary to make another judgment based on the wafer yield loss rate of subsequent random inspections or the final wafer yield loss rate.

[0016] To achieve the above and other related objectives, this application also provides a wafer yield acceptance determination device based on random sampling, the device comprising: processor; A memory on which computer programs that can run on the processor are stored; When the computer program is executed by the processor, it implements the above-mentioned wafer yield acceptance method based on random sampling.

[0017] As described above, the method and apparatus for determining wafer yield loss and judging wafer yield pass / fail based on random sampling in this application have the following beneficial effects: The wafer yield loss and wafer yield acceptance criteria proposed in this application involve first constructing a damage database, then analyzing and processing the obtained wafer defect distribution to determine the defect density of at least one defect type, and finally obtaining the wafer yield loss based on the defect density and the total damage data of each corresponding region in the damage data. The constructed database contains the total damage data of the wafer in each region, which, compared to the damage data of wafer chips in existing technologies, makes the final wafer yield loss rate more accurate. Attached Figure Description

[0018] Figure 1 The diagram shows a flowchart illustrating the method for determining wafer yield loss in this application.

[0019] Figure 2 The diagram shown is a schematic representation of the chip region division result of the test wafer in this embodiment of the application.

[0020] Figure 3 The diagram shown is a test partition map after dividing the defect distribution of the test wafer in this embodiment of the application.

[0021] Figure 4 The diagram shown is a test matching diagram of the defect distribution of the test wafer in an embodiment of this application.

[0022] Figure 5 The image shown is a matching diagram of the test results for testing the defect distribution of a wafer in an embodiment of this application.

[0023] Figure 6 The diagram shown is a schematic representation of the chip region division of the wafer in an embodiment of this application.

[0024] Figure 7 The diagram shown is a partition map of the wafer defect distribution after being divided in this embodiment of the application.

[0025] Figure 8 The diagram shown is a defect matching map of wafer defect distribution in an embodiment of this application. Detailed Implementation

[0026] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0027] Please see Figure 1-8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] A chip contains regions with different characteristics, such as logic and storage. These regions have different sensitivities to different defects, and therefore the destructive power of defects to them also varies. This application divides the wafer product into different regions, pre-constructs the destructive power of each defect type to each region at each process station, imports the defect distribution map that has been scanned and includes the defect location, calculates the yield loss separately, and sums up the multiple results to obtain the final yield loss.

[0029] Based on the above technical concept, this application provides a new technical solution, which is described in detail through the following embodiments.

[0030] Method Example 1: To address the aforementioned technical problems, this application proposes a method for determining wafer yield loss, the flowchart of which is shown below. Figure 1 As shown, it includes at least the following steps: Step S1: Construct a lethality database, which is the total lethality data of various defect types in each region when the test wafer passes through each process station. A wafer consists of multiple identical chips. During the wafer manufacturing process, various types of defects may occur in each process step. However, some defects are so few that they only affect the yield and can be ignored. Therefore, the yield loss rate is calculated based on the analysis of the relatively large number of defect types. That is, the defect types that affect the final yield loss are analyzed during the testing process. Thus, tests are performed in advance based on various defect types to obtain the final yield loss. The total number of defects in each area is obtained by combining the yield loss and the defect loss.

[0031] Specifically, assuming only one process produces one type of defect, the method for obtaining the total lethality data of one defect type in each region will be used as an example. Therefore, determining the total lethality data of each defect type in each region includes the following steps: Step S11: Divide the chip of the test wafer into at least two regions to obtain a chip region map; Depending on their function, the chips on the test wafer are divided into at least two regions. In this embodiment, the region division result is the same for each chip. Figure 2 The diagram shown illustrates the partitioning of chip regions within a wafer, with three distinct regions: region A, region B, and region C. Alternatively, the wafer can be divided into two regions; the specific number of regions obtained depends on the wafer product being manufactured and the partitioning method used.

[0032] Step S12: Scan and obtain the defect test distribution map of the test wafer after it has passed through a certain process station, and determine the scanned defect situation based on the chip area map and the defect test distribution map; S121, Based on the chip region map, the defect test distribution map is processed to obtain a test defect matching map; This step essentially involves first dividing the defect test distribution map according to the size ratio of the 20 chips in the wafer, as shown below. Figure 3 The test partition map shown has 20 chip ranges; then the 20 chip ranges are divided according to the chip area map in step S11, resulting in the following... Figure 4 The test defect matching diagrams shown are 20 chip region diagrams with the same pattern. S122, Determine the scanned defect status by testing the defect matching map; pass Figure 4 It can be seen that the number of defective chips tested is 10, with 2 chips in area A, 3 chips in area B, and 5 chips in area C.

[0033] Step S13: Obtain the test result map of the test wafer, and determine the yield loss based on the chip area map and the test result map; In this embodiment of the application, although there are 10 defective chips in the final test wafer product, only 4 of them (the chips represented by ×) are useful for calculating the actual yield loss. Therefore, the number of chips with yield loss is 4.

[0034] S131, Based on the chip region map, the test result map is processed to obtain a test result matching map; This step essentially involves first dividing the test result image according to the size ratio of the M chips in the wafer to obtain a test result image with a range of M chips; then, dividing the M chip ranges according to the chip region image in step S11 to obtain M test result images with the same chip region image, as shown below. Figure 5 The test result matching diagram shown; since this embodiment only analyzes one type of defect, the resulting test result diagram and defect test distribution are... Figure 1 Similarly, in practice, other defects may occur at process stations after the defect test result map is obtained, so the obtained test result map will be different from the defect distribution map.

[0035] S132, determine the yield loss by matching the test results with the graph; pass Figure 5 Yield analysis revealed that the number of chips causing yield loss was 4 (× represents the number of chips), with 1 chip in region A, 2 chips in region B, and 2 chips in region C.

[0036] Step S14: Determine the total destructive power data of the test wafer in each region based on the scan defect situation and the yield loss situation.

[0037] The total lethality data is obtained by processing the number of defects in each region in the defect scanning situation and the number of defects in each region in the yield loss situation.

[0038] Table 2 A 2 2 100% B 3 1 33% C 5 1 20% The processing method is as follows: yield loss ÷ number of defects = lethality data. Therefore, the lethality of area A is 100%, the lethality of area B is 33%, and the lethality of area C is 20%.

[0039] The above method can be used to obtain the lethality data of other process sites and other defect types. All lethality data are processed to form a lethality database as shown in Table 3.

[0040] Table 3 Type 1 100% 33% 20% ... Type K 50% 20% 10% ... Step S2: Obtain a defect distribution map of the wafer as it passes through a certain process station, and determine the defect density of at least one defect type based on the defect distribution map; The method for determining the density of a type of defect based on the defect distribution map includes: Step S21: Divide the wafer into at least two regions to obtain a chip region map; In this embodiment, the chips on the test wafer are divided into at least two regions based on their different functions, meaning that the region division result is the same for each chip. Figure 6 The diagram showing the division of the chip regions in the wafer has three distinct regions: region A, region B, and region C.

[0041] Step S22: Process the defect distribution map based on the chip region map to obtain a defect matching map; This step essentially involves first dividing the defect distribution map according to the size ratio of the 20 chips in the wafer, as shown below. Figure 7 The result distribution map shown has 20 chip ranges; then the 20 chip ranges are divided according to the chip region map in step S21, resulting in the following... Figure 8 The image shows 20 defect matching diagrams with the same chip region map; Step S23: Determine the defect density using the defect matching map; Step S231: Determine the number of defects in different regions of the wafer using the defect matching map; Specifically, through Figure 8 It can be seen that there are a total of 10 defects, of which 1 is in area A, 1 is in area B, and 8 are in area C, as shown in Table 4.

[0042] Step S231: Then, based on the number of defects in different regions of the wafer and the number of chips in the wafer, the defect density in different regions of the wafer is obtained; The defect density in different regions of a wafer = the number of defects in different regions ÷ the total number of chips. Therefore, the defect density in region A is 5%, the defect density in region B is 5%, and the defect density in region C is 40%.

[0043] Table 4 A 1 5% 50% 2.5% B 1 5% 20% 1.0% C 8 40% 10% 4.0% wafer 7.5% Step S3: Obtain the wafer yield loss rate based on the defect density and the total lethality data of each region in the lethality database.

[0044] Step S31: Retrieve the total damage data of the corresponding defect type of the test wafer in each region from the damage database; In this embodiment of the application, only one type of defect is determined. The total lethality data of each region retrieved from the lethality database are as follows: the total lethality data of region A is 50%, the total lethality data of region B is 20%, and the total lethality data of region C is 10%.

[0045] Step S32: Calculate the yield loss rate caused by defects in each region of the wafer based on the total damage data of each region; Yield loss rate for each region = Defect density × Damage data for each region Specifically, the yield loss rate for area A is calculated as 5% × 50% = 2.5%, meaning the yield loss rate caused by the wafer in area A is 2.5%; the yield loss rate for area B is calculated as 5% × 20% = 1.0%, meaning the yield loss rate caused by the wafer in area B is 1.0%; and the yield loss rate for area C is calculated as 40% × 10% = 4.0%, meaning the yield loss rate caused by the wafer in area C is 4.0%.

[0046] Step S33: Obtain the wafer yield loss rate based on the yield loss rate caused by defects in various regions of the wafer.

[0047] This step essentially involves summing the yield loss rates of each region to obtain the wafer yield loss rate. In this embodiment, the wafer yield loss rate is 2.5% + 1% + 4% = 7.5%. Since only one defect type is identified in this embodiment, the wafer yield loss rate can be obtained by directly summing the yield loss rates of each region. In other embodiments, where two defect types are identified, the wafer yield loss rate for each type needs to be obtained first, and then the wafer yield loss rates for multiple types need to be summed to obtain the final wafer yield loss rate.

[0048] In the embodiments of this application, some steps do not have a sequential relationship. To make the examples clearer, the steps are described. For example, there is no sequential relationship between step S1 and step S2. Step S1 can be executed first, followed by step S2; or step S2 can be executed first, followed by step S1; or steps S1 and S2 can be executed simultaneously. It is understood that the above description is only exemplary, and the embodiments of this application do not limit the scope of the application.

[0049] Device Example 1: To address the aforementioned technical problems, this application proposes a device for determining wafer yield loss, the device comprising: processor; A memory on which computer programs that can run on the processor are stored; The computer program, when executed by the processor, implements the aforementioned method for determining wafer yield loss.

[0050] The specific process of determining the wafer yield loss has been described in detail in the above-mentioned method embodiment one, and will not be repeated here.

[0051] Method Example 2: To address the aforementioned technical problems, this application proposes a wafer yield acceptance method based on random sampling, the method comprising: Determine the wafer yield loss; the wafer yield loss is obtained using the method described above for determining wafer yield loss. The wafer's quality is determined based on the wafer yield loss rate.

[0052] As a further limitation of this application, the determination of whether a wafer is qualified is based on the wafer yield loss rate; When the wafer yield loss rate is greater than or equal to the set value, the wafer is directly judged as unqualified; When the wafer yield loss rate is less than the set value, it is necessary to make another judgment based on the wafer yield loss rate of subsequent random inspections or the final wafer yield loss rate.

[0053] In this embodiment of the application, in order to ensure that the shipment yield requirement is 90%, the wafer yield loss rate must not be greater than 10%.

[0054] In practice, there may be only one or two yield sampling checks. The defect distribution map of the current sampling is judged. If the judgment is not appropriate, the wafer can be scrapped directly, and the previous process stations are analyzed and repaired. If the judgment is qualified, it is necessary to judge again by the wafer yield loss rate of subsequent sampling checks or the final wafer yield loss rate.

[0055] Device Example 2: To address the aforementioned technical problems, this application proposes a wafer yield acceptance judgment device based on random sampling, the device comprising: processor; A memory on which computer programs that can run on the processor are stored; When the computer program is executed by the processor, it implements the above-mentioned wafer yield acceptance method based on random sampling.

[0056] The specific process of the wafer yield qualification judgment method based on sampling inspection has been described in detail in the above-mentioned method embodiment two, and will not be repeated here.

[0057] In summary, this application differentiates between different wafer products, different process sites, and the characteristics of their wafer chips in various regions, defining the total destructive power of various wafer defect types in different regions, thus making the calculated wafer yield loss rate more accurate. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0058] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for determining wafer yield loss, characterized in that, The method includes at least the following steps: A damage database is pre-built. The damage database is the total damage data of various defect types in each region when the test wafer passes through each process station. The total damage data is used to quantify the probability that a certain defect type will cause chip yield loss when it falls in a certain region at a certain process station. Obtain a defect distribution map of the wafers currently being produced through a certain process station, and determine the defect density of at least one defect type based on the defect distribution map; Based on the defect density and the total lethality data of each region in the lethality database, the wafer yield loss rate of the currently produced wafer at a certain process station is calculated.

2. The method for determining wafer yield loss according to claim 1, characterized in that, Methods for obtaining the total destructive power data of a certain type of defect in various regions when a test wafer passes through a certain process station include: The chip on the test wafer is divided into at least two regions using a set method to obtain a chip region map; The defect distribution map of the test wafer after passing through a certain process station is obtained by scanning, and the scanning defect situation is determined according to the chip area map and the defect distribution map; Obtain the test result image of the test wafer, and determine the yield loss based on the chip area image and the test result image; The total destructive power data of the test wafer in each region is determined based on the scan defect situation and the yield loss situation.

3. The method for determining wafer yield loss according to claim 2, characterized in that, Determining the defect density of at least one defect type based on the defect distribution map includes: The wafer is divided into at least two regions using the aforementioned method to obtain a chip region map; A defect matching map is obtained by processing the defect distribution map based on the chip region map; Defect density is determined using a defect matching map.

4. The method for determining wafer yield loss according to claim 3, characterized in that, The configuration method is such that different areas of the chip have different functions.

5. The method for determining wafer yield loss according to claim 1, characterized in that, The step of obtaining the wafer yield loss rate based on the defect density and the corresponding lethality data in the lethality database includes: Retrieve the total lethality data of the corresponding defect type of the test wafer in each region from the lethality database; Calculate the yield loss rate caused by defects in each area of ​​the wafer based on the total destructive power data of each area. The wafer yield loss rate is obtained by calculating the yield loss rate caused by defects in different areas of the wafer.

6. The method for determining wafer yield loss according to claim 5, characterized in that, The wafer yield loss rate is obtained by summing the yield loss rates caused by defects in various regions of the wafer.

7. A device for determining wafer yield loss, characterized in that, The device includes: processor; A memory on which computer programs that can run on the processor are stored; When the computer program is executed by the processor, it implements the method for determining wafer yield loss as described in any one of claims 1-6.

8. A method for judging wafer yield based on random sampling, characterized in that, The method includes: Determine the wafer yield loss; the wafer yield loss is obtained using the method for determining wafer yield loss as described in any one of claims 1-6; The wafer's quality is determined based on the wafer yield loss rate.

9. The wafer yield acceptance method based on sampling inspection according to claim 8, characterized in that, The wafer is judged to be qualified based on the wafer yield loss rate; When the wafer yield loss rate is greater than or equal to the set value, the wafer is directly judged as unqualified; When the wafer yield loss rate is less than the set value, it is necessary to make another judgment based on the wafer yield loss rate of subsequent random inspections or the final wafer yield loss rate.

10. A wafer yield acceptance judgment device based on random sampling, characterized in that, The device includes: processor; A memory on which computer programs that can run on the processor are stored; When the computer program is executed by the processor, it implements the wafer yield acceptance method based on sampling inspection as described in any one of claims 8-9.

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