A semiconductor device and a method of fabricating the same
By forming a barrier structure and adjusting the size of the photolithography layer in the semiconductor device, the problems of contact unit position deviation and connectivity were solved, achieving higher photolithography accuracy and contact unit stability, and improving the integration and reliability of the semiconductor device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
- Filing Date
- 2021-09-01
- Publication Date
- 2026-05-08
AI Technical Summary
In the prior art, due to the shrinking of the process window, positional deviations and interconnections between adjacent contact units occur during the formation of contact units, affecting the integration and reliability of semiconductor devices.
A barrier structure is formed in the spacer region between adjacent gate stacks, and a contact opening is formed on the interlayer dielectric layer to expose the gate stack. By adjusting the size of the photolithography layer and the mask layer, the contact cells are prevented from connecting, thereby increasing the load area of the contact cells and the gate stack.
This effectively avoids the connection between adjacent contact units, reduces the difficulty of photolithography, increases the opening size of the photolithography layer, improves the carrying space of the contact unit and the gate stack, and ensures the accurate positioning and stability of the contact unit.
Smart Images
Figure CN115732399B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor device and its fabrication method. Background Technology
[0002] Currently, the semiconductor process window is being continuously compressed as device integration increases, even approaching the design limits of optical and etching equipment. This poses significant challenges to device design. For example, the shrinking process window greatly reduces the space for forming contact units, leading to positional deviations in previously separate contact units, and even connections between adjacent contact units. (Refer to...) Figure 1 As shown, Figure 1 This is a comparison chart of ideal semiconductor devices and those actually manufactured. Figure 1 This is a top-down view. The root cause of the aforementioned defects is actually the formation process of the contact cells connecting the gate stack. (Reference) Figure 2 , Figure 2 The semiconductor devices shown are Figure 1 The cross-sectional structure at position AA in section a. During the formation of contact cells connecting the gate stack, a patterned photolithographic layer 8' is typically deposited above the interlayer dielectric layer 6' of its transition intermediate; the interlayer dielectric layer is etched according to this patterned photolithographic layer to form contact openings 200' exposing the gate stack. Ideally, in the deposited patterned photolithographic layer, the required photolithographic openings corresponding to adjacent gate stacks are not continuous, such as... Figure 1 As shown in Figure a. However, in actual production, as the process nodes of devices gradually shrink, the corresponding photolithographic aperture size also shrinks, easily leading to the appearance of adjacent photolithographic aperture connections, such as... Figure 1 As shown in b.
[0003] Therefore, in an ideal state, the contact cells above adjacent gate stacks do not shift in position and are not interconnected. However, due to the increase in device integration, the critical size of the contact cells is approaching the photolithography limit, which greatly compresses the patterning space during the photolithography process, resulting in limited exposure. After patterning, the size of the photolithography layer deviates, causing the contact cells formed according to the photolithography pattern to bridge. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a semiconductor device and its fabrication method, addressing the defects of the prior art where the contact units exhibit positional deviations or even interconnection between adjacent contact units.
[0005] The technical solution adopted by this invention to solve its technical problem is: a method for fabricating a semiconductor device, the method comprising:
[0006] An intermediate is provided, the intermediate including a substrate and an interlayer dielectric layer, a source / drain structure and a plurality of gate stacks spaced apart from each other are formed on the substrate, and the interlayer dielectric layer is formed on the substrate and covers the source / drain structure and the gate stacks;
[0007] A barrier structure is formed above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks;
[0008] Contact openings are formed on the interlayer dielectric layer to expose the gate stack and the obstruction structure is removed;
[0009] Material is filled into the contact opening to form a contact unit.
[0010] Preferably, the intermediate further includes a patterned mask layer located on the interlayer dielectric layer, the patterned mask layer exposing the area on the interlayer dielectric layer corresponding to the contact cells of the pre-formed source / drain structure and covering the area on the interlayer dielectric layer corresponding to the contact cells of the pre-formed gate structure.
[0011] The method of etching a patterned mask layer based on a patterned photolithography layer to form a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks includes: depositing a patterned photolithography layer above the interlayer dielectric layer and the patterned mask layer; etching the patterned mask layer based on the patterned photolithography layer to form a barrier structure above the spacing region between adjacent gate stacks; and removing the remaining photolithography layer.
[0012] Preferably, the sidewall of the barrier structure, which extends in the same direction as the gate stack, is a non-curved plane.
[0013] Preferably, the formation of a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks specifically includes:
[0014] A lower photolithography layer, an intermediate photolithography layer, and an upper photolithography layer are deposited sequentially to form three photolithography layers. The upper photolithography layer is patterned by exposure, and the intermediate photolithography layer is etched according to the patterned upper photolithography layer to pattern the intermediate photolithography layer.
[0015] The lateral dimensions of the patterned intermediate photolithography layer are adjusted by lateral etching.
[0016] Based on the patterned intermediate photolithography layer after size adjustment, the lower photolithography layer is etched to make the lower photolithography layer patterned;
[0017] The patterned mask layer is etched according to the patterned lower photolithography layer to form a barrier structure;
[0018] Remove the remaining photolithography layer.
[0019] Preferably, the etching of a patterned mask layer based on a patterned photolithography layer to form a barrier structure corresponding to the spacer region of adjacent gate stacks includes:
[0020] A patterned mask layer is etched along the depth direction of the device based on the patterned photolithography layer to expose the interlayer dielectric layer;
[0021] The remaining patterned mask layer is laterally etched to adjust its lateral dimensions in order to form a barrier structure.
[0022] Preferably, the gate stack includes a gate and a capping layer deposited over the gate; the barrier structure includes a first barrier layer abutting the interlayer dielectric layer;
[0023] The first barrier layer and the cover layer are made of the same material; and / or, the thickness of the first barrier layer is set to be greater than or equal to 30 nm; and / or, the thickness difference between the first barrier layer and the cover layer is less than or equal to 5 nm.
[0024] Preferably, the barrier structure includes a first barrier layer abutting against the interlayer dielectric layer and a second barrier layer disposed above the first barrier layer;
[0025] The second barrier layer and the interlayer dielectric layer are made of the same material; and / or, the thickness of the second barrier layer is set to be greater than or equal to 5 nm.
[0026] Preferably, the gate stack includes a gate and a capping layer deposited over the gate; the barrier structure includes a first barrier layer abutting the interlayer dielectric layer and a second barrier layer disposed above the first barrier layer;
[0027] The method of etching the interlayer dielectric layer according to the barrier structure to form a contact opening for exposing the gate stack and removing the barrier structure includes: depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer; etching the interlayer dielectric layer according to the patterned photolithography layer; continuing to etch and remove the capping layer after exposing the capping layer to form a contact opening for exposing the gate; and removing the remaining photolithography layer.
[0028] Wherein, the second barrier layer is removed while the interlayer dielectric layer is being etched; and / or, the first barrier layer is removed while the cover layer is being etched away.
[0029] Preferably, the barrier structure is a single-layer structure, and the thickness of the barrier structure is greater than or equal to 45 nm.
[0030] Preferably, the gate stack includes a gate and a capping layer deposited over the gate; the barrier structure is a single-layer structure;
[0031] The method of etching the interlayer dielectric layer according to the barrier structure to form a contact opening for exposing the gate stack and removing the barrier structure includes: depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer; etching the interlayer dielectric layer according to the patterned photolithography layer to expose a portion of the capping layer; removing the remaining photolithography layer; removing the barrier structure; and continuing to etch to remove the capping layer to form a contact opening for exposing the gate.
[0032] The semiconductor device and its fabrication method of the present invention have the following beneficial effects: The present invention forms a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks. Subsequently, contact openings exposing the gate stacks are formed on the interlayer dielectric layer, and the barrier structure is removed. The presence of the barrier structure prevents communication between adjacent contact units. Furthermore, the barrier structure of the present invention is formed by etching a mask layer. The lateral dimension of the formation process can be flexibly adjusted, and the opening size of the upper photolithography layer can be close to the width of adjacent gates and their spacing regions in that direction. Compared with existing solutions, this increases the opening size of the photolithography layer, reduces photolithography difficulty, and, through the protective effect of the barrier structure, accurately positions the contact openings above the gate stacks, increasing the load area of the contact units and gate stacks. In addition, the present invention can controllably adjust the spacing of the contact openings through the design of a patterned mask layer, thereby creating contact units and gates with greater load-bearing space. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort:
[0034] Figure 1 It is a comparison chart of ideal semiconductor devices and actual manufactured semiconductor devices;
[0035] Figure 2 This is a schematic diagram illustrating the fabrication principle of semiconductor devices in existing technologies;
[0036] Figure 3 This is a flowchart of the semiconductor device fabrication method according to Embodiment 1 of the present invention;
[0037] Figure 4 This is a schematic diagram of the matrix structure;
[0038] Figure 5 This is a schematic diagram of the formation of a mask layer;
[0039] Figure 6 This is a schematic diagram of the mask layer pattern;
[0040] Figure 7 This is a schematic diagram illustrating the formation of the intermediate;
[0041] Figure 8 This is a schematic diagram of the barrier structure;
[0042] Figure 9 This is one of the schematic diagrams showing the contact openings of the exposed gate stack.
[0043] Figure 10 This is the second schematic diagram of the contact openings that expose the gate stack.
[0044] Figure 11 This is a schematic diagram of the formation of contact units;
[0045] Figure 12 This is a schematic diagram of the contact openings of the exposed gate stack in Embodiment 2. Detailed Implementation
[0046] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0047] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
[0049] The terms "first," "second," and other ordinal numbers used in this specification are used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is solely to distinguish one constituent element from others. For example, a first constituent element may be named a second constituent element without departing from the scope of the invention, and similarly, a second constituent element may be named a first constituent element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0050] The general idea of this invention is as follows: In the process of fabricating semiconductor devices, after forming an intermediate body, a barrier structure is formed above the interlayer dielectric layer corresponding to the spacer region between adjacent gate stacks. The material of the barrier structure has similar etching characteristics to the metal material of the gate. Then, contact openings exposing the gate stacks are formed on the interlayer dielectric layer and the barrier structure is removed. In this way, the presence of the barrier structure can prevent two adjacent contact units from connecting.
[0051] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.
[0052] Example 1
[0053] refer to Figure 3 The method for fabricating the semiconductor device in this embodiment includes:
[0054] S1. Provide a matrix;
[0055] refer to Figure 4 The substrate includes a substrate 1 and an interlayer dielectric layer 6. A plurality of spaced-apart source / drain structures 2 and a plurality of spaced-apart gate stacks are formed on the substrate 1. The interlayer dielectric layer 6 is formed on the substrate 1 and covers the source / drain structures 2 and the gate stacks.
[0056] Specifically, the gate stack may include a gate 3, sidewalls (not shown) abutting against the sidewalls of the gate 3, a capping layer 4 deposited above the gate 3 and the sidewalls to protect the gate, and a stop layer 5. The capping layer 4 serves to protect the gate 3 below it and may be made of silicon nitride. The stop layer 5 abuts against and covers the source / drain structure 2 with the sidewalls of the gate stack. The interlayer dielectric layer 6 covers the capping layer 4, the sidewalls, and the stop layer 5. The interlayer dielectric layer 6 also fills the gap region between adjacent gate stacks and may be made of silicon oxide.
[0057] S2. A mask layer 7 is deposited on top of the interlayer dielectric layer 6 of the substrate;
[0058] refer to Figure 5In this embodiment, the mask layer includes an upper mask layer 73, a middle mask layer 72, and a lower mask layer 71. The upper mask layer 73 assists in the subsequent formation of the contact unit 100a that abuts the source / drain structure 2. The lower mask layer 71 serves to form the barrier structure 7b that separates the spacer region between adjacent gate stacks. The middle mask layer 72 acts as a transition layer to separate the upper mask layer 73 and the lower mask layer 71. Preferably, the upper mask layer 73 is made of a nitrogen-containing compound, such as titanium nitride; and the lower mask layer 71 is made of a nitrogen-containing compound, such as silicon nitride. It is understood that the middle mask layer 72 can also be omitted, but in this embodiment, the etching selectivity between the upper mask layer 73 and the lower mask layer 71 is relatively low, so a transition layer is added to avoid the risk of damage to the lower mask layer 71 during the etching process of the upper mask layer 73.
[0059] S3. Pattern the mask layer 7 to expose the area on the interlayer dielectric layer 6 corresponding to the contact unit of the pre-formed source / drain structure 2;
[0060] refer to Figure 6 This step specifically includes: depositing a patterned photolithography layer 8 above the mask layer. The photolithography layer 8 is also divided into three layers: upper, middle, and lower. The pattern of the photolithography layer 8 is required to expose the area on the interlayer dielectric layer 6 corresponding to the pre-formed contact unit 100a of the source / drain structure 2, and cover the area on the interlayer dielectric layer 6 corresponding to the pre-formed contact unit 200a of the gate 3; etching the mask layer 7 according to the patterned photolithography layer 8 to form a patterned mask layer 7a and expose the area on the interlayer dielectric layer 6 corresponding to the pre-formed contact unit 100a of the source / drain structure 2. The remaining area covered by the patterned mask layer 7a is the area corresponding to the pre-formed contact unit 200a of the gate 3; and removing the remaining photolithography layer 8.
[0061] S4. Form a contact opening 100 on the interlayer dielectric layer 6 to expose the source / drain structure 2;
[0062] refer to Figure 7 This step specifically includes: depositing a patterned photolithography layer over the patterned mask layer 7a and the interlayer dielectric layer 6. The pattern of the photolithography layer is required to form a contact opening 100 for exposing the source / drain structure 2 by etching the interlayer dielectric layer 6 according to the pattern; etching the interlayer dielectric layer 6 according to the patterned photolithography layer to form the contact opening 100 for exposing the source / drain structure 2; and removing the remaining photolithography layer.
[0063] S5. Remove the patterned upper mask layer 73 to form an intermediate.
[0064] refer to Figure 7Specifically, the patterned upper mask layer 73 is removed by wet chemical cleaning. The thickness of the upper mask layer 73 is greater than or equal to 30 nm, so as to play an effective blocking role during the formation of the contact opening 100 of the exposed source / drain structure 2.
[0065] S6. A barrier structure 7b is formed above the interlayer dielectric layer 6 corresponding to the spacing region between adjacent gate stacks.
[0066] This step includes: depositing a patterned photolithography layer over the interlayer dielectric layer 6 and the patterned mask layer 7a; etching the patterned mask layer according to the patterned photolithography layer to form a barrier structure 7b correspondingly above the adjacent gate stack spacing region; and removing the remaining photolithography layer.
[0067] During this process, the blocking structure 7b can be formed to a predetermined size through a lateral dimension adjustment process. The lateral dimension adjustment may include the dimension adjustment of the patterned photolithography layer and / or the dimension adjustment of the patterned mask layer.
[0068] More specifically, see reference Figure 8 Step S6 may include the following sub-steps to perform lateral adjustment of the patterned photolithography layer size:
[0069] S611. A lower photolithography layer, an intermediate photolithography layer, and an upper photolithography layer are deposited sequentially to form three photolithography layers. The upper photolithography layer is patterned by exposure (the pattern is required to be able to etch the patterned mask layer 7a into the shape corresponding to the blocking structure 7b designed in this invention). The intermediate photolithography layer is etched according to the patterned upper photolithography layer to make the intermediate photolithography layer patterned.
[0070] S612. Adjust the lateral dimensions of the patterned intermediate photolithography layer by lateral etching;
[0071] S613. Based on the patterned intermediate photolithography layer after size adjustment, etch the lower photolithography layer to make the lower photolithography layer patterned;
[0072] S614. Etch the remaining mask layer 7a according to the patterned lower photolithography layer to form a barrier structure 7b;
[0073] S615, Remove the remaining photolithography layer.
[0074] More specifically, see reference Figure 8 Step S6 may also include the following sub-steps to perform lateral adjustment of the patterned mask layer size:
[0075] S621. A patterned photolithography layer is deposited above the interlayer dielectric layer 6 and the patterned mask layer 7a;
[0076] S622. Etch a patterned mask layer 7a along the depth direction of the device based on the patterned photolithography layer to expose the interlayer dielectric layer;
[0077] S623. Laterally etch the remaining patterned mask layer 7a to adjust its lateral dimensions in order to form a blocking structure 7b;
[0078] S624. Remove the remaining photolithography layer.
[0079] The reason for the size adjustment is that, as device dimensions shrink, the critical size of the barrier structure designed in this invention may be much smaller than the critical sizes of photolithography and etching. For example, the critical size of photolithography is generally greater than or equal to 52 nm, and the critical size of etching is generally greater than or equal to 32 nm. That is, the minimum size of the photolithography layer after patterning can only reach 52 nm, so it can be adjusted by lateral etching of the intermediate photolithography layer; while the minimum size of the mask layer after etching patterning can only reach 32 nm, so it can also be adjusted by lateral etching of the mask layer. Preferredly, adjustment is first made by lateral etching of the intermediate photolithography layer. If the desired result is not achieved, further adjustment is made by lateral etching of the mask layer.
[0080] It should be noted that unless otherwise specified as lateral etching, all etching mentioned in this article refers to depth etching.
[0081] In this step, the formed barrier structure 7b is a multilayer structure, including a first barrier layer abutting the interlayer dielectric layer and a second barrier layer disposed above the first barrier layer. The first barrier layer is formed by multiple patterned etchings of the lower mask layer 71; the second barrier layer is formed by multiple patterned etchings of the intermediate mask layer 72.
[0082] S7. Etch the interlayer dielectric layer 6 according to the barrier structure 7b to form a contact opening 200 that exposes the gate stack and remove the barrier structure 7b.
[0083] Preferably, the cover layer 4 and the first barrier layer are made of the same material, and the interlayer dielectric layer 6 and the second barrier layer are made of the same material.
[0084] refer to Figure 9 , 10 , Figure 10 It's a bird's-eye view. Figure 9 Figure (a) in the text is Figure 10 The AA section view of Figure (a) in the figure. Figure 9 Figure (b) is Figure 10In the AA cross-sectional view of Figure (b), this step specifically includes: depositing a patterned photolithography layer over the barrier structure 7b and the interlayer dielectric layer 6; etching the interlayer dielectric layer 6 according to the patterned photolithography layer. Since the interlayer dielectric layer 6 and the second barrier layer are made of the same material, the second barrier layer is removed while etching the interlayer dielectric layer 6; after exposing the capping layer 4, continue etching to remove the capping layer 4 to form the contact opening 200 for exposing the gate. Since the capping layer 4 and the first barrier layer are made of the same material, the first barrier layer is removed while etching the capping layer 4; and removing the remaining photolithography layer. It is understood that in other embodiments, if the second barrier layer and the interlayer dielectric layer 6 are made of different materials, and the second barrier layer is not removed simultaneously when etching the interlayer dielectric layer 6, the second barrier layer can be removed separately after etching the interlayer dielectric layer 6. Similarly, if the first barrier layer and the capping layer 4 are made of different materials, and the first barrier layer is not removed simultaneously when etching the capping layer 4, the first barrier layer can be removed separately after etching the capping layer 4.
[0085] The thickness of the first barrier layer is set to be greater than or equal to 30 nm, and / or the thickness difference between the first barrier layer and the capping layer 4 is less than or equal to 5 nm, so that the first barrier layer can be removed simultaneously when the capping layer 4 is removed. The thickness of the second barrier layer is set to be greater than or equal to 5 nm, which can be designed according to the thickness of the first barrier layer, and serves to protect the first barrier layer.
[0086] In this process, by forming the barrier structure 7b in the previous step, the opening size of the photolithographic layer in the direction perpendicular to the extension direction of the gate stack can be close to the width of the adjacent gate and its spacing region in that direction. (Refer to...) Figure 2 Figure (a) and Figure 9 As shown in Figure (a), compared to existing solutions, this invention significantly increases the aperture size of the photolithography layer, reducing the difficulty of photolithography. Furthermore, the protective effect of the barrier structure allows for precise positioning of the contact opening above the gate stack, increasing the load area of the contact unit and the gate stack. In addition, the barrier structure formed by the patterned mask layer design allows for controllable adjustment of the contact opening spacing, resulting in a contact unit and gate with a larger load-bearing space.
[0087] In this embodiment, the blocking structure 7b is a rectangular pillar. The two sides of the rectangular pillar, extending in the same direction as the gate 3, are nearly perpendicular to the horizontal plane of the device, or the two sides are vertical planes or non-curved planes. (Reference) Figure 10 Because of the presence of the rectangular column, the side surface B of the final contact opening is non-curved.
[0088] S8. Fill the contact opening with material to form contact units 100a and 200a.
[0089] refer to Figure 11 The contact openings 100 and 200 formed in steps S5 and S7 are filled with material to form contact units 100a and 200a.
[0090] Example 2
[0091] The difference between Example 2 and Example 1 is that the mask layer is a single-layer structure, which leads to adjustments in some processes. Specifically, the preparation method of this example includes:
[0092] S1. Provide a substrate;
[0093] S2. A single-layer mask layer is deposited on top of the interlayer dielectric layer 6 of the substrate;
[0094] S3. Pattern the mask layer to expose the area on the interlayer dielectric layer 6 corresponding to the contact unit of the pre-formed source / drain structure 2;
[0095] S4. A contact opening 100 is formed on the interlayer dielectric layer 6 to expose the source / drain structure 2, thus forming an intermediate.
[0096] S5. A barrier structure 7c is formed above the interlayer dielectric layer 6 corresponding to the spacing region between adjacent gate stacks. Similarly, the barrier structure 7c here is obtained by etching a patterned mask layer, as shown in a part of the embodiment. In this step, the barrier structure 7c formed is a single-layer structure, which is formed by multiple patterned etchings of the single-layer mask layer in step S2.
[0097] S6. Etch the interlayer dielectric layer 6 according to the barrier structure 7c to form a contact opening 200 that exposes the gate stack and remove the barrier structure 7c.
[0098] Reference Figure 12 This step differs significantly from Embodiment 1. Specifically, this step includes: depositing a patterned photolithography layer above the barrier structure 7c and the interlayer dielectric layer 6, wherein the opening of the patterned photolithography layer corresponds to the area of the contact unit for pre-forming the gate structure; etching the interlayer dielectric layer 6 according to the patterned photolithography layer to expose part of the cover layer 4; removing the remaining photolithography layer; removing the barrier structure 7c; and continuing to etch to remove the cover layer 4 to form the contact opening 200 for exposing the gate.
[0099] In this process, the etching of the interlayer dielectric layer 6 is usually done using dry etching, while the removal of the barrier structure 7c is done using wet etching, which requires transfer to another reaction chamber. Because the etching characteristics of the material of the barrier structure 7c are similar to those of the metal material of the gate 3, when using Embodiment 2, the barrier structure 7c needs to be removed first and then the capping layer 4 needs to be removed, making it impossible to form a contact opening in one step within the same etching chamber.
[0100] In Embodiment 2, a single-layer mask layer structure is used, directly borrowing the mask layer from existing solutions to form the barrier structure 7c, without the need to add other mask layers. In other words, this embodiment directly borrows the mask layer from step S2. On the one hand, during the formation of the contact openings exposing the source / drain structure, the patterned mask layer covers part of the interlayer dielectric layer 6 to protect the area where the contact unit 200a to the gate 3 is to be formed; on the other hand, it serves as the barrier structure 7c during the formation of the contact openings exposing the gate. The thickness of the barrier structure 7c is set to be greater than or equal to 45 nm to meet the masking function when forming the contact openings to the source / drain structure 2, while also meeting the requirements for the subsequent formation of the barrier structure.
[0101] S7. Fill the contact opening with material to form a contact unit.
[0102] Furthermore, the present invention also provides a semiconductor device comprising a semiconductor device manufactured according to an exemplary embodiment of the present invention.
[0103] In summary, the semiconductor device and its fabrication method of the present invention have the following beneficial effects: The present invention forms a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks. Subsequently, contact openings exposing the gate stacks are formed on the interlayer dielectric layer, and the barrier structure is removed. The presence of the barrier structure prevents communication between adjacent contact units. Furthermore, the barrier structure of the present invention is formed by etching a mask layer. The lateral dimension of the formation process can be flexibly adjusted, and the opening size of the upper photolithography layer can be close to the width of adjacent gates and their spacing regions in that direction. Compared with existing solutions, this increases the opening size of the photolithography layer, reduces photolithography difficulty, and, through the protective effect of the barrier structure, accurately positions the contact openings above the gate stacks, increasing the load area of the contact units and gate stacks. In addition, the present invention can controllably adjust the spacing of the contact openings through the design of a patterned mask layer, thereby creating contact units and gates with greater load-bearing space.
[0104] The terms “equal,” “identical,” “simultaneous,” or other similar expressions, not limited to absolute equality or identity in mathematical terms, can refer to similarity in an engineering sense or within an acceptable error range when implementing the rights described in this patent.
[0105] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method includes: An intermediate is provided, the intermediate including a substrate, an interlayer dielectric layer and a patterned mask layer located on the interlayer dielectric layer, a source / drain structure and a plurality of spaced-apart gate stacks are formed over the substrate, and the interlayer dielectric layer is formed over the substrate and covers the source / drain structure and the gate stacks; A barrier structure is formed above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks by etching the patterned mask layer; A patterned photolithography layer is deposited over the barrier structure and the interlayer dielectric layer, and the interlayer dielectric layer is etched according to the photolithography layer to form contact openings that expose the gate stack and remove the barrier structure. Material is filled into the contact opening to form a contact unit.
2. The method according to claim 1, characterized in that, The patterned mask layer exposes the area on the interlayer dielectric layer corresponding to the contact unit of the pre-formed source / drain structure and covers the area on the interlayer dielectric layer corresponding to the contact unit of the pre-formed gate stack. The formation of a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks includes: depositing a patterned photolithography layer above the interlayer dielectric layer and the patterned mask layer; A patterned mask layer is etched based on a patterned photolithography layer to form a barrier structure above the corresponding spacing region of adjacent gate stacks; the remaining photolithography layer is then removed.
3. The method according to claim 2, characterized in that, The sidewall of the barrier structure, which extends in the same direction as the gate stack, is a non-curved plane.
4. The method according to claim 2, characterized in that, The process of etching a patterned mask layer based on a patterned photolithography layer to form a barrier structure above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks specifically includes: A lower photolithography layer, an intermediate photolithography layer, and an upper photolithography layer are deposited sequentially to form three photolithography layers. The upper photolithography layer is patterned by exposure, and the intermediate photolithography layer is etched according to the patterned upper photolithography layer to pattern the intermediate photolithography layer. The lateral dimensions of the patterned intermediate photolithography layer are adjusted by lateral etching. Based on the patterned intermediate photolithography layer after size adjustment, the lower photolithography layer is etched to make the lower photolithography layer patterned; The patterned mask layer is etched according to the patterned lower photolithography layer to form a barrier structure; Remove the remaining photolithography layer.
5. The method according to claim 2, characterized in that, The method of etching a patterned mask layer based on a patterned photolithography layer to form a barrier structure correspondingly above the spacing region of adjacent gate stacks includes: A patterned mask layer is etched along the depth direction of the device based on the patterned photolithography layer to expose the interlayer dielectric layer; The remaining patterned mask layer is laterally etched to adjust its lateral dimensions in order to form a barrier structure.
6. The method according to claim 1, characterized in that, The gate stack includes a gate and a capping layer deposited over the gate; the barrier structure includes a first barrier layer abutting the interlayer dielectric layer; The first barrier layer and the cover layer are made of the same material; and / or, the thickness of the first barrier layer is set to be greater than or equal to 30 nm; and / or, the thickness difference between the first barrier layer and the cover layer is less than or equal to 5 nm.
7. The method according to claim 1, characterized in that, The barrier structure includes a first barrier layer that abuts against the interlayer medium layer and a second barrier layer disposed above the first barrier layer; The second barrier layer and the interlayer dielectric layer are made of the same material; and / or, the thickness of the second barrier layer is set to be greater than or equal to 5 nm.
8. The method according to any one of claims 1 and 6-7, characterized in that, The gate stack includes a gate and a capping layer deposited on the gate; the barrier structure includes a first barrier layer abutting the interlayer dielectric layer and a second barrier layer disposed on the first barrier layer; The method of depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer, and etching the interlayer dielectric layer according to the photolithography layer to form a contact opening for exposing the gate stack and removing the barrier structure includes: depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer; etching the interlayer dielectric layer according to the patterned photolithography layer; continuing to etch and remove the capping layer after exposing the capping layer to form a contact opening for exposing the gate; and removing the remaining photolithography layer. Wherein, the second barrier layer is removed while the interlayer dielectric layer is being etched; and / or, the first barrier layer is removed while the cover layer is being etched away.
9. The method according to claim 1, characterized in that, The barrier structure is a single-layer structure, and the thickness of the barrier structure is greater than or equal to 45 nm.
10. The method according to claim 1 or 9, characterized in that, The gate stack includes a gate and a capping layer deposited on the gate; the barrier structure is a single-layer structure. The method of depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer, and etching the interlayer dielectric layer according to the photolithography layer to form a contact opening for exposing the gate stack and removing the barrier structure includes: depositing a patterned photolithography layer over the barrier structure and the interlayer dielectric layer; etching the interlayer dielectric layer according to the patterned photolithography layer to expose a portion of the capping layer; removing the remaining photolithography layer; removing the barrier structure; and continuing to etch to remove the capping layer to form a contact opening for exposing the gate.
11. A semiconductor device, characterized in that, It is prepared by the method according to any one of claims 1-10.
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