A time delay device
By designing the delay circuit and control circuit of the delay device, the individual delay of the rising edge or falling edge of the square wave signal is realized, which solves the problem that the existing technology cannot delay independently and is suitable for application scenarios that require individual delay.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- EPIC MEMS XIAMEN CO LTD
- Filing Date
- 2021-08-25
- Publication Date
- 2026-07-14
AI Technical Summary
Existing circuits cannot delay the rising or falling edge of a square wave signal individually, thus failing to meet the individual delay requirements of certain devices.
Design a delay device comprising a delay circuit and a control circuit, capable of identifying the rising or falling edge of a signal and delaying it individually according to instructions, and outputting a high or low level by delaying for a preset time through the delay circuit.
It implements the function of delaying the rising edge or falling edge separately, which is suitable for scenarios that require delaying the rising edge or falling edge separately.
Smart Images
Figure CN115733469B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics, and in particular to a time delay device. Background Technology
[0002] Many devices or modules in the prior art use square wave signals as control signals. However, some devices may need to use delayed square wave signals for control. The circuits in the prior art can only delay the entire square wave signal, that is, delay the rising edge and falling edge of the square wave signal for the same time. This cannot be applied to scenarios where the requirement is to delay only the rising edge or the falling edge. Summary of the Invention
[0003] The purpose of this invention is to provide a delay device that can delay only the rising edge or only the falling edge, thereby applicable to scenarios where the requirement is to delay only the rising edge or the falling edge.
[0004] To solve the above-mentioned technical problems, the present invention provides a delay device, including a delay circuit and a control circuit;
[0005] One end of the delay circuit is connected to the output terminal of the signal output device and the detection terminal of the control circuit, respectively; the other end of the delay circuit is connected to the input terminal of the control circuit; and the output terminal of the control circuit is the output terminal of the delay device.
[0006] The control circuit is configured to, upon receiving a rising edge delay command and detecting a rising edge in the signal output by the signal output device, control the signal to delay for a preset time through the delay circuit to output a high level, and upon detecting a falling edge in the signal to immediately output a low level; upon receiving a falling edge delay command and detecting a falling edge in the signal, control the signal to delay for the preset time through the delay circuit to output a low level, and upon detecting a rising edge in the signal to immediately output a high level.
[0007] Preferably, the delay circuit includes a first delay circuit and a second delay circuit, and the control circuit includes a first control circuit and a second control circuit;
[0008] The first terminal of the first delay circuit is connected to one terminal of the signal output device, the first terminal of the second delay circuit, the detection terminal of the first control circuit, and the detection terminal of the second control circuit, respectively. The second terminal of the first delay circuit is connected to the input terminal of the first control circuit, and the second terminal of the second delay circuit is connected to the input terminal of the second control circuit.
[0009] The first control circuit is configured to, upon receiving the rising edge delay instruction and detecting the rising edge in the signal output by the signal output device, control the signal to be delayed by the first delay circuit for a first preset time to output a high level, and upon detecting the falling edge in the signal, immediately output a low level.
[0010] The second control circuit is used to control the signal to delay for the preset time and output a low level when it receives the falling edge delay instruction and detects the falling edge in the signal, and to immediately output a high level when it detects the rising edge in the signal.
[0011] Preferably, the first control circuit is a first flip-flop, and the second control circuit is a second flip-flop;
[0012] The input terminal of the i-th flip-flop is the input terminal of the i-th control circuit, the control terminal of the i-th flip-flop is the detection terminal of the i-th control circuit, and the output terminal of the i-th flip-flop is the output terminal of the i-th control circuit, where i is 1 or 2;
[0013] The first trigger is configured to start working when the rising edge delay instruction is received, and after detecting the rising edge of the signal, output a high level after the first preset time of delay by the first delay circuit, and output a low level immediately when the falling edge of the signal is detected.
[0014] The second flip-flop is configured to start working when the falling edge delay instruction is received, and after detecting the falling edge of the signal, output a low level after the second preset time of the second delay circuit delay, and output a high level immediately when the rising edge of the signal is detected.
[0015] Preferably, the first trigger is a D trigger;
[0016] The D pin of the D flip-flop is set to 1, the first reset pin of the D flip-flop is the control terminal of the first flip-flop, the CP pin of the D flip-flop is the input terminal of the first flip-flop, and the Q pin of the D flip-flop is the output terminal of the first flip-flop.
[0017] Preferably, the second flip-flop is a D flip-flop;
[0018] The D pin of the D flip-flop is set to 1, the second reset pin of the D flip-flop is the control terminal of the second flip-flop, and the CP pin of the D flip-flop is the input terminal of the first flip-flop. The pin is the output terminal of the second flip-flop.
[0019] Preferably, the first delay circuit includes a first capacitor and a first resistor, and the second delay circuit includes a second capacitor and a second resistor;
[0020] The first terminal of the i-th capacitor is the first terminal of the i-th delay circuit, the second terminal of the i-th capacitor is connected to the first terminal of the i-th resistor and serves as the second terminal of the i-th delay circuit, and the second terminal of the i-th resistor is grounded.
[0021] The i-th preset time is the charging time of the i-th capacitor, where i is 1 or 2.
[0022] This application provides a delay device, including a delay circuit and a control circuit. The control circuit detects the rising and falling edges of the signal output by the signal output device. When only the rising edge needs to be delayed, the delay circuit delays for a preset time before outputting a high level. That is, the rising edge is output only after a preset time following the signal's rising edge, thus achieving a delay on the rising edge. The falling edge is not processed and is output directly, thus achieving a delay only on the rising edge. Similarly, when only the falling edge needs to be delayed, the delay circuit delays for a preset time before outputting a low level. That is, the falling edge is output only after a preset time following the signal's falling edge, thus achieving a delay on the falling edge. The rising edge is not processed and is output directly, thus achieving a delay only on the falling edge. Therefore, this application can achieve delay only on the rising edge or only on the falling edge, thus applicable to scenarios where the requirement is to delay only the rising or falling edge. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 A structural block diagram of a delay device provided by the present invention;
[0025] Figure 2 A schematic diagram illustrating a specific implementation of the first delay device provided by the present invention;
[0026] Figure 3 This is a schematic diagram illustrating a specific implementation of the second delay device provided by the present invention. Detailed Implementation
[0027] The core of this invention is to provide a delay device that can delay only the rising edge or only the falling edge, thereby applicable to scenarios where the requirement is to delay only the rising edge or the falling edge.
[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0029] Please refer to Figure 1 , Figure 1 A structural block diagram of a delay device provided by the present invention includes a delay circuit and a control circuit.
[0030] One end of the delay circuit 12 is connected to the output terminal of the signal output device and the detection terminal of the control circuit 13, respectively. The other end of the delay circuit 12 is connected to the input terminal of the control circuit 13, and the output terminal of the control circuit 13 is the output terminal of the delay device.
[0031] The control circuit 13 is configured to, upon receiving a rising edge delay command and detecting a rising edge in the signal output by the signal output device, delay the control signal through the delay circuit 12 for a preset time to output a high level, and upon detecting a falling edge in the signal, immediately output a low level; upon receiving a falling edge delay command and detecting a falling edge in the signal, delay the control signal through the delay circuit 12 for a preset time to output a low level, and upon detecting a rising edge in the signal, immediately output a high level.
[0032] Considering that the delay circuit 12 in the existing technology can only delay the rising edge and falling edge of the square wave signal at the same time, it cannot be applied to scenarios where the requirement is to delay only the rising edge or the falling edge.
[0033] To solve the above-mentioned technical problems, the design concept of this application is as follows: design a delay device that can identify the rising edge and falling edge of the signal output by the signal output device, and delay the rising edge or falling edge separately according to the user's instructions.
[0034] Based on this, the delay device in this application includes a delay circuit 12 and a control circuit 13. The control circuit 13 is used to identify the rising or falling edge of the signal output by the signal output device according to the user instruction (rising edge delay instruction or falling edge delay instruction), and perform a delay according to the edge corresponding to the corresponding delay instruction. Specifically, according to the rising edge delay instruction, when a rising edge is detected, the delay circuit 12 delays for a preset time to output a high level, and for a falling edge, it immediately outputs a low level; according to the falling edge delay instruction, when a falling edge is detected, the delay circuit 12 delays for a preset time to output a low level, and for a rising edge, it immediately outputs a high level.
[0035] It should be noted that the delay circuit 12 in this application may be, but is not limited to, an RC circuit, and the control circuit 13 may be, but is not limited to, a D flip-flop.
[0036] As can be seen, when the delay device includes a delay circuit 12 and a control circuit 13, it can realize the function of delaying only the rising edge or only the falling edge, thus it can be applied to scenarios where the requirement is to delay only the rising edge or only the falling edge.
[0037] Based on the above embodiments:
[0038] In a preferred embodiment, the delay circuit 12 includes a first delay circuit 22 and a second delay circuit 32, and the control circuit 13 includes a first control circuit 23 and a second control circuit 33.
[0039] The first terminal of the first delay circuit 22 is connected to one terminal of the signal output device, the first terminal of the second delay circuit 32, the detection terminal of the first control circuit 23, and the detection terminal of the second control circuit 33, respectively. The second terminal of the first delay circuit 22 is connected to the input terminal of the first control circuit 23, and the second terminal of the second delay circuit 32 is connected to the input terminal of the second control circuit 33.
[0040] The first control circuit 23 is used to control the signal to delay for a first preset time and output a high level when it receives a rising edge delay command and detects a rising edge in the signal output by the signal output device, and to immediately output a low level when it detects a falling edge in the signal.
[0041] The second control circuit 33 is used to output a low level after delaying the control signal for a preset time through the delay circuit 12 when a falling edge delay instruction is received and a falling edge in the signal is detected, and to output a high level immediately when a rising edge in the signal is detected.
[0042] This embodiment aims to provide a specific implementation of a delay device. Specifically, the delay device is divided into two parts: a first delay circuit 22 and a first control circuit 23 are corresponding circuits that separately delay the rising edge; a second delay circuit 32 and a second control circuit 33 are circuits that separately delay the falling edge. Specifically, when the first control module receives a rising edge delay command and detects a rising edge, it delays for a preset time through the first delay circuit 22 and outputs a high level; upon detecting a falling edge, it immediately outputs a low level. When the second control module receives a falling edge delay command and detects a falling edge, it delays for a preset time through the second delay circuit 32 and outputs a low level; upon detecting a rising edge, it immediately outputs a high level.
[0043] In one preferred embodiment, the first delay circuit 22 includes a first capacitor and a first resistor, and the second delay circuit 32 includes a second capacitor and a second resistor.
[0044] The first terminal of the i-th capacitor is the first terminal of the i-th delay circuit 12, the second terminal of the i-th capacitor is connected to the first terminal of the i-th resistor and serves as the second terminal of the i-th delay circuit 12, and the second terminal of the i-th resistor is grounded.
[0045] The preset time for the i-th capacitor is the charging time for the i-th capacitor, where i is 1 or 2.
[0046] Both the first delay circuit 22 and the second delay circuit 32 can be RC circuits. The first control circuit 23 and the second control circuit 33 can be, but are not limited to, flip-flops, specifically, but are not limited to, D flip-flops.
[0047] As can be seen, this embodiment can achieve the functions of the delay circuit 12 and the control circuit 13 in the above embodiments, and the implementation method is simple and reliable.
[0048] In a preferred embodiment, the first control circuit 23 is a first flip-flop, and the second control circuit 33 is a second flip-flop;
[0049] The input terminal of the i-th flip-flop is the input terminal of the i-th control circuit 13, the control terminal of the i-th flip-flop is the detection terminal of the i-th control circuit 13, and the output terminal of the i-th flip-flop is the output terminal of the i-th control circuit 13, where i is 1 or 2.
[0050] The first flip-flop is used to start working when a rising edge delay instruction is received, and after the rising edge of the signal is detected, it outputs a high level after a first preset time of delay by the first delay circuit 22, and immediately outputs a low level when the falling edge of the signal is detected.
[0051] The second flip-flop is used to start working when a falling edge delay instruction is received, and after the falling edge of the signal is detected, it outputs a low level after a second preset time of delay by the second delay circuit 32, and outputs a high level immediately when the rising edge of the signal is detected.
[0052] This embodiment aims to provide a specific implementation of the first control circuit 23 and the second control circuit 33. When the circuit is a flip-flop, the rising edge delay instruction can be, but is not limited to, an instruction to control the first flip-flop to work normally, and the falling edge delay instruction can be, but is not limited to, an instruction to control the second flip-flop to work normally.
[0053] In this embodiment, the trigger may be, but is not limited to, a D trigger, or other edge-triggered triggers, as long as they can achieve the corresponding function. This application does not impose any special limitations on them.
[0054] In summary, when the first control circuit 23 and the second control circuit 33 are flip-flops, the corresponding functions can be achieved, and the implementation using flip-flops is simple and reliable.
[0055] In a preferred embodiment, the first flip-flop is a D flip-flop;
[0056] When the D pin of a D flip-flop is set to 1, the first reset pin of the D flip-flop is the control terminal of the first flip-flop, the CP pin of the D flip-flop is the input terminal of the first flip-flop, and the Q pin of the D flip-flop is the output terminal of the first flip-flop.
[0057] Specifically, please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating a specific implementation of the first delay device provided by the present invention. When the first delay circuit 22 is an RC circuit and the first flip-flop is a D flip-flop, through... Figure 2 In the connection method described, when the signal output from the signal output device is 0, the corresponding D flip-flop is reset, and the Q pin of the D flip-flop outputs a 0 signal. When the signal output from the signal output device changes from 0 to 1 (i.e., when a rising edge is detected), the signal reaches the CP pin of the D flip-flop after a preset delay by the RC circuit. At this time, the Q pin of the corresponding D flip-flop changes from 0 to 1, realizing the toggle function. That is, at this time, the Q pin outputs a 1 signal, thus achieving the rising edge delay. When the signal output from the signal output device changes from 1 to 0 (i.e., when a falling edge is detected), the signal passes through the first reset terminal (…). Figure 2 In The pin makes the signal output of the Q pin of the D flip-flop become 0, that is, it immediately outputs a low level, and correspondingly, there is no delay effect on the falling edge.
[0058] It should be noted that the capacitance of the capacitor in the RC circuit is positively correlated with the preset time, and the preset time can be adjusted by adjusting the parameters of the RC circuit.
[0059] In summary, when the first delay circuit 22 in this application is an RC circuit and the first control circuit 23 is a D flip-flop, it is possible to achieve a delay only for the rising edge, and the implementation method is simple and reliable.
[0060] In a preferred embodiment, the second flip-flop is a D flip-flop;
[0061] When the D pin of a D flip-flop is set to 1, the second reset pin of the D flip-flop is the control terminal of the second flip-flop, and the CP pin of the D flip-flop is the input terminal of the first flip-flop. The pin is the output of the second flip-flop.
[0062] Specifically, please refer to Figure 3 , Figure 3This is a schematic diagram illustrating a specific implementation of the second delay device provided by the present invention. When the second delay circuit 32 is an RC circuit and the second flip-flop is a D flip-flop, [the device]... Figure 3 In the connection method described, when the signal output device outputs a 1, the corresponding D flip-flop is reset, and the Q pin of the D flip-flop outputs a 0 signal. The pin outputs a 1 signal, and the D flip-flop... The pin is the output terminal of the second control circuit 33; when the signal output by the signal output device changes from 1 to 0 (that is, when a falling edge is detected), the signal reaches the CP pin of the D flip-flop after a preset time delay by the RC circuit. At this time, the corresponding D flip-flop... The pin switches from 1 to 0 to achieve the toggle function, that is, at this time... The pin output signal is 1, thus achieving a delay on the falling edge. When the signal output device detects a change from 0 to 1 (i.e., when a rising edge is detected), the signal passes through the second reset terminal ( Figure 3 The R pin in the circuit is used to reset the D flip-flop. At this time, the Q pin of the D flip-flop outputs 0. When the signal output from the pin becomes 1, that is, a high level is output immediately, and there is no delay effect on the rising edge.
[0063] It should be noted that the capacitance of the capacitor in the RC circuit is positively correlated with the preset time, and the preset time can be adjusted by adjusting the parameters of the RC circuit.
[0064] In summary, when the second delay circuit 32 in this application is an RC circuit and the second control circuit 33 is a D flip-flop, it is possible to achieve a delay only for the falling edge, and the implementation method is simple and reliable.
[0065] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0066] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0067] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A time delay device, characterized in that, Includes delay circuits and control circuits; One end of the delay circuit is connected to the output terminal of the signal output device and the detection terminal of the control circuit, respectively; the other end of the delay circuit is connected to the input terminal of the control circuit; and the output terminal of the control circuit is the output terminal of the delay device. The control circuit is configured to, upon receiving a rising edge delay command and detecting a rising edge in the signal output by the signal output device, control the signal to delay for a preset time through the delay circuit to output a high level, and upon detecting a falling edge in the signal to immediately output a low level; upon receiving a falling edge delay command and detecting a falling edge in the signal, control the signal to delay for the preset time through the delay circuit to output a low level, and upon detecting a rising edge in the signal to immediately output a high level.
2. The delay device as described in claim 1, characterized in that, The delay circuit includes a first delay circuit and a second delay circuit, and the control circuit includes a first control circuit and a second control circuit; The first terminal of the first delay circuit is connected to one terminal of the signal output device, the first terminal of the second delay circuit, the detection terminal of the first control circuit, and the detection terminal of the second control circuit, respectively. The second terminal of the first delay circuit is connected to the input terminal of the first control circuit, and the second terminal of the second delay circuit is connected to the input terminal of the second control circuit. The first control circuit is configured to, upon receiving the rising edge delay instruction and detecting the rising edge in the signal output by the signal output device, control the signal to be delayed by the first delay circuit for a first preset time to output a high level, and upon detecting the falling edge in the signal, immediately output a low level. The second control circuit is used to control the signal to delay for a second preset time to output a low level when it receives the falling edge delay command and detects the falling edge in the signal, and to immediately output a high level when it detects the rising edge in the signal.
3. The delay device as described in claim 2, characterized in that, The first control circuit is a first flip-flop, and the second control circuit is a second flip-flop; The input terminal of the i-th flip-flop is the input terminal of the i-th control circuit, the control terminal of the i-th flip-flop is the detection terminal of the i-th control circuit, and the output terminal of the i-th flip-flop is the output terminal of the i-th control circuit, where i is 1 or 2; The first trigger is configured to start working when the rising edge delay instruction is received, and after detecting the rising edge of the signal, output a high level after the first preset time of delay by the first delay circuit, and output a low level immediately when the falling edge of the signal is detected. The second flip-flop is configured to start working when the falling edge delay instruction is received, and after detecting the falling edge of the signal, output a low level after the second preset time of the second delay circuit delay, and output a high level immediately when the rising edge of the signal is detected.
4. The delay device as described in claim 3, characterized in that, The first trigger is a D trigger; The D pin of the D flip-flop is set to 1, the first reset pin of the D flip-flop is the control terminal of the first flip-flop, the CP pin of the D flip-flop is the input terminal of the first flip-flop, and the Q pin of the D flip-flop is the output terminal of the first flip-flop.
5. The delay device as described in claim 3, characterized in that, The second flip-flop is a D flip-flop; The D pin of the D flip-flop is set to 1, the second reset pin of the D flip-flop is the control terminal of the second flip-flop, and the CP pin of the D flip-flop is the input terminal of the first flip-flop. The pin is the output terminal of the second flip-flop.
6. The delay device according to any one of claims 2-5, characterized in that, The first delay circuit includes a first capacitor and a first resistor, and the second delay circuit includes a second capacitor and a second resistor; The first terminal of the i-th capacitor is the first terminal of the i-th delay circuit, the second terminal of the i-th capacitor is connected to the first terminal of the i-th resistor and serves as the second terminal of the i-th delay circuit, and the second terminal of the i-th resistor is grounded. The i-th preset time is the charging time of the i-th capacitor, where i is 1 or 2.