Charge pump type clock management circuit and its dual-core analog-to-digital converter

Abstract

The application relates to a charge pump type clock management circuit and a dual-core analog-digital converter thereof, the clock management circuit comprising a pulse generation circuit, a first phase-locked loop, a second phase-locked loop and a phase operation circuit connected in sequence, the first phase-locked loop and the second phase-locked loop each comprising a delay circuit, a phase detector and a charge pump connected in sequence, the output end of the charge pump being connected with the input end of the delay circuit, the input end of the delay circuit of the first phase-locked loop being connected with the pulse generation circuit, and the output end of the phase detector of the first phase-locked loop being connected with the input ends of the delay circuit and the phase detector of the second phase-locked loop respectively. The dual-core analog-digital converter comprises a first core module and a second core module. The application improves the design of the charge pump type phase-locked loop, constructs two closed loop type charge pump phase-locked loops, and improves the performance of the charge pump, so as to reduce the clock jitter of the clock management circuit and improve the performance of the analog-digital converter under a wide voltage.

Description

Technical Field

[0001] This invention relates to a charge pump clock management circuit and a dual-core analog-to-digital converter using the aforementioned charge pump clock management circuit, belonging to the field of analog-to-digital conversion technology. Background Technology

[0002] With the booming development of the integrated circuit industry, the manufacturing process of integrated circuits is constantly improving. Analog-to-digital converters (ADCs), as commonly used analog devices, are widely used in various types of electronic devices. How to achieve good performance of ADCs under wide voltage input conditions is a common research goal for scholars both domestically and internationally.

[0003] Because analog-to-digital converters (ADCs) require clock management circuits to provide non-overlapping clocks, their accuracy is affected by the performance of these clock management circuits. To achieve high-speed, high-precision ADCs, the clock management circuits need to maintain low jitter over a wide input range. While charge pump phase-locked loops (PLLs) used in clock management circuits have the advantage of a wide capture range, traditional charge pumps suffer from non-ideal effects such as charge leakage, current mismatch, and charge sharing, which directly affect the performance of the PLL and lead to output jitter in the clock management circuit. Summary of the Invention

[0004] This invention provides a charge pump type clock management circuit and its dual-core analog-to-digital converter, aiming to solve at least one of the technical problems existing in the prior art.

[0005] The present invention relates to a clock management circuit, comprising a pulse generation circuit, a first phase-locked loop (PLL), a second PLL, and a phase operation circuit connected in sequence. Both the first and second PLLs include a delay circuit, a phase detector, and a charge pump connected in sequence. The output of the pulse generation circuit is connected to the input of the delay circuit, and the output of the pulse generation circuit is connected to the input of the phase detector of the first PLL. The output of the charge pump is connected to the input of the delay circuit. Specifically, the input of the delay circuit of the first PLL is connected to the pulse generation circuit; the output of the phase detector of the first PLL is connected to both the delay circuit and the phase detector of the second PLL; the output of the delay circuit of the second PLL is connected to the input of the phase operation circuit; and the phase operation circuit outputs a clock signal.

[0006] Furthermore, the charge pump includes a charge pump core circuit; the charge pump core circuit includes a common-gate common-source charging current source and a common-gate common-source discharging current source, the charging current source being connected to a common-source PMOS transistor M1; the discharging current source being connected to a common-source NMOS transistor M6; the common-source PMOS transistor M1 and the common-source NMOS transistor M6 are controlled by the output signal of the phase detector.

[0007] Furthermore, the charge pump also includes a bias circuit for providing bias to the charge pump core circuitry; the bias circuit is connected to the gate of the charging current source through a first transmission gate control circuit, and the bias circuit is connected to the gate of the discharging current source through a second transmission gate control circuit.

[0008] Furthermore, the discharge current source and the discharge boosting circuit form a discharge negative feedback loop; the charging current source and the charging boosting circuit form a charging negative feedback loop.

[0009] Furthermore, the impedance R1 of the charging current source is calculated as follows:

[0010] R1≈g m8 {r 026 ||[g m9 r 09 (r 08 ||r 07 )]}(g m3 r 03 r 02 )

[0011] In the formula, g m8 For the equivalent transconductance of NMOS transistor M8, r 026 G is the channel impedance of NMOS transistor M26. m9 For the equivalent transconductance of PMOS transistor M9, r 09 r is the channel impedance of PMOS transistor M9. 08 r is the channel impedance of NMOS transistor M8. 07 G is the channel impedance of NMOS transistor M7. m3 For the equivalent transconductance of PMOS transistor M3, r 03 r is the channel impedance of PMOS transistor M3. 02 The channel impedance of PMOS transistor M2;

[0012] The impedance R2 of the discharge current source is calculated as follows:

[0013] R2≈g m10 {r 028 ||[g m11 r 011 (r 010 ||r012 )]}(g m4 r 04 r 05 )

[0014] In the formula, g m10 For the equivalent transconductance of PMOS transistor M10, r 028 G is the channel impedance of the PMOS transistor M28. m11 For the equivalent transconductance of NMOS transistor M11, r 011 r is the channel impedance of NMOS transistor M11. 010 r is the channel impedance of PMOS transistor M10. 012 G is the channel impedance of NMOS transistor M12. m4 For the equivalent transconductance of NMOS transistor M4, r 04 r is the channel impedance of PMOS transistor M4. 05 This is the channel impedance of NMOS transistor M5.

[0015] Furthermore, a single-ended to complementary circuit is provided between the phase detector and the charge pump. The single-ended complementary circuit converts the single-phase clock signal output by the phase detector into two complementary clock signals. The charge pump includes an operational amplifier, two common-source PMOS transistors M1 for switching on and off the two clock signals, two common-source NMOS transistors M6 for switching on and off the two clock signals, and two switched capacitors. The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to one of the common-source PMOS transistors M1, one of the common-source NMOS transistors M6, and one switched capacitor. The output terminal of the operational amplifier is connected to another common-source PMOS transistor M1, another common-source NMOS transistor M6, and another switched capacitor.

[0016] Furthermore, the delay circuit of the first phase-locked loop includes a MOSFET M d11 MOSFET M d12 MOSFET M d13 And the first inverter, the MOS transistor M d11 and the MOS transistor M d12 The pulse generation circuit is connected in parallel with the output terminal of the MOS transistor M. d11 The source and MOS transistor M d12 The source connection, M d11 The drain terminal and MOSFET M d12 The gate terminal is connected to the input terminal of the first inverter, and the first inverter outputs a signal.

[0017] Furthermore, the delay circuit of the second phase-locked loop includes a second inverter and a MOSFET.d21 and capacitor C d2 The output terminal of the phase detector in the first phase-locked loop is connected to the input terminal of the second inverter, and the second inverter outputs a signal; the MOS transistor M d21 The gate of the MOSFET is connected to the output terminal of the second inverter. d21 The drain of the capacitor C d2 The output terminal of the charge pump of the second phase-locked loop is connected to the MOS transistor M. d21 The source connection.

[0018] Another aspect of the technical solution of the present invention relates to an analog-to-digital converter, comprising a first core module, the first core module including a first control logic circuit, the first control logic circuit including a clock management circuit according to any one of claims 1 to 8; a second core module, the second core module including a second control logic circuit, the second control logic circuit including a clock management circuit according to any one of claims 1 to 8; wherein, the input terminal of the first control logic circuit is connected to the input terminal of the second control logic circuit, and the second control logic circuit outputs the final result.

[0019] Furthermore, the first kernel module further includes a first sampling circuit, a first comparator, and a first digital-to-analog converter circuit. The output terminal of the first sampling circuit is connected to the non-inverting input terminal of the first comparator circuit, the output terminal of the first comparator circuit is connected to the input terminal of the first control logic circuit, the output terminal of the first control logic circuit is connected to the input terminal of the first digital-to-analog converter circuit, and the output terminal of the first digital-to-analog converter circuit is connected to the non-inverting input terminal of the first comparator circuit. The second kernel module further includes a second sampling circuit, a second comparator circuit, and a second digital-to-analog converter circuit. The output terminal of the second sampling circuit is connected to the inverting input terminal of the second comparator circuit, the output terminal of the second comparator circuit is connected to the input terminal of the second control logic circuit, the output terminal of the second control logic circuit is connected to the input terminal of the second digital-to-analog converter circuit, and the output terminal of the second digital-to-analog converter circuit is connected to the inverting input terminal of the second comparator circuit.

[0020] The beneficial effects of this invention are as follows.

[0021] This invention relates to a charge pump-type clock management circuit and its dual-core analog-to-digital converter (ADC). By improving the design of the charge pump phase-locked loop (PLL), two closed-loop charge pump PLLs are constructed, and the performance of the charge pump is enhanced to reduce clock jitter in the clock management circuit, enabling the ADC to maintain good performance under wide input voltage conditions. Common-source switching technology is employed to suppress charge sharing in the charge pump; a transmission gate is added between the common-source and common-gate charge / discharge current sources to suppress leakage current generated when the charge pump is turned off; a current source boosting circuit is added and forms negative feedback loops with the common-source and common-gate charge / discharge current sources to reduce the low mismatch rate of the charge pump; the PLL adopts a closed-loop structure and has two PLLs to achieve a stable and adjustable dual-phase non-overlapping clock output with a stable duty cycle, reducing output clock jitter; the ADC employs a dual-core structure to handle high-voltage and low-voltage inputs separately, addressing the wide input voltage range. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of an analog-to-digital converter according to an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the overall structure of the clock management circuit according to an embodiment of the present invention.

[0024] Figure 3(a) is a schematic diagram of the delay circuit of the first phase-locked loop according to an embodiment of the present invention.

[0025] Figure 3(b) is a schematic diagram of the delay circuit of the second phase-locked loop according to an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the internal structure of a charge pump according to an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the overall structure of a charge pump according to an embodiment of the present invention.

[0028] Figure 6 This is a simulation result diagram of an analog-to-digital converter according to an embodiment of the present invention. Detailed Implementation

[0029] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention.

[0030] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a," "described," and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from one another. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. Any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided herein are intended only to better illustrate embodiments of the invention and, unless otherwise required, do not impose a limitation on the scope of the invention.

[0032] Reference Figure 1 One aspect of the present invention provides an analog-to-digital converter (ADC) with a dual-core structure, comprising a first core module and a second core module. The first core module (ADCH) includes a first sampling circuit, a first comparator (CMPH), a first control logic circuit (CMPH), and a first digital-to-analog converter (DACH). The output of the first sampling circuit is connected to the non-inverting input (i.e., the "+" terminal in the figure) of the first comparator circuit. The output of the first comparator circuit is connected to the input of the first control logic circuit. The output of the first control logic circuit is connected to the input of the first DACH. The output of the first DACH is connected to the non-inverting input of the first comparator circuit. The second kernel module (ADCL) includes a second sampling circuit, a second comparator circuit (L), a second control logic circuit (L), and a second digital-to-analog converter circuit (DACL). The output of the second sampling circuit is connected to the inverting input (the "-" terminal in the diagram) of the second comparator circuit. The output of the second comparator circuit is connected to the input of the second control logic circuit. The output of the second control logic circuit is connected to the input of the second DACL. The output of the second DACL is connected to the inverting input of the second comparator circuit. The input of the first control logic circuit is connected to the input of the second control logic circuit, and the second control logic circuit outputs the final result.

[0033] Specifically, the sampling circuit samples the input signal V. inThe simulation is performed and transmitted to the comparator, then the most significant bit (MSB) is set to 1, and the remaining bits are all zero, according to signal V. in 1 / 2V REF The comparator output is obtained by determining the magnitude relationship between them, and then... in <1 / 2V REF V in >1 / 2V REF The highest bit is either 0 or 1, thus accurately determining the highest bit. Similarly, the second highest bit, and so on, can be determined. Finally, the process ends after obtaining the lowest bit. The first and second kernel modules use a successive approximation method, which is beneficial for reducing area and cost. A specific embodiment is described here; see [link to specific implementation]. Figure 1 In this embodiment of the invention, the dual-core analog-to-digital converter (ADC) has a first core module responsible for calculating the high four bits and outputting D11-D8, i.e., the first core module is responsible for handling high voltage input issues, while the second core module is responsible for calculating the low eight bits and outputting the final result D11-D0, i.e., the second core module is responsible for handling high voltage input issues. The two core modules work relatively independently, sharing the same timing, and cooperate to complete the final AD calculation, thereby helping to solve the problem of wide voltage input.

[0034] Reference Figure 2 Another aspect of the present invention provides a clock management circuit, which is disposed in a first control logic circuit and a second control logic circuit, for providing clock functionality to the analog-to-digital converter. The clock management circuit includes a pulse generation circuit, a first phase-locked loop (DLL1), a second phase-locked loop (DLL2), and a phase operation circuit connected in sequence. Both the first and second phase-locked loops include a delay circuit (controllable delay chain), a phase detector, and a charge pump connected in sequence. The output terminal of the pulse generation circuit is connected to the input terminal of the delay circuit, and the output terminal of the pulse generation circuit is connected to the input terminal of the phase detector of the first phase-locked loop. The output terminal of the charge pump is connected to the input terminal of the delay circuit. Specifically, the input terminal of the delay circuit of the first phase-locked loop is connected to the pulse generation circuit; the output terminal of the phase detector of the first phase-locked loop is connected to both the input terminals of the delay circuit and the phase detector of the second phase-locked loop; the output terminal of the delay circuit of the second phase-locked loop is connected to the input terminal of the phase operation circuit, which outputs a clock signal. Specifically, the first phase-locked loop (DLL1) processes input clock signals with different duty cycles into clock signals with a 50% duty cycle. The second phase-locked loop (DLL2) then delays the 50% duty cycle clock signal output from DLL1 by a short time and generates multiple clock signals P1, P2, P3, ..., P8 with equal phase differences, where P... n With P n+1The clock signal is an inverted clock signal, and there is a certain delay between the two. The phase operation circuit calculates the output phase of DLL2 to generate the dual-phase non-overlapping clock GLK required by the analog-to-digital converter (ADC). OUT1 GLK OUT2 , ..., GLK OUTn Signal, in which GLK OUTn With GLK OUTn+1 The signal is a set of two-phase non-overlapping clock signals, and n can be determined according to the number of non-overlapping clock signals required by the actual circuit.

[0035] In one application embodiment, the pulse generation circuit is a narrow pulse generation circuit, including a D flip-flop, an inverter, and a buffer, used to generate an input clock signal GLK with an arbitrary duty cycle. IN The signal is converted into a narrow pulse clock signal with a fixed pulse width, allowing the phase-locked loop (PLL) to adjust the duty cycle of the clock signal through delay. The narrow pulse clock signal output by the pulse generation circuit enters the delay circuit of the first PLL (hereinafter referred to as the first delay circuit). Referring to Figure 3(a), the first delay circuit includes a MOSFET M... d11 M d12 M d13 And the first inverter, MOSFET M d11 and M d12 Parallel configuration, narrow pulse clock signal passes through M d11 and M d12 After the source terminal, GLK0 is output through the first inverter to the phase detector of DDL1 (hereinafter referred to as the first phase detector). Among them, MOS transistor M d12 The drain and MOSFET M d13 The gate connection of DDL1, the charge pump output signal V CTRL / V CTRL1 Input to MOSFET M d13 In the source. This configuration makes the terminal voltage V... CTRL / V CTRL1 The value of the delay affects the falling edge of the clock but has no effect on the rising edge, thus enabling the delay of only one edge of the clock to be adjusted while ensuring that the other edge is not affected, thereby allowing the first phase-locked loop to stably output the clock duty cycle.

[0036] See Figure 2 The first phase detector outputs the signal GLK. 50％ The circuit then enters the delay circuit of DLL2 (hereinafter referred to as the second delay circuit). Referring to Figure 3(b), the second delay circuit includes a second inverter and a MOSFET M... d21 and capacitor C d2 Input signal GLK 50％The signal enters the second inverter, and is then output to the phase operation circuit and the phase detector of DDL2. The MOS transistor M... d21 The gate of the MOSFET is connected to the output of the second inverter. d21 The drain and capacitor C d2 Connection, DDL2's charge pump output signal V CTRL / V CTRL1 Input to MOSFET M d13 In the source of the circuit. By changing the equivalent load of the second inverter, the delay of the rising and falling edges of the output clock can be changed simultaneously, so that the second phase-locked loop can generate a small, controllable delay for both the rising and falling edges of the clock signal.

[0037] In one embodiment, reference is made to Figure 4 In the clock management circuit of this embodiment, the output signal of the phase detector is the control signal of the charge pump. The charge pump includes a bias circuit and a charge pump core circuit; the bias circuit provides bias for the charge pump core circuit. See also... Figure 4 Mid-frame Figure 1 The bias circuit includes a current source Ibias and MOSFETs M23, M24, and M25. See also... Figure 4 Mid-frame Figure 2 The charge pump core circuit includes MOSFETs M1-M22, MOSFETs M26-M29, and transmission gates TG1 and TG2. Among them, MOSFETs M2 and M3 form a common-source, common-gate charging current source, MOSFETs M4 and M5 form a common-source, common-gate amplification current source, PMOS transistor M1 is the common-source switch (i.e., charging switch) for the charging current source, and NMOS transistor M6 is the common-source switch (i.e., discharging switch) for the discharging current source. Thus, the charge sharing of the charge pump is suppressed by using common-source switching technology.

[0038] Furthermore, MOSFETs M18-M22 and transmission gate TG1 form the first transmission gate control circuit of the charging current source, with control terminals UP and UPb... MOSFETs M13-M17 and transmission gate TG2 form the second transmission gate control circuit of the charging current source. The control terminals DN and DNb... A first transmission gate control circuit is added between the bias circuit and the common-source cascode charging current source, and a second transmission gate control circuit is added between the bias circuit and the common-source cascode discharging current source. This allows the charging current source and the common-source switch PMOS transistor M1 to be turned off simultaneously, as well as the discharging current source and the common-source switch NMOS transistor M6 to be turned off simultaneously. This suppresses the leakage current generated when the charge pump is turned off, making the charge pump output voltage more stable.

[0039] In one application embodiment, when UP=0 and DN=1, the common-source PMOS transistor M1 (charging switch) is turned off, and the common-source NMOS transistor M6 (discharging switch) is turned on, causing the charge pump to discharge. At this time, the transmission gate TG1 is turned off and the transmission gate TG2 is turned on, cutting off the gate bias voltage of the charging current source M2 transistor, thereby suppressing the leakage current generated in the charging branch. Correspondingly, when UP=1 and DN=0, the common-source PMOS transistor M1 (charging switch) is turned on, and the common-source NMOS transistor M6 (discharging switch) is turned off. At this time, the transmission gate TG1 is turned on and the transmission gate TG2 is turned off, cutting off the gate bias voltage of the discharging current source M5 transistor, thereby suppressing the leakage current generated in the discharging branch.

[0040] In one embodiment, the discharge current source and the discharge boost circuit form a discharge negative feedback loop, and the charging current source and the charging boost circuit form a charging negative feedback loop. This increases the impedance in the charging and discharging branches, making the charge pump's charging and discharging current more stable and improving the matching of the charge pump's charging and discharging current. Specifically, referring to Figure 3, the discharge boost circuit includes MOSFETs M10-M12, which, together with MOSFETs M4-M5, form a discharge negative feedback loop, thereby increasing the impedance of the discharge branch. The charging boost circuit includes MOSFETs M7-M9, which, together with MOSFETs M2-M3, form a charging negative feedback loop, thereby increasing the impedance of the charging branch.

[0041] In one application embodiment, the impedance R1 of the charging current source is calculated as follows:

[0042] R1≈g m8 {r 026 ||[g m9 r 09 (r 08 ||r 07 )]}(g m3 r 03 r 02 )

[0043] In the formula, g m8 For the equivalent transconductance of NMOS transistor M8, r 026 G is the channel impedance of NMOS transistor M26. m9 For the equivalent transconductance of PMOS transistor M9, r 09 r is the channel impedance of PMOS transistor M9. 08 r is the channel impedance of NMOS transistor M8. 07 G is the channel impedance of PMOS transistor M7. m3 For the equivalent transconductance of PMOS transistor M3, r 03 r is the channel impedance of PMOS transistor M3. 02 This is the channel impedance of PMOS transistor M2.

[0044] In one application embodiment, the impedance R2 of the charging current source is calculated as follows:

[0045] R2≈g m10 {r 028 ||[g m11 r 011 (r 010 ||r 012 )]}(g m4 r 04 r 05 )

[0046] In the formula, g m10 For the equivalent transconductance of PMOS transistor M10, r 028 G is the channel impedance of the PMOS transistor M28. m11 For the equivalent transconductance of NMOS transistor M11, r 011 r is the channel impedance of NMOS transistor M11. 010 r is the channel impedance of PMOS transistor M10. 012 G is the channel impedance of NMOS transistor M12. m4 For the equivalent transconductance of NMOS transistor M4, r 04 r is the channel impedance of PMOS transistor M4. 05 This is the channel impedance of NMOS transistor M5.

[0047] In one embodiment, in the first and second phase-locked loops of this invention, a single-ended to complementary circuit is provided between the phase detector and the charge pump. The single-ended to complementary circuit consists of a directional controller and a transmission gate. The single-ended to complementary circuit converts the single-phase clock signal GLK output by the phase detector into a complementary circuit. 50％ / GLK PD This is converted into two complementary clock signals, CLK and GLK. n (i.e., GLK1 and GLK) 1n GLK2 and GLK 2n Accordingly, the charge pump is equipped with two common-source PMOS transistors M1 (charging switches) and two common-source NMOS transistors M6 (discharging switches) for switching on and off the two clock signals, respectively, as well as an operational amplifier and two complementary switched capacitors. The inverting input ("-") terminal of the operational amplifier is connected to the output terminal of the operational amplifier, the non-inverting input ("+") terminal of the operational amplifier is connected to one of the common-source PMOS transistors M1 and M6, and one switched capacitor, and the output terminal of the operational amplifier is connected to the other common-source PMOS transistor M1, the other common-source NMOS transistor M6, and the other switched capacitor. The output signal V of the charge pump is... CTRL (V CTRL1 / VCTRL2 The input is given to the non-inverting input ("+") terminal of the operational amplifier. The charging switches (S1 and S2) and discharging switches (S3 and S4) are controlled by the output signals CLK and GLK of the phase detector. n (i.e., GLK1 and GLK) 1n GLK2 and GLK 2n )control.

[0048] Specifically, when the charging switch is closed and the discharging switch is open, the charge pump flows through the charging current source I. P The switched capacitor is charged so that the output voltage V CTRL The current continuously increases. When the charging switch is open and the discharging switch is closed, the discharge current source I of the charge pump... N Discharging the switched capacitor causes the output voltage V to... CTRL The voltage continuously decreases. At that time, the charging switch and discharging switch were simultaneously closed or opened, and the output voltage was a single voltage V. CTRL This setting remains unchanged. This configuration ensures that both the charging and discharging current sources are always on, and that the terminal voltage of the current source always follows the output voltage, thus avoiding phase jitter caused by voltage fluctuations at the current source terminals during switching.

[0049] This invention experimentally verifies the design of an analog-to-digital converter and its storage method. (Participants) Figure 6 Signal 1 is the conversion signal, signal 2 is the GLK signal, signal 3 is the output change of DACH, signal 4 is the output result of CMPH, signal 5 is the output change of DACL, signal 6 is the output result of CMPL, and signal 7 is the structure of the digital output. Simulation results demonstrate that the analog-to-digital converter of this embodiment can achieve stable output under wide voltage conditions.

[0050] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable analog-to-digital converter. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0051] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0052] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RS1M, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0053] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in a non-volatile analog-to-digital converter. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including a specific visual depiction of physical and tangible objects generated on the display.

[0054] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A clock management circuit, characterized in that, include: The circuit includes a pulse generation circuit, a first phase-locked loop (PLL), a second PLL, and a phase calculation circuit; both the first PLL and the second PLL include a delay circuit, a phase detector, and a charge pump. The pulse generation circuit and the phase detector of the first phase-locked loop both receive a clock signal CLK. IN The output terminal of the pulse generation circuit is connected to the input terminal of the delay circuit of the first phase-locked loop. The output terminal of the delay circuit of the first phase-locked loop is connected to the second input terminal of the phase detector of the first phase-locked loop; the output terminal of the phase detector of the first phase-locked loop is connected to the input terminal of the charge pump of the first phase-locked loop, the input terminal of the delay circuit of the second phase-locked loop, and the first input terminal of the phase detector of the second phase-locked loop; the output terminal of the charge pump of the first phase-locked loop is connected to the input terminal of the delay circuit of the first phase-locked loop. The output terminal of the delay circuit of the second phase-locked loop is connected to the second input terminal of the phase detector of the second phase-locked loop and the input terminal of the phase operation circuit, respectively; the output terminal of the phase detector of the second phase-locked loop is connected to the input terminal of the charge pump of the second phase-locked loop, and the output terminal of the charge pump of the second phase-locked loop is connected to the input terminal of the delay circuit of the second phase-locked loop. The first phase-locked loop processes input clock signals with different duty cycles into clock signals with a 50% duty cycle, and the second phase-locked loop delays the 50% duty cycle clock signal output by the first phase-locked loop by a short time and generates multiple clock signals with equal phase differences. The phase operation circuit calculates the output phase of the second phase-locked loop to generate the dual-phase non-overlapping clock required by the analog-to-digital converter.

2. The clock management circuit according to claim 1, characterized in that, The charge pump includes a charge pump core circuit; the charge pump core circuit includes a common-gate common-source charging current source and a common-gate common-source discharging current source, the charging current source being connected to a common-source PMOS transistor M1; the discharging current source being connected to a common-source NMOS transistor M6; the common-source PMOS transistor M1 and the common-source NMOS transistor M6 are controlled by the output signal of the phase detector.

3. The clock management circuit according to claim 2, characterized in that, The charge pump further includes a bias circuit for providing bias to the charge pump core circuitry; the bias circuit is connected to the gate of the charging current source via a first transmission gate control circuit, and the bias circuit is connected to the gate of the discharging current source via a second transmission gate control circuit.

4. The clock management circuit according to claim 3, characterized in that, The discharge current source and the discharge boosting circuit form a discharge negative feedback loop; the charging current source and the charging boosting circuit form a charging negative feedback loop.

5. The clock management circuit according to claim 4, characterized in that, The impedance of the charging current source The calculation is as follows: In the formula, The equivalent transconductance of NMOS transistor M8 is... The channel impedance of NMOS transistor M26 is... This is the equivalent transconductance of PMOS transistor M9. The channel impedance of PMOS transistor M9 is... The channel impedance of NMOS transistor M8 is... The channel impedance of NMOS transistor M7 is... This is the equivalent transconductance of PMOS transistor M3. This is the channel impedance of PMOS transistor M3. The channel impedance of PMOS transistor M2; The impedance R2 of the discharge current source is calculated as follows: In the formula, The equivalent transconductance of PMOS transistor M10 is given. The channel impedance of PMOS transistor M28 is... The equivalent transconductance of NMOS transistor M11, The channel impedance of NMOS transistor M11 is... The channel impedance of PMOS transistor M10 is... The channel impedance of NMOS transistor M12 is... The equivalent transconductance of NMOS transistor M4 is given. This is the channel impedance of PMOS transistor M4. This is the channel impedance of NMOS transistor M5.

6. The clock management circuit according to claim 2, characterized in that, A single-ended to complementary circuit is provided between the phase detector and the charge pump. The single-ended to complementary circuit converts the single-phase clock signal output by the phase detector into two complementary clock signals. The charge pump includes an operational amplifier, two common-source PMOS transistors M1 for switching on and off the two clock signals, two common-source NMOS transistors M6 for switching on and off the two clock signals, and two switched capacitors. The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to one of the common-source PMOS transistors M1, one of the common-source NMOS transistors M6, and one switched capacitor. The output terminal of the operational amplifier is connected to another common-source PMOS transistor M1, another common-source NMOS transistor M6, and another switched capacitor.

7. The clock management circuit according to claim 6, characterized in that, The delay circuit of the first phase-locked loop includes a MOSFET M d11 MOSFET M d12 MOSFET M d13 And the first inverter, the MOS transistor M d11 and the MOS transistor M d12 The pulse generation circuit is connected in parallel with the output terminal of the MOS transistor M. d11 The source and MOS transistor M d12 The source connection, M d11 The drain terminal and MOSFET M d12 The gate terminal is connected to the input terminal of the first inverter, and the first inverter outputs a signal.

8. The clock management circuit according to claim 6, characterized in that, The delay circuit of the second phase-locked loop includes a second inverter and a MOSFET M. d21 and capacitor C d2 The output terminal of the phase detector in the first phase-locked loop is connected to the input terminal of the second inverter, and the second inverter outputs a signal; the MOS transistor M d21 The gate of the MOSFET is connected to the output terminal of the second inverter. d21 The drain of the capacitor C d2 The output terminal of the charge pump of the second phase-locked loop is connected to the MOS transistor M. d21 The source connection.

9. An analog-to-digital converter, characterized in that, include: A first kernel module, the first kernel module including a first control logic circuit, the first control logic circuit including a clock management circuit according to any one of claims 1 to 8; The second kernel module includes a second control logic circuit, which includes a clock management circuit as described in any one of claims 1 to 8. The input terminal of the first control logic circuit is connected to the input terminal of the second control logic circuit, and the second control logic circuit outputs the final result.

10. The analog-to-digital converter according to claim 9, characterized in that: The first kernel module further includes a first sampling circuit, a first comparator, and a first digital-to-analog converter circuit. The output terminal of the first sampling circuit is connected to the non-inverting input terminal of the first comparator circuit. The output terminal of the first comparator circuit is connected to the input terminal of the first control logic circuit. The output terminal of the first control logic circuit is connected to the input terminal of the first digital-to-analog converter circuit. The output terminal of the first digital-to-analog converter circuit is connected to the non-inverting input terminal of the first comparator circuit. The second kernel module further includes a second sampling circuit, a second comparison circuit, and a second digital-to-analog converter circuit. The output terminal of the second sampling circuit is connected to the inverting input terminal of the second comparison circuit. The output terminal of the second comparison circuit is connected to the input terminal of the second control logic circuit. The output terminal of the second control logic circuit is connected to the input terminal of the second digital-to-analog converter circuit. The output terminal of the second digital-to-analog converter circuit is connected to the inverting input terminal of the second comparison circuit.

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