Pixel circuit and display panel

Abstract

The application discloses a pixel circuit and a display panel. The pixel circuit comprises a data writing module. The data writing module is used for writing data voltage of a current frame to a first node in a setting stage before a data writing stage of the current frame, and controlling the first node and a second node to be disconnected. The setting stage at least comprises a light emitting stage of a previous frame. The data writing module is also used for transmitting the data voltage of the current frame from the first node to the second node in the data writing stage of the current frame. Since the writing of the data voltage of the current frame to the pixel circuit is completed in advance before the data writing stage of the current frame, even if the refresh frequency is increased and the time of the data writing stage is reduced, the data voltage can still be fully transmitted to the second node, and the display effect is improved. Meanwhile, the first nodes and the second nodes of all rows of pixel circuits are simultaneously connected, the high refresh rate can be ensured, the overall switching of a display picture is realized, and the display effect is further improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a pixel circuit and a display panel. BACKGROUND

[0002] With the development of display technology, panel manufacturers and consumers have higher and higher requirements for high-frequency display of display panels.

[0003] At present, with the increase of refresh frequency, the time of one frame becomes shorter, so that the time of data writing becomes shorter, which leads to insufficient data writing and affects the display effect. SUMMARY

[0004] The present application provides a pixel circuit and a display panel to make the writing of data voltage more sufficient and improve the display effect.

[0005] In a first aspect, embodiments of the present application provide a pixel circuit, comprising: a data writing module, a first storage module, a second storage module, a driving module, and a light emitting module.

[0006] The data writing module is configured to write data voltage of a current frame to a first node and control the first node and a second node to be disconnected in a setting stage before a data writing stage of the current frame, wherein the setting stage at least includes a light emitting stage of a previous frame.

[0007] The data writing module is further configured to transmit the data voltage of the current frame from the first node to the second node in the data writing stage of the current frame.

[0008] The driving module and the light emitting module are connected between a first power voltage input end and a second power voltage input end, a control end of the driving module is electrically connected with the second node, and the driving module is configured to drive the light emitting module to emit light according to the data voltage of the current frame in a light emitting stage of the current frame.

[0009] One end of the first storage module is electrically connected with the first power voltage input end, and the other end is electrically connected with the first node; one end of the second storage module is electrically connected with the first power voltage input end, and the other end is electrically connected with the second node.

[0010] Optionally, the data writing module comprises a first writing unit and a second writing unit, the first writing unit is configured to write the data voltage of the current frame to the first node in the setting stage before the data writing stage of the current frame.

[0011] The second writing unit is configured to control the first node and the second node to be disconnected in the setting stage, and to transmit the data voltage from the first node to the second node in the data writing stage of the current frame.

[0012] Optionally, the control end of the first write unit is electrically connected with the first control signal input end, the first end of the first write unit is electrically connected with the data voltage input end, and the second end of the first write unit is electrically connected with the first node.

[0013] The control end of the second write unit is electrically connected with the second control signal input end, the first end of the second write unit is electrically connected with the first node, and the second end of the second write unit is electrically connected with the second node.

[0014] Optionally, the first write unit comprises a first transistor, the gate of the first transistor is used as the control end of the first write unit, the first pole of the first transistor is used as the first end of the first write unit, and the second pole of the first transistor is used as the second end of the first write unit.

[0015] Optionally, the second write unit comprises a second transistor, the gate of the second transistor is used as the control end of the second write unit, the first pole of the second transistor is used as the first end of the second write unit, and the second pole of the second transistor is used as the second end of the second write unit.

[0016] Optionally, the pixel circuit further comprises a light-emitting control module, the light-emitting control module comprises a first light-emitting control unit connected between the first end of the driving module and the first power voltage input end and / or a second light-emitting control unit connected between the second end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is electrically connected with the second power voltage input end, and the light-emitting control module is used for being turned on in the light-emitting stage.

[0017] Optionally, the pixel circuit further comprises a first initialization module, the first initialization module is used for writing the first initialization voltage to the control end of the driving module in the initialization stage.

[0018] Optionally, the setting stage further comprises an initialization stage of the current frame.

[0019] Optionally, the pixel circuit further comprises a second initialization module, the second initialization module is used for writing the second initialization voltage to the first end of the light-emitting module in the initialization stage.

[0020] Optionally, the data voltage is equal to [Vx*(C01+C02)-C02*Vinit1] / C01.

[0021] Wherein, Vx represents the required voltage of the control end of the driving module corresponding to the target display gray scale of the current frame, C01 represents the size of the first storage capacitor included in the first storage module, C02 represents the size of the second storage capacitor included in the second storage module, and Vinit1 represents the first initialization voltage.

[0022] In a second aspect, the embodiments of the present application further provide a display panel comprising the pixel circuit of the first aspect.

[0023] Optionally, the pixel circuit array is arranged, the data writing module comprises a first writing unit and a second writing unit, the display panel further comprises a control module and a plurality of first control signal lines, wherein the control module comprises a plurality of first output ends, each first output end is electrically connected with the control end of the first writing unit of a row of pixel circuits through a first control signal line;

[0024] The display panel further comprises a second control signal line, the control module comprises a second output end electrically connected with the second control signal line, and the second control signal line is electrically connected with the control end of the second writing unit of each pixel circuit in the display panel; or the display panel further comprises a plurality of second control signal lines, the control module comprises a second output end electrically connected with each second control signal line in a one-to-one manner, and each second output end is electrically connected with the control end of the second writing unit of a row of pixel circuits through a second control signal line.

[0025] Optionally, the pixel circuit further comprises a light-emitting control module;

[0026] The display panel further comprises a data output module and a data line connected with the data output module, each data line is connected with a column of pixel circuits, and the data output module is configured to output, when the control module outputs an effective level signal of a first control signal to a first control signal line through a first output end, a data voltage corresponding to a next frame of a pixel circuit connected with the first control signal line to each data line;

[0027] The display panel comprises a second control signal line, the display panel further comprises a light-emitting control signal line, the control module further comprises a third output end electrically connected with the light-emitting control signal line, and the light-emitting control signal line is electrically connected with the control end of the light-emitting control module of each pixel circuit in the display panel; the control module is configured to sequentially output an effective level signal of a first control signal through a first output end when an effective level signal of a light-emitting control signal is output through a third output end; and the control module is further configured to output an effective level signal of a second control signal to the second control signal line through a second output end after sequentially outputting the effective level signal of the first control signal through the first output end and outputting the effective level signal of the light-emitting control signal through the third output end;

[0028] Alternatively, the display panel includes a plurality of second control signal lines, the display panel further includes a plurality of light-emitting control signal lines, the control module further includes a third output end electrically connected to each of the light-emitting control signal lines, each of the light-emitting control signal lines is electrically connected to the control end of the light-emitting control module of a row of pixel circuits in the display panel; when the control module outputs an effective level signal of the light-emitting control signal through the third output end to the connected light-emitting control signal line, the control module outputs an effective level signal of the first control signal through the first output end to the row of pixel circuits connected to the light-emitting control signal line; and the control module is further configured to output an effective level signal of the second control signal through the second output end to the row of pixel circuits connected to the light-emitting control signal line after the control module outputs an effective level signal of the first control signal through the first output end to the row of pixel circuits connected to the light-emitting control signal line and outputs an effective level signal of the light-emitting control signal through the third output end.

[0029] Optionally, the pixel circuit further includes a first initialization module.

[0030] The display panel includes a second control signal line, the display panel further includes a light-emitting control signal line, the display panel further includes an initialization control signal line, the control module further includes a fourth output end electrically connected to the initialization control signal line, and the initialization control signal line is electrically connected to the control end of the first initialization module of each pixel circuit in the display panel; the control module is further configured to output an effective level signal of the initialization control signal through the fourth output end to the initialization control signal line after the control module outputs an effective level signal of the first control signal through the first output end and outputs an effective level signal of the light-emitting control signal through the third output end; and the control module is further configured to output an effective level signal of the second control signal through the second output end to the second control signal line after the control module outputs an effective level signal of the initialization control signal through the fourth output end to the initialization control signal line.

[0031] Alternatively, the display panel includes a plurality of second control signal lines, the display panel further includes a plurality of light-emitting control signal lines, the display panel further includes a plurality of initialization control signal lines, the control module further includes a fourth output end electrically connected to each initialization control signal line in one-to-one correspondence, and each initialization control signal line is electrically connected to the control end of the initialization control module of a row of pixel circuits in the display panel; the control module is further configured to, after the effective level signal of the first control signal is output to the row of pixel circuits connected to the light-emitting control signal line through the first output end and the effective level signal of the light-emitting control signal is output through the third output end, output the effective level signal of the initialization control signal to the initialization control signal line connected to the row of pixel circuits through the fourth output end; and the control module is further configured to, after the effective level signal of the initialization control signal is output to the initialization control signal line connected to the row of pixel circuits through the fourth output end, output the effective level signal of the second control signal to the row of pixel circuits connected to the light-emitting control signal line through the second output end.

[0032] The pixel circuit and the display panel provided by the embodiment of the present application include a data writing module, a first storage module, a second storage module, a driving module and a light-emitting module. The data writing module is configured to write a data voltage to a first node and control the first node to be disconnected from a second node in a setting stage before a data writing stage of a current frame, and the setting stage at least includes a light-emitting stage of a previous frame. The data writing module is further configured to transmit the data voltage from the first node to the second node in the data writing stage of the current frame. In the embodiment of the present application, the data writing module of the pixel circuit writes the data voltage of the current frame to the first node of the pixel circuit in the setting stage before the data writing stage of the current frame, and the setting stage at least includes the light-emitting stage of the previous frame. Because the light-emitting stage has a relatively long time, the data voltage can be more fully written into the pixel circuit. Because the writing of the data voltage of the current frame to the pixel circuit is completed in advance before the data writing stage of the current frame, even if the refresh frequency is increased and the time of the data writing stage is reduced, the data voltage of the current frame can still be fully transmitted to the second node, which is beneficial to improving the display effect. Meanwhile, when the first nodes and the second nodes of all the rows of pixel circuits are simultaneously connected, the first nodes of all the pixel circuits can be simultaneously written with the data voltage, so that the high refresh rate can be ensured, the overall switching of the display picture can be realized, the problem that the display picture of the current frame and the display picture of the previous frame exist simultaneously can be avoided, and the display effect can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a pixel circuit provided by the embodiment of the present application;

[0034] Figure 2Fig. 3 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0035] Figure 3 Fig. 4 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0036] Figure 4 Fig. 5 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0037] Figure 5 Fig. 6 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0038] Figure 6 Fig. 7 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0039] Figure 7 Fig. 8 is a timing diagram of a pixel circuit provided by an embodiment of the present application;

[0040] Figure 8 Fig. 9 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present application;

[0041] Figure 9 Fig. 10 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0042] Figure 10 Fig. 11 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0043] Figure 11 Fig. 12 is a driving timing diagram of a display panel provided by an embodiment of the present application;

[0044] Figure 12 Fig. 13 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0045] Figure 13 Fig. 14 is a driving timing diagram of another display panel provided by an embodiment of the present application;

[0046] Figure 14 Fig. 15 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0047] Figure 15 Fig. 16 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0048] Figure 16 Fig. 17 is a driving timing diagram of another display panel provided by an embodiment of the present application;

[0049] Figure 17 Fig. 18 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0050] Figure 18 is another driving timing diagram of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended to be merely illustrative of the present application and not in limitation thereof. It should also be noted that, for the purpose of description, only the parts related to the present application are shown in the accompanying drawings rather than all the parts.

[0052] As described in the background section, the data voltage writing of the existing pixel circuit is incomplete, and there is a problem of uneven display of the display panel. The inventors have found that the reason for the above problem is that the working process of the existing pixel circuit usually includes a data writing stage and a light emitting stage. In the data writing stage, the driving chip of the display panel writes the data voltage to the pixel circuit through the data line. In the light emitting stage, the driving transistor of the pixel circuit emits light according to the written data voltage. In the working process of the existing pixel circuit, the data writing stage of the display panel in which the driving chip transmits the data voltage to the data line is a separately set stage, and the data voltage in the display panel is written to the pixel circuit row by row. Therefore, the data writing stage time for each row of pixel circuit is very short, which causes the data voltage to be unable to be fully written to the pixel circuit, resulting in poor display effect.

[0053] Based on the above reasons, the present application provides a pixel circuit, Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application, referring to Figure 1 The pixel circuit includes a data writing module 10, a first storage module 20, a second storage module 30, a driving module 40, and a light emitting module 50.

[0054] The data writing module 10 is configured to write the data voltage of the current frame to the first node A and control the disconnection between the first node A and the second node B in a setting stage before the data writing stage of the current frame. The setting stage at least includes the light emitting stage of the previous frame.

[0055] The data writing module 10 is further configured to transmit the data voltage of the current frame from the first node A to the second node B in the data writing stage of the current frame.

[0056] The driving module 40 and the light emitting module 50 are connected between the first power voltage input end VDD and the second power voltage input end VSS. The control end of the driving module 40 is electrically connected with the second node B. The driving module 40 is configured to drive the light emitting module 50 to emit light according to the data voltage of the current frame in the light emitting stage of the current frame.

[0057] One end of the first storage module 20 is electrically connected with the first power voltage input terminal VDD, and the other end is electrically connected with the first node A. One end of the second storage module 30 is electrically connected with the first power voltage input terminal VDD, and the other end is electrically connected with the second node B.

[0058] Optionally, the data writing module 10 is electrically connected with the data voltage input terminal VDATA, and the data voltage input terminal VDATA is used to provide a data voltage. The first storage module 20 can be a capacitor, and the second storage module 30 can also be a capacitor. The first storage module 20 is used to store the data voltage written by the first node A, and the second storage module 30 is used to store the voltage at the second node B. The light emitting module 50 can be an organic light emitting diode (OLED), and the OLED emits light under the driving of a driving current. The driving module 40 generates the driving current to drive the light emitting module 50 to emit light according to the data voltage. The first power voltage input terminal VDD can be used to input a first power voltage, and the second power voltage input terminal VSS is used to input a second power voltage. Optionally, the first power voltage can be a high level, and the second power voltage can be a low level.

[0059] The working stage of the pixel circuit can include a data writing stage and a light emitting stage. When the setting stage includes the light emitting stage of the previous frame, that is, in the light emitting stage of the previous frame, the data writing module 10 of the pixel circuit writes the data voltage of the current frame to the first node A, and the time of the light emitting stage is relatively long, so that the data voltage can be sufficiently written into the pixel circuit, and in the light emitting stage of the previous frame, the first node A and the second node B are disconnected, and the data voltage of the current frame written to the first node A cannot be transmitted to the second node B, and thus will not affect the change of the driving current generated by the driving module 40, avoiding affecting the light emission of the light emitting module 50 of the previous frame. In the data writing stage of the current frame, the data writing module 10 transmits the data voltage from the first node A to the second node B. Because the first node A has completed the writing of the data voltage in advance before the data writing stage of the current frame, even if the refresh frequency is increased and the time of the data writing stage is reduced, the data voltage can still be sufficiently transmitted to the second node B, improving the display effect.

[0060] When the display panel comprises a plurality of pixel circuits, in a setting stage before a data writing stage of a current frame, the data voltage of each row of pixel circuits is written to the first node A. When the picture is switched, the first node A and the second node B of all rows of pixel circuits are controlled to be connected at the same time, so that the data voltage of all rows of pixel circuits is written to the control end of the driving module 40 at the same time, and the driving module 40 drives the light-emitting module 50 to emit light according to the data voltage. Controlling the first node A and the second node B of all rows of pixel circuits to be connected at the same time can realize that the data voltage of the first node A of all pixel circuits is written to the second node B at the same time, thereby ensuring a high refresh rate, and realizing the overall switching of the display picture, avoiding the problem that the display picture of the current frame and the display picture of the last frame exist at the same time, and being beneficial to improving the display effect.

[0061] The pixel circuit of the embodiment, the data writing module writes the data voltage of the current frame to the first node of the pixel circuit in a setting stage before a data writing stage of the current frame, and the setting stage at least includes an emitting stage of the last frame. Because the emitting stage has a long time, the data voltage of the current frame can be more fully written into the pixel circuit. Because the writing of the data voltage of the current frame to the pixel circuit is completed in advance before the data writing stage of the current frame, even if the refresh frequency is increased and the time of the data writing stage is reduced, the data voltage can still be fully transmitted to the second node, which is beneficial to improving the display effect. At the same time, when the first node and the second node of the data writing module of all rows of pixel circuits are controlled to be connected at the same time, the data voltage of the first node of all pixel circuits can be written to the second node at the same time, thereby ensuring a high refresh rate, realizing the overall switching of the display picture, avoiding the problem that the display picture of the current frame and the display picture of the last frame exist at the same time, and further improving the display effect.

[0062] Figure 2 Another structure schematic diagram of a pixel circuit provided by the embodiment of the application is provided, and the pixel circuit comprises a first node A and a second node B. Figure 2 Optionally, the data writing module 10 comprises a first writing unit 11 and a second writing unit 12, the first writing unit 11 is used for writing the data voltage of the current frame to the first node A in a setting stage before a data writing stage of the current frame;

[0063] The second writing unit 12 is used for controlling the first node A and the second node B to be disconnected in the setting stage, and is used for transmitting the data voltage from the first node A to the second node B in the data writing stage of the current frame.

[0064] The first writing unit 11 writes the data voltage of the current frame to the first node A in the setting stage, and the second writing unit 12 controls the first node A and the second node B to be disconnected in the setting stage, so as to avoid the influence of the data voltage of the current frame on the potential of the second node B. In the data writing stage of the current frame, the second writing unit 12 controls the first node A and the second node B to be connected, so as to transmit the data voltage of the current frame written in the first node A to the second node B, and realize the control of the control end of the data voltage writing driving module 40.

[0065] With reference to the foregoing Figure 2 Optionally, the control end of the first writing unit 11 is electrically connected with the first control signal input end S1, the first end of the first writing unit 11 is electrically connected with the data voltage input end VDATA, and the second end of the first writing unit 11 is electrically connected with the first node A.

[0066] The control end of the second writing unit 12 is electrically connected with the second control signal input end S2, the first end of the second writing unit 12 is electrically connected with the first node A, and the second end of the second writing unit 12 is electrically connected with the second node B.

[0067] In the setting stage, the first writing unit 11 is turned on under the control of the signal input in the first control signal input end S1, and the data voltage transmitted by the data voltage input end VDATA is written in the first node A. At the same time, in the setting stage, the second writing unit 12 is turned off under the control of the signal input in the second control signal input end S2, so as to avoid the data voltage from being written in the control end of the driving module 40 in the non-data voltage writing stage, thereby affecting the light emission of the light emitting module 50.

[0068] In the data writing stage of the current frame, the second writing unit 12 is turned on under the control of the signal input in the second control signal input end S2, so as to write the data voltage written in the first node A into the second node B, and realize the writing of the data voltage.

[0069] Figure 3 Another structure schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 2. Figure 3 Optionally, the first writing unit 11 comprises a first transistor T1, the gate of the first transistor T1 is used as the control end of the first writing unit 11, the first pole of the first transistor T1 is used as the first end of the first writing unit 11, and the second pole of the first transistor T1 is used as the second end of the first writing unit 11.

[0070] The first transistor T1 can be a P-type transistor or an N-type transistor. In this embodiment, the first transistor T1 is exemplarily shown as a P-type transistor. When the first transistor T1 is a P-type transistor, in the setting stage, the signal inputted by the first control signal input end S1 is at a low level, the first transistor T1 is turned on, and the data voltage of the current frame is written into the first node A. It is worth noting that in the data writing stage of each frame, the signal inputted by the first control signal input end S1 can be at a low level or a high level, that is, the first transistor T1 can be turned on or turned off, which is not specifically limited in this embodiment.

[0071] With reference to the foregoing Figure 3 Optionally, the second writing unit 12 comprises a second transistor T2, a gate of the second transistor T2 serving as a control end of the second writing unit 12, a first pole of the second transistor T2 serving as a first end of the second writing unit 12, and a second pole of the second transistor T2 serving as a second end of the second writing unit 12.

[0072] The second transistor T2 can be a P-type transistor or an N-type transistor. In this embodiment, the second transistor T2 is exemplarily shown as a P-type transistor. When the second transistor T2 is a P-type transistor, in the setting stage before the data writing stage of the current frame, the signal inputted by the second control signal input end S2 is at a high level, and the second transistor T2 is turned off. In the data writing stage of each frame, the signal inputted by the second control signal input end S2 is at a low level, the second transistor T2 is turned on, and the data voltage written into the first node A is transmitted to the second node B.

[0073] Figure 4 Another structure schematic diagram of a pixel circuit provided by the embodiment of the present application is shown in FIG. 6, which is described with reference to the foregoing Figure 4 Optionally, the pixel circuit further comprises a light-emitting control module 60, the light-emitting control module comprising a first light-emitting control unit 61 connected between the first end of the driving module 40 and the first power voltage input end VDD and / or a second light-emitting control unit 62 connected between the second end of the driving module 40 and the first end of the light-emitting module 50, the second end of the light-emitting module 50 being electrically connected with the second power voltage input end VSS, the light-emitting control module 60 being used for being turned on in the light-emitting stage, specifically, the light-emitting control module 60 being used for being turned on in the light-emitting stage of each frame.

[0074] The pixel circuit including the light emitting control module 60 can include only the first light emitting control unit 61 connected between the driving module 40 and the first power voltage input terminal VDD, can include only the second light emitting control unit 62 connected between the driving module 40 and the second power voltage input terminal VSS, and can include both the first light emitting control unit 61 and the second light emitting control unit 62. The embodiment exemplarily shows that the pixel circuit includes both the first light emitting control unit 61 and the second light emitting control unit 62. The first light emitting control unit 61 and the second light emitting control unit 62 are turned on in the light emitting stage of each frame, so that the driving module 40 generates a driving current to drive the light emitting module 50 to emit light according to the data voltage and the first power voltage.

[0075] Figure 5 Another structure schematic diagram of a pixel circuit provided by the embodiment of the present application is shown in FIG. 4. Figure 5 Optionally, the pixel circuit further includes a first initialization module 70, and the first initialization module 70 is configured to write a first initialization voltage to the control terminal of the driving module 40 in an initialization stage.

[0076] The pixel circuit can include only the data writing module 10, the first storage module 20, the second storage module 30, the driving module 40, the light emitting module 50, and the first initialization module 70. The pixel circuit can also include the data writing module 10, the first storage module 20, the second storage module 30, the driving module 40, the light emitting module 50, the light emitting control module 60, and the first initialization module 70. In the embodiment, the pixel circuit includes the data writing module 10, the first storage module 20, the second storage module 30, the driving module 40, the light emitting module 50, the light emitting control module 60, and the first initialization module 70. The first initialization module 70 is connected to the control terminal of the driving module 40, and the first initialization module 70 is also connected to a first initialization voltage input terminal VI1 configured to input a first initialization voltage. Specifically, the first initialization module 70 is configured to be turned on in the initialization stage of each frame. In the initialization stage of each frame, the first initialization module 70 writes the first initialization voltage to the control terminal of the driving module 40, so as to initialize the driving module 40.

[0077] Continuing to refer to Figure 5 Optionally, the setting stage further includes an initialization stage of the current frame.

[0078] In one frame, the working process of the pixel circuit includes an initialization stage, a data writing stage and a light emitting stage. The setting stage includes the light emitting stage of the previous frame and the initialization stage of the current frame. In the light emitting stage of the previous frame and the initialization stage of the current frame, the data writing module 10 writes the data voltage of the current frame to the first node A, and stores the voltage written in the first node A via the first storage module 20. In the initialization stage of the current frame, the first initialization module 70 writes the first initialization voltage to the control end of the driving module 40, and completes the initialization of the driving module 40. In the data writing stage of one frame, the data writing module 10 transmits the data voltage of the current frame written in the first node A to the second node B, and realizes writing the data voltage to the control end of the driving module 40. In the light emitting stage of one frame, the driving module 40 generates the driving current according to the data voltage and the first power voltage input by the first power voltage input end VDD, and drives the light emitting module 50 to emit light. Compared with the setting stage including only the light emitting stage of the previous frame, the setting stage including the light emitting stage of the previous frame and the initialization stage of the current frame can prolong the time of writing the data voltage into the first node A of the pixel circuit, so that the writing of the data voltage into the pixel circuit is more sufficient, thereby further improving the display effect.

[0079] With reference to Figure 5 Optionally, the pixel circuit further includes a second initialization module 80, and the second initialization module 80 is configured to write a second initialization voltage to the first end of the light emitting module 50 in the initialization stage, so as to avoid the influence of the residual charge of the first end of the light emitting module 50 on the light emitting brightness of the current frame. Specifically, the second initialization module 80 is configured to be turned on in the initialization stage of each frame. Optionally, the second initialization module 80 is electrically connected with a second initialization voltage input end VI2, and the second initialization voltage input end VI2 is configured to provide the second initialization voltage. Optionally, the first initialization voltage is equal to the second initialization voltage, and at this time, the first initialization voltage input end VI1 and the second initialization input end VI2 can input the same signal, thereby providing the same initialization voltage.

[0080] Figure 6 Another structure diagram of a pixel circuit provided by the embodiment of the present application is shown in FIG. 4. The pixel circuit shown in FIG. 4 is similar to the pixel circuit shown in FIG. 3, and the difference between the two is that the pixel circuit shown in FIG. 4 further includes a second initialization module 80. Figure 5 and 6Optionally, the first storage module 20 comprises a first storage capacitor C1, the second storage module 30 comprises a second storage capacitor C2, the data writing module 10 comprises a first transistor T1 and a second transistor T2, the connection relationship of the first transistor T1 and the second transistor T2 is the same as the above embodiment, which will not be repeated here. The driving module 40 comprises a third transistor T3, the first initialization module 70 comprises a fourth transistor T4, the second initialization module 80 comprises a fifth transistor T5, the first light-emitting control unit 61 comprises a sixth transistor T6, and the second light-emitting control unit 62 comprises a seventh transistor T7. The first electrode of the fourth transistor T4 is connected to the first initialization voltage input end VI1, the second electrode of the fourth transistor T4 is connected to the gate of the third transistor T3, and the gate of the fourth transistor T4 is connected to the initialization control signal input end S3. The first electrode of the fifth transistor T5 is connected to the second initialization voltage input end VI2, the second electrode of the fifth transistor T5 is connected to the first end of the light-emitting module 50, and the gate of the fifth transistor T5 is connected to the initialization control signal input end S3. The first electrode of the sixth transistor T6 is connected to the first power voltage input end VDD, the second electrode of the sixth transistor T6 is connected to the first electrode of the third transistor T3, the first electrode of the seventh transistor T7 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7 is connected to the first end of the light-emitting module 50, and the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both connected to the light-emitting control signal input end EM.

[0081] Figure 7 A timing diagram of a pixel circuit provided by the embodiment of the present application, Figure 7 The timing diagram shown is applicable to Figure 6 The pixel circuit shown, and Figure 6 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors, as exemplarily shown in the embodiment. For reference Figure 6 and Figure 7For example, when the setting stage includes the light emitting stage t3 of the previous frame T12, the working process of the pixel circuit is as follows: in the light emitting stage t3 of the previous frame T12, the signal inputted by the light emitting control signal input end EM and the signal inputted by the first control signal input end S1 are both low level, the signal inputted by the initialization control signal input end S3 and the signal inputted by the second control signal input end S2 are both high level, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off, the sixth transistor T6 and the seventh transistor T7 are turned on, the first power supply voltage inputted by the first power supply voltage input end VDD is transmitted to the first electrode of the third transistor T3, the third transistor T3 generates a driving current according to the data voltage of the previous frame at the gate and the first power supply voltage at the first electrode, and the light emitting module 50 is driven to emit light. At the same time, the first transistor T1 is turned on, and the data voltage of the current frame T11 is transmitted to the first node A through the first transistor T1. The pulse width of the low level inputted by the first control signal input end S1 can be less than or equal to the pulse width of the low level inputted by the light emitting control signal input end EM.

[0082] In the initialization stage t1 of the current frame T11, the signal inputted by the initialization control signal input end S3 is low level, the signals inputted by the first control signal input end S1, the second control signal input end S2 and the light emitting control signal input end EM are all high level, the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are turned off, the fourth transistor T4 and the fifth transistor T5 are turned on, the first initialization voltage provided by the first initialization voltage input end VI1 is written into the gate of the third transistor T3, and the second initialization voltage provided by the second initialization voltage input end VI2 is written into the first end of the light emitting module 50, and the first initialization voltage can be equal to the second initialization voltage.

[0083] In the data writing stage t2 of the current frame T11, the signal inputted by the initialization control signal input end S3, the signal inputted by the first control signal input end S1 and the signal inputted by the light emitting control signal input end EM are all high level, the signal inputted by the second control signal input end S2 is low level, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the second transistor T2 is turned on, so that the data voltage of the first node A is written into the second node B and stored through the second storage capacitor C2.

[0084] The working process of the light emitting stage t3 of the current frame T11 is the same as that of the light emitting stage t3 of the previous frame T12, and will not be described here in detail.

[0085] Optionally, the data voltage is equal to [Vx*(C01+C02)-C02*Vinit1] / C01.

[0086] Wherein Vx represents the required voltage of the control end of the driving module 40 corresponding to the target display gray scale of the current frame, C01 represents the size of the first storage capacitor C1 included in the first storage module 20, C02 represents the size of the second storage capacitor C2 included in the second storage module 30, and Vinit1 represents the first initialization voltage.

[0087] The pixel circuit satisfies the formula VDA*C01+Vinit1*C02=Vx*(C01+C02), wherein VDA is the data voltage, and according to the above formula, the data voltage VDA=[Vx*(C01+C02)-C02*Vinit1] / C01.

[0088] The embodiment of the present application also provides a driving method of the pixel circuit. Figure 8 The embodiment of the present application also provides a driving method of the pixel circuit.

[0089] The driving method of the pixel circuit comprises:

[0090] S100: The data write-in module writes the data voltage into the first node and controls the disconnection between the first node and the second node before the data write-in stage of the current frame, wherein the setting stage at least comprises the light-emitting stage of the last frame.

[0091] Optionally, the pixel circuit further comprises a first initialization module, and the setting stage further comprises an initialization stage of the current frame.

[0092] S200: The data write-in module transmits the data voltage from the first node to the second node in the data write-in stage of the current frame.

[0093] S300: The driving module drives the light-emitting module to emit light according to the data voltage in the light-emitting stage of the current frame.

[0094] The driving method of the pixel circuit provided by the embodiment has the beneficial effects of the pixel circuit in the above-mentioned embodiment, and the embodiment will not be repeated here.

[0095] The embodiment of the present application also provides a display panel, which comprises the pixel circuit in any of the above-mentioned embodiments. The display panel has the effects of the pixel circuit, and the embodiment will not be repeated here.

[0096] Figure 9 The embodiment of the present application also provides a display panel, which comprises the pixel circuit in any of the above-mentioned embodiments. The display panel has the effects of the pixel circuit, and the embodiment will not be repeated here. Figure 2 and Figure 9Optionally, the pixel circuit array is arranged, the data writing module 10 comprises a first writing unit 11 and a second writing unit 12, and the display panel further comprises a control module 01 and a plurality of first control signal lines CTRL1, wherein the control module 01 comprises a plurality of first output terminals U1, each first output terminal U1 is electrically connected with the control terminal of the first writing unit 11 of a row of pixel circuits 02 through a first control signal line CTRL1.

[0097] For example, the control module 01 can comprise a scanning circuit, the scanning circuit comprises a plurality of stages of shift registers, the output terminal of each stage of shift registers is used as the first output terminal U1 of the control module 01, and the shift registers are used for generating signals for controlling the first writing unit 11 to be turned on and turned off.

[0098] Optionally, the display panel further comprises a second control signal line CTRL2, the control module 01 comprises a second output terminal U2 electrically connected with the second control signal line CTRL2, and the second control signal line CTRL2 is electrically connected with the control terminal of the second writing unit 12 of each pixel circuit 02 in the display panel.

[0099] Here, the second control signal line CTRL2 can be a signal line, and the signal line is connected with the control terminals of the second writing units 12 of all rows of pixel circuits 02. The second control signal line CTRL2 can also comprise a plurality of signal lines, each signal line is connected with the control terminal of the second writing unit 12 of a row of pixel circuits 02, and all the second control signal lines CTRL2 are connected with the same second output terminal U2, so that the control terminals of the second writing units 12 of all rows of pixel circuits 02 are controlled by the same signal.

[0100] In the setting stage before the data writing stage of the current frame, the control module 01 controls the first writing unit 11 of the pixel circuit to be turned on row by row, and then the data voltage of the current frame is transmitted to the first node A, and the voltage at the first node A can be stored through the first storage module 20. In the data writing stage of the current frame, the control module 01 outputs a signal through the second output end U2 to control the second writing unit 12 of all pixel circuits 02 to be turned on at the same time, and then the data voltage of the current frame written by the first node A is transmitted to the control end of the driving module 40, and the driving module 40 drives the light emitting module 50 to emit light according to the data voltage. The control ends of the second writing units 12 of all rows of pixel circuits 02 are connected to the same signal, so that all pixel circuits 02 can simultaneously transmit the data voltage of the current frame written by the first node A to the second node B, so that the driving module 40 simultaneously drives the light emitting module 50 to emit light, thereby realizing the simultaneous switching of the gray scale of all rows of pixel circuits 02, realizing the picture switching of the display panel, thereby avoiding the display panel from remaining the picture of the previous frame when displaying the picture of the current frame, and being beneficial to improving the display quality. When the first node A and the second node B of all rows of pixel circuits 02 are simultaneously connected, the first node A of all pixel circuits 02 can simultaneously write the data voltage of the current frame to the second node B, thereby ensuring a high refresh rate. When the light emitting module 50 emits light, the data voltage of the current frame written in the first node A of all rows of pixel circuits 02 is realized, which does not affect the light emitting effect of the light emitting module 50, and the data voltage of the current frame written in the first node A can be transmitted to the second node B only in a short time. Moreover, all rows of pixel circuits 02 simultaneously switch the gray scale, which avoids the display panel from appearing dark lines, and is beneficial to improving the picture display effect. The process of writing the data voltage of the current frame into the first node A of the pixel circuit 02 is at least multiplexed with the light emitting stage of the previous frame, so that the writing time of the data voltage into the pixel circuit 02 can be sufficient, and the writing of the data voltage from the first node A to the second node B is the writing process of the internal node of the pixel circuit 02, so that even if the refresh frequency is increased and the data writing stage time is reduced, the data voltage can still be fully transmitted to the second node B, and the display effect is further improved.

[0101] Figure 10 Another structure diagram of a display panel provided by the embodiment of the present application is provided, Figure 11 A driving timing diagram of a display panel provided by the embodiment of the present application is provided, Figure 11 The timing diagram shown is applicable to a display panel including Figure 6 The display panel of the pixel circuit shown. Figure 11 In the embodiment, L11 is a first control signal corresponding to the first row of pixel circuits 02, L12 is a first control signal corresponding to the second row of pixel circuits 02, L1n is a first control signal corresponding to the nth row of pixel circuits 02, n≥1, and reference Figure 5 、 Figure 6 ,Figure 10 and Figure 11 Optionally, the pixel circuit further comprises a light emitting control module 60.

[0102] The display panel further comprises a data output module 03 and data lines VD connected with the data output module 03, each data line VD being connected with a column of pixel circuits 02; the data output module 03 is configured to output, when the control module 01 outputs the active level signal of the first control signal to the first control signal line CTRL1 through the first output end U1, the data voltage of the next frame corresponding to the pixel circuit connected with the first control signal line CTRL1 to each data line VD.

[0103] The display panel comprises a second control signal line CTRL2, and further comprises a light emitting control signal line EMB; the control module 01 further comprises a third output end U3 electrically connected with the light emitting control signal line EMB, and the light emitting control signal line EMB is electrically connected with the control end of the light emitting control module 60 of each pixel circuit 02 in the display panel; the control module 01 is configured to sequentially output the active level signal of the first control signal through the first output end U1 when the control module 01 outputs the active level signal of the light emitting control signal M through the third output end U3; and the control module 01 is further configured to output the active level signal of the second control signal to the second control signal line CTRL2 through the second output end U2 after sequentially outputting the active level signal of the first control signal through the first output end U1 and outputting the active level signal of the light emitting control signal M through the third output end U3.

[0104] In the embodiment, the first write-in unit 11 comprises a first transistor T1, the second write-in unit 12 comprises a second transistor T2, the driving module 40 comprises a third transistor T3, and the light emitting control module 60 comprises a sixth transistor T6 and a seventh transistor T7. The connection relationship of each transistor is as described above in the embodiment of the pixel circuit, which will not be repeated here. The first transistor T1 is connected with the first control signal line CTRL1 through a first control signal input end S1, the second transistor T2 is connected with the second control signal line CTRL2 through a second control signal input end S2, and the sixth transistor T6 and the seventh transistor T7 are connected with the light emitting control signal line EMB through a light emitting control signal input end EM.

[0105] The effective level signal is a signal for enabling the corresponding module. When the first transistor T1 is a P-type transistor, the effective level signal of the first control signal is low. When the sixth transistor T6 and the seventh transistor T7 are P-type transistors, the effective level signal of the light-emitting control signal M is low. In other embodiments, when the first transistor T1, the sixth transistor T6 and the seventh transistor T7 are N-type transistors, the corresponding effective level signals are all high. In the light-emitting stage t3 of the current frame T11, the light-emitting control signal M output by the control module 01 is low, the sixth transistor T6 and the seventh transistor T7 are enabled, and the control module 01 controls all the rows of the pixel circuit 02 to emit light at the same time.

[0106] In the light-emitting stage t3 of the current frame T11, the first control signal output by the control module 01 through the first output terminal U1 is low, and the first transistor T1 is enabled row by row. At this time, the data output module 03 outputs the data voltage of the next frame corresponding to the pixel circuit 02 connected to the first control signal line CTRL1 to each data line VD, so as to realize the writing of the data voltage into the first node A of each row of pixel circuit 02 row by row.

[0107] When the light-emitting stage t3 of the current frame T11 ends, the data writing stage t2 of the next frame T13 starts, the second control signal L2 output by the control module 01 to the second control signal line CTRL2 is low, and the second transistor T2 of all rows of pixel circuit 02 is enabled at the same time, and the data voltage of the next frame written into the first node A is transmitted to the second node B.

[0108] The working process of the light-emitting stage t3 of the next frame T13 is the same as that of the current frame T11, which will not be described here in detail.

[0109] The display panel of the embodiment can realize the simultaneous writing of the data voltage of the next frame into the first node and the second node of all rows of pixel circuit at the data writing stage of the next frame, so as to ensure the high refresh rate. In the light-emitting stage of the next frame, the sixth transistor and the seventh transistor of all rows of pixel circuit are enabled at the same time, so as to realize the simultaneous switching of all rows of pixel circuit to the next gray scale, and realize the switching of the display panel picture, avoid the existence of the current frame picture and the next frame picture at the same time, and improve the display effect. When the light-emitting module of the current frame emits light, the data voltage of the next frame of all rows is written into the first node of the pixel circuit, which does not affect the light-emitting effect, and the data voltage of the next frame written into the first node can be transmitted to the second node in a short time. All rows of pixel circuit simultaneously switch the gray scale, avoid the display panel to appear dark row, and improve the picture display effect.

[0110] Figure 12 FIG. 2 shows a structure of another display panel according to an embodiment of the present application, Figure 13 FIG. 3 shows a driving timing diagram of another display panel according to an embodiment of the present application, Figure 13 The timing diagram shown in FIG. 1 is applicable to a display panel including Figure 6 The display panel shown in FIG. 2 includes the pixel circuit shown in FIG. 1, and Figure 5 、 Figure 6 、 Figure 12 and Figure 13 Optionally, the pixel circuit 02 further includes a first initialization module 70.

[0111] The display panel includes a second control signal line CLK2, and further includes a light-emitting control signal line EMB and an initialization control signal line CTRL3. The control module 01 further includes a fourth output terminal U4 electrically connected to the initialization control signal line CTRL3. The first initialization module 70 of each pixel circuit 02 in the display panel is electrically connected to the control terminal of the fourth output terminal U4. The control module 01 is configured to sequentially output the active level signal of the first control signal through the first output terminal U1, output the active level signal of the light-emitting control signal M through the third output terminal U3, and then output the active level signal of the initialization control signal VR through the fourth output terminal U4 to the initialization control signal line CTRL3. The control module 01 is further configured to output the active level signal of the second control signal L2 through the second output terminal U2 to the second control signal line CLK2 after outputting the active level signal of the initialization control signal through the fourth output terminal U4 to the initialization control signal line CTRL3.

[0112] In this embodiment, the first initialization module 70 includes a fourth transistor T4. The connection relationship of the fourth transistor T4 is as described above in the embodiment of the pixel circuit. In this embodiment, the connection relationship of the fourth transistor T4 will not be described again. The fourth transistor T4 is connected to the initialization control signal line CTRL3 through the initialization control signal input terminal S3. When the fourth transistor T4 is a P-type transistor, the active level signal of the initialization signal is a low level. In other embodiments, when the fourth transistor T4 is an N-type transistor, the active level signal of the corresponding signal is a high level.

[0113] When the pixel circuit 02 includes the first initialization module 70, the working process of the pixel circuit in any frame includes an initialization stage t1, a data writing stage t2, and a light-emitting stage t3. For the current frame, the setting stage includes at least the light-emitting stage t3 of the previous frame, and the setting stage can further include the initialization stage t1 of the current frame. Figure 13Taking the light emitting stage t3 of the previous frame as an example, in the light emitting stage t3 of the current frame T11 (as the setting stage of the next frame), the control module 01 sends a low level to the control end of the light emitting control module 60 of the pixel circuit 02 of all rows, and controls the light emitting module 50 of all rows to emit light at the same time. At the same time, the control module 01 also transmits a low level to the gate of the first transistor T1 of the pixel circuit 02 row by row, controls the first transistor T1 to be turned on row by row, and realizes writing the data voltage of the next frame T13 into the first node A row by row.

[0114] After the light emitting stage t3 of the current frame T11 ends, the initialization stage t1 of the next frame T13 starts, the control module 01 transmits a low level to the gate of the fourth transistor T4 of the pixel circuit 02 of all rows at the same time, the fourth transistor T4 is turned on, and all rows are controlled to write the first initialization voltage into the gate of the third transistor T3 at the same time, and the initialization of the pixel circuit 02 is completed.

[0115] In the data writing stage t2 of the next frame T13, the control module 01 transmits a low level to the gate of the second transistor T2 of the pixel circuit 02 of all rows at the same time, the second transistor T2 is turned on, all rows are controlled to write the data voltage written into the first node A into the second node B at the same time, and the voltage written into the second node B is stored through the second storage capacitor C2.

[0116] The working process of the light emitting stage of the next frame T13 is the same as the light emitting stage t3 of the current frame T11 described above, and the embodiment will not be described here.

[0117] In the embodiment, when the first node and the second node of all the pixel circuits are simultaneously connected, the first node of all the pixel circuits can simultaneously write data voltages to the second node, and high refresh rate can be ensured. In the light emitting stage of the next frame, the sixth transistor and the seventh transistor of all the pixel circuits are simultaneously controlled to be turned on, so that all the pixel circuits are simultaneously switched to the next gray scale, the switching of the display panel picture is realized, the current frame picture and the next frame picture are prevented from existing simultaneously, and the display effect is improved. When the light emitting module emits light in the current frame, the data voltage of the next frame of all the rows is written into the first node of the pixel circuit, the light emitting effect of the light emitting module in the current frame is not affected, the data voltage written into the first node can be transmitted to the second node in a short time, the gray scale switching of all the pixel circuits is simultaneously performed, the dark row of the display panel is prevented, and the picture display effect is improved. The data voltage writing process in the first node is multiplexed with other working periods, so that even if the refresh frequency is increased and the data writing time is reduced, the data voltage can still be fully transmitted to the second node, and the display effect is further improved. It should be noted that when the setting stage includes the light emitting stage of the previous frame and the initialization stage of the current frame, the total time length of the low voltage transmitted by the control module to the gate electrode of the first transistor of the pixel circuit row by row can be greater than the time length of the light emitting stage, and less than or equal to the total time length of the light emitting stage and the initialization stage.

[0118] Figure 14 Another structure diagram of a display panel provided by the embodiment of the application is shown in FIG. 6. Figure 14 and Figure 2 Optionally, the display panel further includes a plurality of second control signal lines CTRL2, and the control module 01 includes a second output end U2 electrically connected to each of the second control signal lines CTRL2 in one-to-one correspondence. Each second output end U2 is electrically connected to the control end of the second writing unit 12 of a row of pixel circuits 02 through a second control signal line CTRL2.

[0119] In the embodiment, the control module 01 controls the first writing unit 11 of the pixel circuit to be turned on row by row in the setting stage, and then transmits the data voltage to the first node A in the pixel circuit 02 row by row. After the data voltage is written into the first node A of a row of pixel circuits 02, the control module 01 can control the second writing unit 12 connected to the row of pixel circuits 02 to be turned on, so as to transmit the data voltage written in the first node A to the second node B, and then realize the control of the light emitting module 50 to emit light.

[0120] In the setting stage before the data writing stage of the current frame in the embodiment, the data voltage of the current frame is written to the first node of the pixel circuit, and the setting stage at least includes the light emitting stage of the previous frame. The long time of the light emitting stage can make the data voltage of the current frame more fully written into the pixel circuit. The process of writing the data voltage of the current frame into the pixel circuit is at least multiplexed with the light emitting stage of the previous frame of the pixel circuit, so that the writing time of the data voltage of the current frame into the pixel circuit can be sufficient, and the writing of the data voltage of the current frame from the first node to the second node is the writing process of the internal node of the pixel circuit, so that even if the refresh frequency is increased and the time of the data writing stage is reduced, the data voltage can still be fully transmitted from the first node to the second node in the pixel circuit, which is beneficial to improve the display effect.

[0121] Figure 15 Another structure diagram of a display panel provided by the embodiment of the present application is provided, Figure 16 Another driving timing diagram of a display panel provided by the embodiment of the present application is provided, Figure 16 The driving timing diagram shown is applicable to a display panel including Figure 6 The display panel including the pixel circuit shown. Figure 16 In the embodiment, L11 is a first control signal corresponding to the first row of pixel circuits 02, L12 is a first control signal corresponding to the second row of pixel circuits 02, L1n is a first control signal corresponding to the nth row of pixel circuits 02, L21 is a second control signal corresponding to the first row of pixel circuits 02, L22 is a second control signal corresponding to the second row of pixel circuits 02, L2n is a second control signal corresponding to the nth row of pixel circuits 02, M1 is a light emitting control signal corresponding to the first row of pixel circuits 02, M2 is a light emitting control signal corresponding to the second row of pixel circuits 02, and Mn is a light emitting control signal corresponding to the nth row of pixel circuits 02, n≥1. Referring to Figure 5 、 Figure 6 、 Figure 15 and Figure 16Optionally, the display panel comprises a plurality of second control signal lines CTRL2, and the display panel further comprises a plurality of light-emitting control signal lines EMB. The control module 01 further comprises a third output end U3 electrically connected to each of the light-emitting control signal lines EMB. Each of the light-emitting control signal lines EMB is electrically connected to the control end of the light-emitting control module 60 of a row of pixel circuits 02 in the display panel. When the control module 01 outputs an active level signal of the light-emitting control signal to the connected light-emitting control signal line EMB through the third output end U3, the control module 01 outputs an active level signal of the first control signal to the row of pixel circuits 02 connected to the light-emitting control signal line EMB through the first output end U1. After the control module 01 outputs an active level signal of the first control signal to the row of pixel circuits 02 connected to the light-emitting control signal line EMB through the first output end U1 and outputs an active level signal of the light-emitting control signal through the third output end U3, the control module 01 outputs an active level signal of the second control signal to the row of pixel circuits 02 connected to the light-emitting control signal line EMB through the second output end U2.

[0122] In the embodiment, the first write unit 11 comprises a first transistor T1, the second write unit 12 comprises a second transistor T2, the driving module 40 comprises a third transistor T3, and the light-emitting control module 60 comprises a sixth transistor T6 and a seventh transistor T7. The connection relationship of each transistor is described above in the embodiment of the pixel circuit, which will not be repeated here. The first transistor T1 is connected to the first control signal line CTRL1 through a first control signal input end S1, the second transistor T2 is connected to the second control signal line CTRL2 through a second control signal input end S2, and the sixth transistor T6 and the seventh transistor T7 are connected to the light-emitting control signal line EMB through a light-emitting control signal input end EM. When the first transistor T1 is a P-type transistor, the active level signal of the first control signal is low. When the second transistor T2 is a P-type transistor, the active level signal of the second control signal L2 is low. When the sixth transistor T6 and the seventh transistor T7 are P-type transistors, the active level signal of the light-emitting control signal M is low. In other embodiments, when the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are N-type transistors, the active level signals of the corresponding signals are high.

[0123] Taking the first row of pixel circuits as an example, in the light emitting stage t3 of the current frame T11, the control module 01 sends low level to the light emitting control signal line EMB corresponding to each row of pixel circuits 02 row by row, controls the sixth transistor T6 and the seventh transistor T7 to be turned on row by row, and realizes row-by-row control of the light emitting module 50 to emit light. Taking the first row of pixel circuits as an example, in the light emitting stage t3 of the first row of pixel circuits 02 in the current frame T11, the light emitting control signal of the first row of pixel circuits 02 is low level, the control module 01 outputs low level to the first control signal line CTRL1 connected with the first row of pixel circuits 02 at the same time, the first transistor T1 connected with the first row of pixel circuits 02 is turned on, and the data voltage of the next frame T13 is written into the first node A through the first transistor T1, and the first storage capacitor C1 stores the data voltage written into the first node A. After the data voltage of the next frame T13 of the first row of pixel circuits 02 is written into the first node A through the first transistor T1, the first row of pixel circuits 02 enters the data writing stage t2 of the next frame T13, the control module 01 controls the second control signal transmitted by the second control signal line CTRL2 to be low level in the data writing stage t2 of the next frame T13, controls the second transistor T2 of the first row of pixel circuits 02 to be turned on, and makes the data voltage of the next frame T13 written into the first node A written into the second node B. The working process of the light emitting stage t3 of the next frame T13 is the same as that of the current frame T11, which will not be described here in detail.

[0124] In the setting stage before the data writing stage of the next frame in the embodiment, the data voltage of the next frame is written into the first node of the pixel circuit. For the next frame of the current frame, the setting stage at least includes the light emitting stage of the current frame. Because the light emitting stage has a long time, the data voltage of the next frame can be more fully written into the pixel circuit.

[0125] Figure 17 FIG. 4 is a structural schematic diagram of another display panel provided by the embodiment of the present application, Figure 18 FIG. 5 is a driving timing diagram of another display panel provided by the embodiment of the present application, Figure 18 The driving timing diagram shown can be applied to a display panel including Figure 6 the pixel circuit shown, Figure 18 In the embodiment, VR1 is the initialization control signal corresponding to the first row of pixel circuits, VR2 is the initialization control signal corresponding to the second row of pixel circuits, and VR3 is the initialization control signal corresponding to the nth row of pixel circuits 02. Referring to Figure 5 , Figure 6 , Figure 17 and Figure 18Optionally, the display panel comprises a plurality of second control signal lines CTRL2, and further comprises a plurality of light-emitting control signal lines EMB, and further comprises a plurality of initialization control signal lines CTRL3; the control module 01 further comprises a fourth output end U4 electrically connected to the initialization control signal lines CTRL3 in one-to-one correspondence, and each initialization control signal line CTRL3 is electrically connected to the control end of the initialization control module 70 of a row of pixel circuits 02 in the display panel; the control module 01 is further configured to, after outputting the active level signal of the first control signal to a row of pixel circuits 02 connected to the light-emitting control signal line EMB through the first output end U1 and outputting the active level signal of the light-emitting control signal through the third output end U3, output the active level signal of the initialization control signal to the initialization control signal line CTRL3 connected to a row of pixel circuits 02 connected to the light-emitting control signal line EMB through the fourth output end U4; and the control module 01 is further configured to, after outputting the active level signal of the initialization control signal to the initialization control signal line CTRL3 connected to a row of pixel circuits connected to the light-emitting control signal line EMB through the fourth output end U4, output the active level signal of the second control signal to a row of pixel circuits connected to the light-emitting control signal line EMB through the second output end U2.

[0126] In the embodiment, the first initialization module 70 comprises a fourth transistor T4. The connection relationship of the fourth transistor T4 is described above, and will not be repeated here. The fourth transistor T4 is connected to the initialization control signal line CTRL3 through the initialization control signal input end S3. When the fourth transistor T4 is a P-type transistor, the active level signal of the initialization signal is low. In other embodiments, when the fourth transistor T4 is an N-type transistor, the active level signal of the corresponding signal is high.

[0127] When the pixel circuit 02 comprises the first initialization module 70, the working process of the pixel circuit in any frame comprises an initialization stage t1, a data writing stage t2 and a light-emitting stage t3. Optionally, for the current frame, the setting stage at least comprises the light-emitting stage t3 of the previous frame, and the setting stage can further comprise the initialization stage t1 of the current frame. Figure 18 Taking the case that the setting stage comprises the light-emitting stage t3 of the previous frame for the current frame as an example. Taking the first row of pixel circuits 02 as an example, when the control module 01 transmits a low level to the light-emitting control module 60 of the first row of pixel circuits 02, a low level is simultaneously transmitted to the gate of the first transistor T1 connected to the first row of pixel circuits 02, so as to realize writing of the data voltage of the next frame to the first node A of the first row of pixel circuits 02.

[0128] The light emitting stage t3 of the current frame T11 of the first row of pixel circuits 02 ends, and the initialization stage t1 of the next frame T13 of the first row of pixel circuits 02 is entered, the control module 01 transmits a low level to the gate of the fourth transistor T4 of the first row of pixel circuits 02, the fourth transistor T4 is turned on, the first initialization voltage is written to the gate of the third transistor T3, and the initialization of the pixel circuit 02 is completed.

[0129] After the control module 01 transmits a low level to the gate of the fourth transistor T4 of the first row of pixel circuits 02, and the writing of the first initialization voltage is completed, the first row of pixel circuits can enter the data writing stage t2 of the next frame T13, in the data writing stage t2 of the next frame, the control module 01 transmits a low level to the gate of the second transistor T2 of the first row of pixel circuits 02, the second transistor T2 is turned on, the data voltage of the next frame written to the first node A is written to the second node B, and the voltage written to the second node B is stored through the second storage capacitor C2.

[0130] The working process of the light emitting stage of the next frame T13 is the same as that of the light emitting stage t3 of the current frame T11, and will not be described here in this embodiment.

[0131] In the setting stage before the data writing stage of the next frame in this embodiment, the data voltage of the next frame is written to the first node of the pixel circuit, and for the next frame of the current frame, the setting stage at least includes the light emitting stage of the current frame and the initialization stage of the next frame, and because the light emitting stage has a long time, the data voltage of the next frame can be more fully written to the pixel circuit.

[0132] Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: Data writing module, first storage module, second storage module, driver module, light-emitting module; The data writing module is used to write the data voltage of the current frame to the first node during a setting phase before the data writing phase of the current frame, and to control the disconnection between the first node and the second node; wherein, the setting phase includes at least the light emission phase of the previous frame; The data writing module is also used to transmit the data voltage of the current frame from the first node to the second node during the data writing phase of the current frame; The driving module and the light-emitting module are connected between the first power supply voltage input terminal and the second power supply voltage input terminal. The control terminal of the driving module is electrically connected to the second node. The driving module is used to drive the light-emitting module to emit light according to the data voltage of the current frame during the light-emitting phase of the current frame. One end of the first storage module is electrically connected to the first power supply voltage input terminal, and the other end is electrically connected to the first node; one end of the second storage module is electrically connected to the first power supply voltage input terminal, and the other end is electrically connected to the second node. It also includes a first initialization module, which is used to write a first initialization voltage to the control terminal of the drive module during the initialization phase; The setting phase also includes the initialization phase of the current frame, which extends the time for writing the data voltage to the first node; It also includes a light emission control module, which includes a first light emission control unit connected between the first end of the driving module and the first power supply voltage input terminal and / or a second light emission control unit connected between the second end of the driving module and the first end of the light emission module. The second end of the light emission module is electrically connected to the second power supply voltage input terminal. The light emission control module is used to turn on during the light emission phase of the previous frame and / or the current frame; and to turn off the first light emission control unit during the initialization phase of the current frame.

2. The pixel circuit according to claim 1, characterized in that, The data writing module includes a first writing unit and a second writing unit. The first writing unit is used to write the data voltage of the current frame to the first node during the setting stage before the data writing stage of the current frame. The second writing unit is used to control the first node and the second node to disconnect during the setting phase, and to transmit the data voltage from the first node to the second node during the data writing phase of the current frame.

3. The pixel circuit according to claim 2, characterized in that, The control terminal of the first writing unit is electrically connected to the first control signal input terminal, the first terminal of the first writing unit is electrically connected to the data voltage input terminal, and the second terminal of the first writing unit is electrically connected to the first node. The control terminal of the second writing unit is electrically connected to the second control signal input terminal, the first terminal of the second writing unit is electrically connected to the first node, and the second terminal of the second writing unit is electrically connected to the second node.

4. The pixel circuit according to claim 3, characterized in that, The first writing unit includes a first transistor, the gate of the first transistor serves as the control terminal of the first writing unit, the first electrode of the first transistor serves as the first terminal of the first writing unit, and the second electrode of the first transistor serves as the second terminal of the first writing unit.

5. The pixel circuit according to claim 3, characterized in that, The second writing unit includes a second transistor, the gate of the second transistor serves as the control terminal of the second writing unit, the first electrode of the second transistor serves as the first terminal of the second writing unit, and the second electrode of the second transistor serves as the second terminal of the second writing unit.

6. The pixel circuit according to any one of claims 1-5, characterized in that, The pixel circuit further includes a second initialization module, which is used to write a second initialization voltage to the first terminal of the light-emitting module during the initialization phase.

7. The pixel circuit according to claim 1, characterized in that, The data voltage equals ; in This indicates the required voltage at the control terminal of the driving module corresponding to the target display grayscale of the current frame. This indicates the size of the first storage capacitor included in the first storage module. This indicates the size of the second storage capacitor included in the second storage module. This represents the first initialization voltage.

8. A display panel, characterized in that, The display panel includes the pixel circuit according to any one of claims 1-7; the pixel circuit array is arranged, the data writing module includes a first writing unit and a second writing unit, the display panel further includes a control module and multiple first control signal lines, wherein the control module includes multiple first output terminals, and each first output terminal is electrically connected to the control terminal of the first writing unit of a row of pixel circuits through a first control signal line. The display panel further includes a second control signal line, and the control module includes a second output terminal electrically connected to the second control signal line. The second control signal line is electrically connected to the control terminal of the second writing unit of each pixel circuit in the display panel. Alternatively, the display panel further includes multiple second control signal lines, and the control module includes second output terminals electrically connected to each of the second control signal lines. Each second output terminal is electrically connected to the control terminal of the second writing unit of a row of pixel circuits through a second control signal line. The display panel further includes a data output module and data lines connected to the data output module. Each data line connects to a column of pixel circuits. The data output module is used to output the data voltage of the next frame corresponding to the pixel circuit connected to the first control signal line to each data line when the control module outputs an effective level signal of the first control signal to the first control signal line through the first output terminal. The display panel further includes a light emission control signal line, and the control module further includes a third output terminal electrically connected to the light emission control signal line. The light emission control signal line is electrically connected to the control terminals of the light emission control modules of each pixel circuit in the display panel. When the control module outputs an effective level signal of the light emission control signal through the third output terminal, it sequentially outputs an effective level signal of the first control signal through the first output terminal. The control module is also used to sequentially output an effective level signal of the first control signal through the first output terminal and an effective level signal of the light emission control signal through the third output terminal, and then output an effective level signal of the second control signal to the second control signal line through the second output terminal. The display panel further includes an initialization control signal line, and the control module further includes a fourth output terminal electrically connected to the initialization control signal line. The initialization control signal line is electrically connected to the control terminal of the first initialization module of each pixel circuit in the display panel. The control module is also configured to sequentially output a valid level signal of a first control signal through the first output terminal and a valid level signal of a light emission control signal through the third output terminal, and then output a valid level signal of an initialization control signal to the initialization control signal line through the fourth output terminal. The control module is also configured to output a valid level signal of a second control signal to the second control signal line through the second output terminal after outputting a valid level signal of an initialization control signal to the initialization control signal line through the fourth output terminal.

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