A high-speed link time division multiplexing circuit based on video ID

Abstract

The application discloses a high-speed link time division multiplexing circuit based on video ID, which comprises a sending end and a receiving end. The sending end comprises a video sending line buffer, a cyclic priority arbiter, a framing module and a high-speed link sending interface. Parallel video streams of different channels are buffered in the respective video sending line buffers in the form of line buffering. The cyclic priority arbiter reads the data in the non-empty video line buffer according to the state of each video line buffer, marks the video ID, and then sends the data to the framing module for framing. Finally, the data is sent to the high-speed link in series through the high-speed link sending interface. The receiving end decodes the data and distributes the data to different video receiving line buffers according to the video ID for video reconstruction and output. The application improves the utilization rate of the video transmission bandwidth, buffers only video lines, realizes video transmission in a short time, and is convenient for implementation on a programmable logic device.

Description

Technical Field

[0001] This invention belongs to the field of video processing, and relates to integrated circuits for video processing equipment in aerospace vehicles, specifically a high-speed link time-division multiplexing circuit based on video ID. Background Technology

[0002] High-speed digital video transmission technology is one of the key technologies for transmitting video between video processing equipment, video acquisition equipment, and video display equipment. The video from aerospace vehicles originates from various onboard video acquisition devices, characterized by a large number of videos but relatively low bandwidth per video stream. When using high-speed digital video transmission technology between video processing and display devices, because it is compatible with high-speed transmission rate standards, there is often a large bandwidth margin. By utilizing this bandwidth margin through time-division multiplexing, the video processing equipment can transmit the acquired video to the display device via a single high-speed link using time-division multiplexing. Summary of the Invention

[0003] The purpose of this invention is to provide a high-speed link time-division multiplexing circuit based on video ID, which uses line buffering to realize video packet transmission in turn, thereby improving the utilization rate of video transmission bandwidth. At the same time, it only needs to buffer video lines, so that video transmission can be realized in a shorter time. This circuit is easy to implement on a programmable logic device.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] A high-speed link time-division multiplexing circuit based on video ID includes a transmitter and a receiver. The transmitter includes a video transmission line buffer, a cyclic priority arbiter, a framing module, and a high-speed link transmission interface. Parallel video streams from different channels are first buffered in their respective video transmission line buffers in a line-buffered manner. The cyclic priority arbiter reads the data in the non-empty video line buffers according to the state of each video line buffer, marks them with video IDs, and then sends them to the framing module for framing. Finally, the data is serially transmitted to the high-speed link through the high-speed link transmission interface. After decoding, the receiver allocates the video to different video reception line buffers according to the video IDs for video reconstruction and output.

[0006] Preferably, the cyclic priority arbiter sequentially scans each video transmission line buffer, reads video data of one frame length from the non-empty video transmission line buffer according to the agreed frame format, marks the video ID according to different channels, and then sends it to the framing module.

[0007] Preferably, the video transmission line buffer contains two independent sub-line buffers. After receiving the parallel video signal input on the corresponding channel, the video is written to one sub-line buffer through ping-pong operation, and then the full sub-line buffer is notified to the cyclic valid arbitrator and the video is continued to be written to the other sub-line buffer.

[0008] The round-robin arbiter first checks if one of the sub-line buffers is full. If it is full, it reads video data of one frame length from the sub-line buffer. Otherwise, it checks the other sub-line buffer. If the other sub-line buffer is also not full, it scans the next video send line buffer.

[0009] Preferably, the framing module encapsulates the video data according to the agreed frame format and generates control code indicator flags according to the 8b / 10b encoding requirements, which are then sent to the high-speed link transmission interface together with the data frames;

[0010] The high-speed link transmission interface transcodes the received data into 8b / 10b format and converts the parallel data into high-speed serial data for transmission.

[0011] Preferably, the receiving end includes a high-speed link receiving interface, a frame deframe module, a pixel decoding allocation module based on video ID, a video receiving line buffer, and a video timing reconstruction module;

[0012] The high-speed link receiving interface decodes the received high-speed serial data into 8b / 10b and transcodes the serial data into parallel data and 8b / 10b control code indication flags.

[0013] The frame decoding module decodes the received data frames to extract the payload data and extracts the video resolution and video ID of each video channel.

[0014] The pixel decoding allocation module based on video ID reallocates video data according to video ID to form various video stream data, and writes the video to the corresponding video receiving line buffer.

[0015] The video receiving line buffer receives the valid video data stream and reassembles the video pixel data that has been split into multiple frames into one line of data.

[0016] The video timing reconstruction module regenerates the parallel video signal based on the received video resolution and frame rate, and generates data valid flag signals as well as line valid signals and field valid flag signals.

[0017] The beneficial effects of this invention are as follows:

[0018] Compared to the traditional high-speed link single-channel single-video transmission method, the multi-video source multiplexing single-link transmission method has the following advantages: 1. Improves bandwidth utilization; 2. Reduces transmission link complexity, reduces line cost and weight; 3. Reduces the number of high-speed links, thereby reducing material costs and overall power consumption. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a high-speed link time-division multiplexing circuit based on video ID.

[0020] Figure 2 This is a schematic diagram of a video ID-based link time-division multiplexing circuit applied to a video processing system. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0022] See Figure 1 As shown in the figure, this embodiment illustrates a high-speed link time-division multiplexing circuit based on video ID, which implements video packet transmission through line buffering. It includes a transmitter and a receiver. The transmitter includes a video transmission line buffer, a round-first arbiter, a framing module, and a high-speed link transmission interface. The receiver includes a high-speed link reception interface, a frame deframing module, a pixel decoding and allocation module based on video ID, a video reception line buffer, and a video timing reconstruction module. Video streams from different channels are first buffered in their respective video transmission line buffers using line buffering. The round-first arbiter, based on the state of each video line buffer, sequentially reads data from non-empty video line buffers, marks them with video IDs, and then sends them to the framing module for framing. Finally, the data is transmitted to the high-speed link through the high-speed link transmission interface. After decoding, the receiver allocates the video streams to different video reception line buffers according to the video IDs for video reconstruction and output.

[0023] Video transmission line buffer: Receives parallel digital RGB signals input from the onboard video acquisition device on the corresponding channel. In this embodiment, the video transmission line buffer contains two independent sub-line buffer FIFOs. After the received valid video signal is filled in one sub-line buffer FIFO through a ping-pong operation, the filled FIFO is notified to the cyclic valid arbitrator, and video continues to be written to the other sub-line buffer FIFO.

[0024] The cyclic priority arbiter sequentially scans each video transmit line buffer, reads one frame of video data from a non-empty buffer according to a pre-defined frame format (e.g., ADVB, Aviation Digital Video Bus), labels it with a video ID based on different channels, and then sends it to the framing module. In this embodiment, since each video transmit line buffer contains two independent sub-line buffer FIFOs, the cyclic priority arbiter first determines whether one sub-line buffer FIFO is full. If it is full, it reads one frame of video data from that sub-line buffer FIFO; otherwise, it checks the other sub-line buffer FIFO. If the other sub-line buffer FIFO is also not full, it scans the next video transmit line buffer.

[0025] The framing module's main function is to encapsulate video data according to the agreed frame format (such as ADVB) based on the FC-AV (fiber-optic audio-visual) frame header control protocol, and generate control code indicator flags according to 8b / 10b encoding requirements, which are then sent to the high-speed link transmission interface along with the ADVB format data frames.

[0026] High-speed link transmission interface: Its main function is to transcode the received data into 8b / 10b and convert parallel data into high-speed serial data for transmission.

[0027] High-speed link receiving interface: Its main function is to decode the received high-speed serial data into 8b / 10b and convert the serial data into parallel data and 8b / 10b control code indication flags.

[0028] The frame decoding module's main function is to decode the received ADVB format data frames according to the FC-AV frame header control protocol, decode the payload data, and extract information such as video resolution, video ID, and color frame rate for each video channel.

[0029] The pixel decoding and allocation module based on video ID: Its main function is to reallocate video data according to the video ID to form various video stream data, and write the video to the corresponding video receiving line buffer.

[0030] Video receive line buffer: Its main function is to receive valid video data streams and recombine video pixel data that has been split into multiple ADVB frames into one line of data.

[0031] Video timing reconstruction module: Its main function is to regenerate parallel digital RGB signals based on the received video resolution and frame rate, and generate data valid flag signals as well as line valid signals and field valid flag signals.

[0032] See Figure 2 As illustrated, this embodiment applies a high-speed link time-division multiplexing circuit based on video ID to the ARINC818 video network transmission scheme of the cockpit display and control system. The in-cabin / outside cameras are used to monitor and record the activity status of personnel in the cockpit and the status information of landing gear, weapon racks, etc. outside the cockpit; the photoelectric detection equipment is used to detect infrared targets and provide guidance for the pilot to find and lock onto targets; the DAS system provides the pilot with 360-degree all-round environmental situational awareness through multiple cameras distributed around the fuselage.

[0033] The camera uses a 1024×768 resolution, 24-bit monochrome pixel format, and a 60Hz refresh rate. The required transmission bandwidth is: BW = 1024×768×24×60 ≈ 1.14Gbps, while the ARINC818 video transmission channel supports a maximum of 4.25Gbps. Using one ARINC818 fiber optic channel for video transmission and reception with one camera would be a significant waste of bandwidth and would also increase the number of interconnecting cables between devices. Therefore, we can use a time-division multiplexing method to transmit multiple camera videos through a single fiber optic link.

[0034] This video processing system is divided into a video processing unit and a task processing unit. Both units utilize FPGAs to implement the transmission and reception processing chips for high-speed transmission of multiple video channels. Within the video processing unit, sensor video is converted into parallel digital RGB video by a decoding chip and input to the FPGA. The FPGA performs video gating and allocation, dividing the eight input video channels into four groups of two videos each, with video IDs marked as 0 and 1. These two video channels are transmitted via a time-division multiplexed high-speed serial bus. The task processing unit uses the FPGA to receive the high-speed video link, decodes the two video channels based on their video IDs, and sends them to the display according to the task assigned by the task unit.

[0035] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A high-speed link time-division multiplexing circuit based on video ID, comprising a transmitter and a receiver, characterized in that... The sending end includes a video transmission line buffer, a round-robin arbitrator, a framing module, and a high-speed link transmission interface; Parallel video streams from different channels are first buffered in their respective video transmission line buffers in a line-buffered manner. The round-robin arbiter reads the data in the non-empty video line buffers in turn according to the state of each video line buffer, marks the video IDs, and then sends them to the framing module for framing. If the video transmission line buffer contains two independent sub-line buffers, after receiving the parallel video signal input on the corresponding channel, the video is written to one sub-line buffer through ping-pong operation, and then the full sub-line buffer is notified to the cyclic valid arbitrator and the video is continued to be written to the other sub-line buffer. The round-robin arbiter first checks whether one of the sub-line buffers is full. If it is full, it reads video data of one frame length from the sub-line buffer. Otherwise, it checks the other sub-line buffer. If the other sub-line buffer is also not full, it scans the next video send line buffer. Finally, the video is serially transmitted to the high-speed link via the high-speed link transmission interface. After decoding, the receiving end allocates the video to different video receiving line buffers according to the video ID for video reconstruction and output. The receiving end includes a high-speed link receiving interface, a frame deframe module, a pixel decoding and allocation module based on video ID, a video receiving line buffer, and a video timing reconstruction module; The high-speed link receiving interface decodes the received high-speed serial data into 8b / 10b data and transcodes the serial data into parallel data and 8b / 10b control code indication flags. The frame decoding module decodes the received data frames to extract the payload data and extracts the video resolution and video ID of each video channel. The pixel decoding allocation module based on video ID reallocates video data according to video ID to form various video stream data, and writes the video to the corresponding video receiving line buffer. The video receiving line buffer receives the valid video data stream and reassembles the video pixel data that has been split into multiple frames into one line of data. The video timing reconstruction module regenerates the parallel video signal based on the received video resolution and frame rate, and generates data valid flag signals as well as line valid signals and field valid flag signals.

2. The high-speed link time-division multiplexing circuit based on video ID according to claim 1, characterized in that... The cyclic priority arbiter sequentially scans each video transmission line buffer, reads video data of one frame length from the non-empty video transmission line buffer according to the agreed frame format, marks the video ID according to different channels, and then sends it to the framing module.

3. The high-speed link time-division multiplexing circuit based on video ID according to claim 1, characterized in that... The framing module encapsulates the video data according to the agreed frame format and generates control code indicator flags according to the 8b / 10b encoding requirements, which are then sent to the high-speed link transmission interface along with the data frames. The high-speed link transmission interface transcodes the received data into 8b / 10b format and converts the parallel data into high-speed serial data for transmission.

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