Gate circuits and display devices

Abstract

Embodiments of this disclosure relate to a gate circuit and a display device. The display device includes a display panel and a plurality of gate circuits. Each gate circuit includes: a pull-up transistor controlled by a Q node and electrically connected between an input terminal of a first gate signal and an output terminal of a scan signal; a pull-down transistor controlled by a QB node and electrically connected between the output terminal of the scan signal and an input terminal of a first gate drive voltage; a first switching transistor controlled by a Q1 node electrically connected to the Q node and electrically connected between an input terminal of a second gate signal and the QB node; a second switching transistor controlled by the second gate signal and electrically connected between an input terminal of a third gate signal and the Q1 node; and a first capacitor, one terminal of which is electrically connected to the Q node.

Description

[0001] This application is a divisional application of National Application No. 202110882254.0, filed on August 2, 2021, entitled "Gate Circuit and Display Device".

[0002] Cross-reference to related applications

[0003] This application claims priority to Korean Patent Application No. 10-2020-0165745, filed on December 1, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0004] Embodiments of this disclosure relate to gate circuits and display devices. Background Technology

[0005] The development of the information society has led to an increased demand for display devices that display images and the use of various types of display devices (e.g., liquid crystal displays, organic light-emitting displays, etc.).

[0006] The display device may include: a display panel having multiple gate lines, multiple data lines, and multiple sub-pixels; and various driving circuits for driving the display panel. For example, the display device may include a gate driving circuit for driving the multiple gate lines, a data driving circuit for driving the multiple data lines, and a controller for controlling the gate driving circuit and the data driving circuit.

[0007] The gate drive circuit can provide a scan signal to the gate line at a predetermined time and can control the driving timing of the sub-pixels connected to the gate line.

[0008] The gate drive circuit may include various circuit elements for outputting a scan signal. These circuit elements degrade over time, and this degradation can lead to output defects in the scan signal.

[0009] Since the driving timing of sub-pixels is controlled by the scan signal provided by the gate drive circuit, defects in the image displayed on the display panel may occur when a defect occurs in the output of the scan signal.

[0010] Therefore, methods are needed to enhance the output stability and improve the reliability of the scan signal of the gate drive circuit. Summary of the Invention

[0011] Embodiments of this disclosure provide a method for reducing the degradation of circuit elements included in a gate drive circuit and enhancing the output stability of the scan signal of the gate drive circuit.

[0012] Embodiments of this disclosure also provide a method that can improve the reliability of the gate drive circuit by enabling the gate drive circuit to stably provide a scan signal, even if the circuit elements included in the gate drive circuit degrade.

[0013] In one aspect, embodiments of this disclosure provide a display device, comprising: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels disposed thereon; and a plurality of gate circuits driving the plurality of gate lines, wherein each of the plurality of gate circuits comprises: a pull-up transistor controlled by a Q node and electrically connected between an input terminal of a first gate clock signal and an output terminal of a scan signal; a pull-down transistor controlled by a QB node and electrically connected between the output terminal of the scan signal and an input terminal of a first gate drive voltage; a first switching transistor controlled by a Q1 node electrically connected to the Q node and electrically connected between an input terminal of a second gate clock signal and a QB node; and a bootstrap capacitor electrically connected between the Q1 node and the input terminal of the first gate clock signal.

[0014] In another aspect, embodiments of this disclosure provide a gate circuit comprising: a pull-up transistor controlled by a Q node and electrically connected between an input terminal of a first gate clock signal and an output terminal of a scan signal; a pull-down transistor controlled by a QB node and electrically connected between the output terminal of the scan signal and an input terminal of a first gate drive voltage; a switching transistor controlled by a Q1 node electrically connected to the Q node and electrically connected between an input terminal of a second gate clock signal and a QB node; and a bootstrap capacitor electrically connected between the Q1 node and the input terminal of the first gate clock signal.

[0015] In another aspect, embodiments of this disclosure provide a gate circuit, comprising: a pull-up transistor controlled by a Q node and electrically connected between an input terminal of a first gate clock signal and an output terminal of a scan signal; a pull-down transistor controlled by a QB node and electrically connected between the output terminal of the scan signal and an input terminal of a first gate drive voltage; a dummy transistor electrically connected between a Q node and a Q1 node; a Q node capacitor electrically connected between a Q node and the output terminal of the scan signal; and a bootstrap capacitor electrically connected between a Q1 node and the input terminal of the first gate clock signal.

[0016] According to various embodiments of this disclosure, since the switching transistor used to control the refresh of the QB node is controlled by a Q1 node different from the Q node, the degradation of the switching transistor can be reduced.

[0017] According to various embodiments of this disclosure, since a bootstrap capacitor is arranged between the Q1 node and the input terminal of the gate clock signal, the driving stability of the switching transistor controlled by the Q1 node can be enhanced, and refresh defects of the QB node can be prevented, thereby improving the reliability of the gate drive circuit.

[0018] According to various embodiments of this disclosure, by providing a bootstrap capacitor between the Q1 node (different from the Q node) and the input terminal of the gate clock signal used to output the scan signal, the voltage level of the Q1 node can be stably maintained at the output timing of the scan signal. Therefore, the drive state of the switching transistor controlled by the Q1 node and controlling the QB node can be stably controlled, thus preventing refresh defects in the QB node and enabling a stable output of the scan signal, thereby improving the reliability of the gate circuit. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a diagram schematically illustrating the configuration included in a display device according to an embodiment of the present disclosure;

[0021] Figure 2 This is a diagram schematically illustrating the configuration of the gate circuitry included in a gate drive circuitry according to an embodiment of the present disclosure.

[0022] Figure 3 This is a diagram illustrating an example of the structure of a gate circuit according to an embodiment of the present disclosure;

[0023] Figure 4 It is shown Figure 3 A diagram showing an example of the drive waveform for the gate circuit;

[0024] Figure 5 This is a diagram illustrating another example of the structure of a gate circuit according to an embodiment of the present disclosure;

[0025] Figures 6 to 11 It is shown Figure 5 A diagram illustrating an example of a driving scheme for the gate circuit; and Figure 12 It is shown Figure 5 A diagram showing an example of the W / L of the switching transistors included in the gate circuit. Detailed Implementation

[0026] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and the same reference numerals may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such detailed descriptions might obscure the subject matter of some embodiments of this disclosure. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0028] When referring to the first element and the second element as "connected or coupled," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlapping," etc., with each other.

[0029] When time-related terms (such as “after,” “following,” “next,” “before,” etc.) are used to describe the process or operation of an element or configuration, or the flow or step in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately after.”

[0030] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of a component or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is provided. Additionally, the term "may" fully encompasses all the meanings of the term "can."

[0031] Figure 1This is a schematic diagram illustrating the configuration included in a display device 100 according to an embodiment of the present disclosure. All components of the display device 100 according to all embodiments of the present disclosure are operatively coupled and configured.

[0032] Reference Figure 1 The display device 100 may include a display panel 110 and a gate driving circuit 120, a data driving circuit 130 and a controller 140 for driving the display panel 110.

[0033] The display panel 110 may include an active area AA with multiple sub-pixels SP and a non-active area NA located outside the active area AA.

[0034] Multiple gate lines GL and multiple data lines DL can be arranged on the display panel 110. Multiple sub-pixels SP can be located in the area where the gate lines GL and data lines DL intersect.

[0035] The gate drive circuit 120 is controlled by the controller 140 and outputs the scan signal sequentially to multiple gate lines GL arranged on the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0036] The gate drive circuit 120 may include one or more gate driver integrated circuits (GDICs) (not shown), and depending on the driving method, it may be located only on one side of the display panel 110, or it may be located on both sides of the display panel 110.

[0037] Each gate driver integrated circuit (GDIC) can be connected to the bonding pads of the display panel 110 via tape automated bonding (TAB) or chip-on-glass (COG) methods, or it can be implemented via gate-in-panel (GIP) methods, thus being directly disposed on the display panel 110. In some cases, the gate driver integrated circuit (GDIC) can be integrated and disposed on the display panel 110. Furthermore, each gate driver integrated circuit (GDIC) can be implemented via chip-on-film (COF) methods, in which components are mounted on a film connected to the display panel 110.

[0038] The data driving circuit 130 receives image data from the controller 140 and converts the image data into an analog data voltage Vdata. Then, the data driving circuit 130 outputs the data voltage Vdata to each data line DL according to the timing of the scan signal applied through the gate line GL, so that each sub-pixel in the plurality of sub-pixels SP emits light with a brightness according to the image data.

[0039] The data drive circuit 130 may include one or more source driver integrated circuits (SDICs) (not shown).

[0040] Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc.

[0041] Each source driver integrated circuit (SDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-a-brush (TAB) method or a chip-on-glass (COG) method, or it can be directly disposed on the display panel 110. Alternatively, in some cases, the source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method, in which each source driver integrated circuit (SDIC) can be mounted on a film connected to the display panel 110 and electrically connected to the display panel 110 via wiring on the film.

[0042] The controller 140 provides various control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130.

[0043] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the gate drive circuit 120 and the data drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0044] The controller 140 allows the gate drive circuit 120 to output a scan signal according to a timing implemented per frame, and converts the data signal received from the outside into a data signal format that conforms to the data drive circuit 130, and then outputs the converted image data to the data drive circuit 130.

[0045] The controller 140 receives various timing signals, including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal DE, clock signal CLK, etc., and image data from an external source (e.g., a host system).

[0046] The controller 140 can use various timing signals received from the outside to generate various control signals, and can output the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0047] For example, in order to control the gate drive circuit 120, the controller 140 outputs various gate control signals GCS, including the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, etc.

[0048] The gate start pulse (GSP) controls the start timing of operation of one or more gate driver integrated circuits (GDICs) constituting the gate drive circuit 120. The gate shift clock (GSC), which serves as a common input to one or more gate driver integrated circuits (GDICs), controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information for one or more gate driver integrated circuits (GDICs).

[0049] In addition, in order to control the data drive circuit 130, the controller 140 outputs various data control signals DCS, including the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE.

[0050] The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SSC is a clock signal used to control the timing of the sampled data in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0051] The display device 100 may also include a power management integrated circuit, which is used to provide various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or to control the various voltages or currents to be provided to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc.

[0052] Each of the multiple sub-pixels SP can be an area defined by the intersection of gate line GL and data line DL, and liquid crystal or light-emitting elements can be disposed therein depending on the type of display device 100.

[0053] For example, if the display device 100 is a liquid crystal display device, the display panel 110 may include a liquid crystal layer. Furthermore, by controlling the arrangement of the liquid crystal according to the field formed by each of the plurality of sub-pixels SP, the brightness of the sub-pixels SP can be controlled, and an image can be displayed.

[0054] As another example, when the display device 100 is an organic light-emitting display device, organic light-emitting diodes (OLEDs) and various circuit elements can be disposed on multiple sub-pixels SP. When the current supplied to the organic light-emitting diodes (OLEDs) disposed on the sub-pixels SP is controlled by the various circuit elements, each sub-pixel SP can represent a brightness corresponding to image data.

[0055] Alternatively, in some cases, light-emitting diodes (LEDs) or micro LEDs (μLEDs) can be disposed on sub-pixels (SPs).

[0056] As described above, the display device 100 can control the driving timing of the sub-pixel SP according to the scanning signal provided by the gate driving circuit 120, and can display images through the display panel 110.

[0057] The gate drive circuit 120 can output scan signals to multiple gate lines GL and can include multiple gate circuits that control each of the multiple gate lines GL.

[0058] Figure 2 This is a diagram schematically illustrating the configuration of the gate circuitry included in the gate drive circuitry 120 according to an embodiment of the present disclosure.

[0059] Reference Figure 2 The gate circuit may include a pull-up transistor Tup controlled by the Q node and a pull-down transistor Tdn controlled by the QB node. The pull-up transistor Tup controls the output of the on-level scan signal, and the pull-down transistor Tdn controls the output of the off-level scan signal.

[0060] The gate circuit may include a plurality of transistors and at least one capacitor for controlling the voltage level of the Q node and the voltage level of the QB node.

[0061] The gate circuit can receive various signals and voltages, and can output a scan signal according to the operation of the pull-up transistor Tup and the pull-down transistor Tdn.

[0062] For example, the gate circuit may receive a gate start signal VST for controlling drive timing and at least one gate clock signal GCLK. The gate start signal VST may be a carry signal output from other gate circuits.

[0063] The gate circuit can receive one or more drive voltages, and can receive a first gate drive voltage VGH and a second gate drive voltage VGL. For example, the first gate drive voltage VGH can be a high-level drive voltage, and the second gate drive voltage VGL can be a low-level drive voltage.

[0064] The gate circuit can control the Q node and QB node by receiving various signals and voltages, and can output a scan signal at a predetermined time.

[0065] The circuit elements controlling the Q-node and QB-node in the gate circuit can be configured in various ways and can be configured according to the gate drive circuit to minimize the degradation of the circuit elements.

[0066] Figure 3 This is a diagram illustrating an example of the structure of a gate circuit according to an embodiment of the present disclosure.

[0067] Reference Figure 3 The gate circuit may include multiple transistors Tup, Tdn, T11, T12, T21, T22, T3, T4, T5, Tdmy and at least one capacitor CQ, CQB.

[0068] Figure 3 Examples are shown where each of the multiple transistors included in the gate circuit is P-type; in some cases, at least some of the multiple transistors included in the gate circuit may be N-type. Furthermore, Figure 3 The example illustrates a case where some transistors in the gate circuit are configured as dual transistors. If desired, the multiple transistors in the gate circuit can be configured as a single transistor or dual transistors.

[0069] The gate circuit may include a pull-up transistor Tup and a pull-down transistor Tdn that control the output of the scan signal to the gate line GL.

[0070] The pull-up transistor Tup can be electrically connected between the input terminal of the first gate clock signal GCLK1 and the output terminal SCOUT(n) of the scan signal. The pull-up transistor Tup can be controlled by the Q node.

[0071] The pull-down transistor Tdn can be electrically connected between the output terminal SCOUT(n) of the scan signal and the input terminal of the first gate drive voltage VGH. The pull-down transistor Tdn can be controlled by the QB node.

[0072] The gate circuit may include various circuit elements for controlling the Q node and QB node.

[0073] The first switching transistors T11 and T12 can be electrically connected between the input terminal of the second gate clock signal GCLK2 and the QB node. The first switching transistors T11 and T12 can be controlled by the Q1 node.

[0074] The first switching transistors T11 and T12 can be in the on or off state according to the voltage level of node Q1, and can also control the voltage level of node QB.

[0075] The second switching transistors T21 and T22 can be electrically connected between the input terminal of the gate start signal VST and the Q1 node. The second switching transistors T21 and T22 can be controlled by the second gate clock signal GCLK2.

[0076] The second switching transistors T21 and T22 can be in the on or off state according to the second gate clock signal GCLK2, and can control the voltage level of node Q1.

[0077] The third switching transistor T3 can be electrically connected between node Q1 and the fourth switching transistor T4. The third switching transistor T3 can be controlled by the first gate clock signal GCLK1.

[0078] The fourth switching transistor T4 can be electrically connected between the third switching transistor T3 and the input terminal of the first gate drive voltage VGH. The fourth switching transistor T4 can be controlled by the QB node.

[0079] The fifth switching transistor T5 can be electrically connected between the input terminal of the second gate drive voltage VGL and the QB node. The fifth switching transistor T5 can be controlled by the second gate clock signal GCLK2.

[0080] The gate circuit may include a Q-node capacitor CQ electrically connected between the Q-node and the output terminal of the scan signal. The gate circuit may include a QB-node capacitor CQB electrically connected between the QB-node and the input terminal of the first gate drive voltage VGH.

[0081] The gate circuit may also include a pseudo transistor Tdmy in addition to the switching transistors described above.

[0082] The dummy transistor Tdmy can be electrically connected between the Q node and the Q1 node. The gate node of the dummy transistor Tdmy can be electrically connected to the input terminal of the second gate drive voltage VGL. The dummy transistor Tdmy can be controlled according to the second gate drive voltage VGL.

[0083] When the second gate drive voltage VGL, which serves as a low-potential drive voltage, is supplied to the gate node of the dummy transistor Tdmy, the dummy transistor Tdmy can remain in the on state during the drive period of the gate circuit.

[0084] The pseudo transistor Tdmy can remain on during the drive period of the gate circuit and can function as a resistor between the Q node and the Q1 node.

[0085] When the voltage level of the Q node, which forms a capacitance with the output terminal of the scan signal via the Q node capacitor CQ, changes at the timing of the output scan signal, the degree of change in the voltage level of the Q1 node can be reduced by using the pseudo transistor Tdmy.

[0086] Therefore, the stress applied to the first switching transistors T11 and T12 due to the change in the voltage level of node Q1 at the timing of the output scan signal can be reduced.

[0087] Figure 4 It is shown Figure 3 A diagram showing an example of the drive waveform for the gate circuit.

[0088] Reference Figure 4 In case A, the first gate clock signal GCLK1 and the second gate clock signal GCLK2 have different phases.

[0089] The gate start signal VST can be used as a low-level input during the first time period P1.

[0090] Since the second gate clock signal GCLK2 is low during the first period P1, the second switching transistors T21 and T22 can be in the on state.

[0091] Since the second switching transistors T21 and T22 become on, the gate start signal VST can be provided to node Q1. Based on the gate start signal VST, node Q1 can be at a low level.

[0092] Since the pseudo transistor Tdmy remains on during the drive period of the gate circuit, if node Q1 goes low, node Q can also go low.

[0093] Since node Q1 goes low, the first switching transistors T11 and T12 controlled by node Q1 can be in the on state.

[0094] Since the first switching transistors T11 and T12 are turned on, the second gate clock signal GCLK2 can be provided to the QB node. Based on the second gate clock signal GCLK2, the QB node can be at a low level.

[0095] Since both Q node and QB node are at a low level during the first time period P1, both pull-up transistor Tup and pull-down transistor Tdn can be in the on state.

[0096] In the second time period P2, the levels of the first gate clock signal GCKL1, the second gate clock signal GCLK2, and the gate start signal VST can be changed.

[0097] Since the second gate clock signal GCLK2 is high during the second time period P2, the second switching transistors T21 and T22 can be in the off state.

[0098] Since nodes Q1 and Q1 remain at a low level during the second time period P2, the first switching transistors T11 and T12 can remain on.

[0099] Since the first switching transistors T11 and T12 remain on, the second gate clock signal GCLK2 can be provided to the QB node. Based on the second gate clock signal GCLK2, the QB node can go high.

[0100] Since node Q is low during the second time period P2, the pull-up transistor Tup can remain on. Since node QB is high during the second time period P2, the pull-down transistor Tdn can be off.

[0101] Since the pull-up transistor Tup is in the on state during the second time period P2 and the first gate clock signal GCLK1 is low, the low-level scan signal can be output to the output terminal of the scan signal.

[0102] Based on the low-level scan signal output, the voltage level of the Q node can be further reduced. Since the dummy transistor Tdmy is located between the Q1 node and the Q node, the Q1 node can maintain its previous voltage level even if the voltage level of the Q node becomes lower.

[0103] Therefore, it is possible to prevent stress from being applied to the first switching transistors T11 and T12 based on the change in the voltage level of the Q node when outputting a low-level scan signal.

[0104] As described above, by reducing the stress applied to the first switching transistors T11 and T12, degradation of the first switching transistors T11 and T12 can be prevented or delayed. However, degradation of the first switching transistors T11 and T12 may occur as the driving time increases.

[0105] In this situation, due to the change in the threshold voltage of the first switching transistors T11 and T12, the operation control of the first switching transistors T11 and T12 may not be executed normally.

[0106] For example, such as Figure 4 In the example shown in case B, the first switching transistors T11 and T12 cannot remain in the on state during the second time period P2.

[0107] If the first switching transistors T11 and T12 turn off during the second time period P2, the high-level second gate clock signal GCLK2 cannot be provided to the QB node, and the QB node can remain low.

[0108] Since the QB node is at a low level, the fourth switching transistor T4 and the pull-down transistor Tdn can remain on.

[0109] Since the third switching transistor T3 becomes on during the second time period P2 through the low-level first gate clock signal GCLK1, the first gate drive voltage VGH can be provided to the Q node through the fourth switching transistor T4 and the third switching transistor T3.

[0110] When nodes Q1 and Q go high, the pull-up transistor Tup can be turned off.

[0111] Since the pull-up transistor Tup is turned off and the pull-down transistor Tdn is turned on, a high-level scan signal can be output to the output terminal of the scan signal.

[0112] Because the gate circuit cannot output a low-level scan signal at a predetermined timing, a driving defect may occur in the sub-pixel SP driven by the gate line GL connected to the corresponding gate circuit.

[0113] According to embodiments of the present disclosure, a method is provided that can delay the degradation of the first switching transistors T11 and T12 controlling the QB node and stably output a scan signal even when the first switching transistors T11 and T12 degrade due to the increase in the driving time of the gate circuit.

[0114] Figure 5 This is a diagram illustrating another example of the structure of a gate circuit according to an embodiment of the present disclosure.

[0115] Reference Figure 5 The gate circuit may include multiple transistors Tup, Tdn, T11, T12, T21, T22, T3, T4, T5, Tdmy and at least one capacitor CQ, CQB, CQ1.

[0116] The gate circuit may include a pull-up transistor Tup and a pull-down transistor Tdn to control the output of the scan signal. The connection structure and driving method of the pull-up transistor Tup and the pull-down transistor Tdn can be consistent with... Figure 3 The connection structure and driving method of the described gate circuit are the same.

[0117] The gate circuit may include multiple transistors T11, T12, T21, T22, T3, T4, T5, and Tdmy that control the voltage levels of the Q-node and QB-node. The connection structure and driving method of the multiple transistors T11, T12, T21, T22, T3, T4, T5, and Tdmy can be... Figure 3 The connection structure and driving method of the described gate circuit are the same.

[0118] The gate circuit may include a Q-node capacitor CQ electrically connected between the Q-node and the output terminal SCOUT(n) of the scan signal. The gate circuit may include a QB-node capacitor CQB electrically connected between the QB-node and the input terminal of the first gate drive voltage VGH.

[0119] The gate circuit may include a Q1 node capacitor CQ1 electrically connected between the Q1 node and the input terminal of the first gate clock signal GCLK1.

[0120] One end of capacitor CQ1 at node Q1 can be electrically connected to node Q1.

[0121] The other end of the capacitor CQ1 at node Q1 can be electrically connected to the input terminal of the first gate clock signal GCLK1.

[0122] The input terminal of the first gate clock signal GCLK1 can refer to the input terminal of the first gate clock signal GCLK1 electrically connected to the gate node of the third switching transistor T3. Alternatively, the input terminal of the first gate clock signal GCLK1 can refer to the input terminal of the first gate clock signal GCLK1 electrically connected to the pull-up transistor Tup.

[0123] The line that supplies the first gate clock signal GCLK1 to the third switching transistor T3 and the line that supplies the first gate clock signal GCLK1 to the pull-up transistor Tup can be the same or different from each other.

[0124] The Q1 node can form a capacitance with the Q1 node capacitor CQ1 and the input terminal of the first gate clock signal GCLK1. The voltage level of the Q1 node can be changed according to the level of the first gate clock signal GCLK1.

[0125] Therefore, since a low-level first gate clock signal GCLK1 is provided at the timing of the low-level scan signal, the voltage level of node Q1 can be kept low.

[0126] Since the capacitor CQ1 at node Q1 maintains the low level of node Q1 through bootstrapping, the first switching transistors T11 and T12 can remain in the on state.

[0127] Since the first switching transistors T11 and T12 remain on, the second gate clock signal GCLK2, which is high-level for the QB node, can be provided normally.

[0128] Since a high-level voltage is properly applied to the QB node, the fourth switching transistor T4 and the pull-down transistor Tdn can remain off.

[0129] Therefore, the levels of Q1 node and Q node can be maintained stably, and a low-level scan signal can be output normally through the output terminal of the scan signal.

[0130] The capacitance of capacitor CQ1 at node Q1 can be configured to stably control the voltage level of node Q1. The capacitance of capacitor CQ1 at node Q1 can be the same as or different from the capacitance of capacitor CQ at node Q.

[0131] Figures 6 to 11 It is shown Figure 5 A diagram illustrating an example of a driving scheme for the gate circuit.

[0132] Reference Figure 6 In the driving timing diagram of the gate circuit, during the period corresponding to ①, the first gate clock signal GCLK1 can be high, the second gate clock signal GCLK2 can be low, and the gate start signal VST can be high.

[0133] Since the first gate clock signal GCLK1 is high, the third switching transistor T3 can be in the off state.

[0134] Since the second gate clock signal GCLK2 is low, the second switching transistors T21 and T22 and the fifth switching transistor T5 can be in the on state.

[0135] Since the second switching transistors T21 and T22 are in the ON state, a high-level gate start signal VST can be provided to node Q1. Since node Q1 is high, the first switching transistors T11 and T12 can be in the OFF state.

[0136] Since the dummy transistor Tdmy is kept on by the second gate drive voltage VGL, the Q node can be at the same high level as the Q1 node. Because the Q node is high, the pull-up transistor Tup can be off.

[0137] Since the fifth switching transistor T5 is in the on state, the second gate drive voltage VGL can be provided to the QB node.

[0138] Since the QB node is at a low level, the fourth switching transistor T4 and the pull-down transistor Tdn can be in the on state.

[0139] Since the pull-up transistor Tup becomes off and the pull-down transistor Tdn becomes on, the first gate drive voltage VGH can be output through the output terminal of the scan signal.

[0140] Reference Figure 7In the driving timing diagram of the gate circuit, during the period corresponding to ②, the first gate clock signal GCLK1 can be low, the second gate clock signal GCLK2 can be high, and the gate start signal VST can be high.

[0141] Since the first gate clock signal GCLK1 is low, the third switching transistor T3 can be in the on state.

[0142] Since the second gate clock signal GCLK2 is high, the second switching transistors T21 and T22 and the fifth switching transistor T5 can be in the off state.

[0143] Since the third switching transistor T3 becomes on when the fourth switching transistor T4 is on, the first gate drive voltage VGH can be provided to node Q1. Therefore, nodes Q1 and Q can remain at a high level.

[0144] Since node Q1 is at a high level, the first switching transistors T11 and T12 can remain off.

[0145] Since the Q node remains high and the QB node remains low, a high-level scan signal can be output by pulling down the transistor Tdn.

[0146] Reference Figure 8 In the driving timing diagram of the gate circuit, during the period corresponding to ③, the first gate clock signal GCLK1 can be high, the second gate clock signal GCLK2 can be low, and the gate start signal VST can be low.

[0147] Since the first gate clock signal GCLK1 is high, the third switching transistor T3 can be in the off state.

[0148] Since the second gate clock signal GCLK2 is low, the second switching transistors T21 and T22 and the fifth switching transistor T5 can be in the on state.

[0149] Since the second switching transistors T21 and T22 are turned on and the third switching transistor T3 is turned off, the low-level gate start signal VST can be provided to node Q1.

[0150] Since the pseudo transistor Tdmy remains on, the Q node can be at the same low level as the Q1 node.

[0151] Since node Q1 is at a low level, the first switching transistors T11 and T12 can be in the on state.

[0152] Since the first switching transistors T11 and T12 are turned on, the low-level second gate clock signal GCLK2 can be provided to the QB node. Furthermore, since the fifth switching transistor T5 is turned on, the low-level second gate drive voltage VGL can be provided to the QB node.

[0153] Since both the Q node and the QB node are at a low level, both the pull-up transistor Tup and the pull-down transistor Tdn can be in the on state.

[0154] The first gate clock signal GCLK1 can be output via the pull-up transistor Tup, and the first gate drive voltage VGH can be output via the pull-down transistor Tdn. Since both the first gate clock signal GCLK1 and the first gate drive voltage VGH are high, a high-level scan signal can be output.

[0155] Reference Figure 9 In the driving timing diagram of the gate circuit, during the period corresponding to ④, the first gate clock signal GCLK1 can be low, the second gate clock signal GCLK2 can be high, and the gate start signal VST can be high.

[0156] Since the first gate clock signal GCLK1 is low, the third switching transistor T3 can be in the on state.

[0157] Since the second gate clock signal GCLK2 is high, the second switching transistors T21 and T22 and the fifth switching transistor T5 can be in the off state.

[0158] Since the second switching transistors T21 and T22 are turned off, the gate start signal VST does not need to be provided to the Q1 node.

[0159] Therefore, node Q1 can remain low. Because node Q1 remains low, the first switching transistors T11 and T12 can remain on.

[0160] Since the first switching transistors T11 and T12 remain on, the high-level second gate clock signal GCLK2 can be provided to the QB node.

[0161] Since the fifth switching transistor T5 is in the off state, the second gate drive voltage VGL may not be provided to the QB node.

[0162] Therefore, nodes Q1 and Q remain low, while node QB can go high.

[0163] Furthermore, since the Q1 node capacitor CQ1 is positioned between the Q1 node and the input terminal of the first gate clock signal GCLK1, the low level of the Q1 node can be stably maintained.

[0164] Since the first gate clock signal GCLK1 is input at a low level during the corresponding period, the low level of node Q1, which forms a capacitor with the input terminal of the first gate clock signal GCLK1, can be stably maintained.

[0165] By stably maintaining the low level of node Q1, the first switching transistors T11 and T12 can be kept in the on state, and the refresh of node QB can be stably performed.

[0166] Since the QB node is high, the fourth switching transistor T4 and the pull-down transistor Tdn can be in the off state.

[0167] Since the Q node is at a low level, the pull-up transistor Tup can be in the on state.

[0168] Since the pull-up transistor Tup is in the on state, the first gate clock signal GCLK1 can be output through the output terminal of the scan signal.

[0169] Since the first gate clock signal GCLK1 is low, the level of the Q node can be further reduced based on the output of the first gate clock signal GCLK1 through the output terminal of the scan signal.

[0170] Since the pseudo transistor Tdmy is located between the Q node and the Q1 node, the voltage levels of the Q node and the Q1 node can be different from each other during the corresponding time period.

[0171] As described above, by placing a capacitor CQ1 at the Q1 node between the Q1 node and the input terminal of the first gate clock signal GCLK1, the low level of the Q1 node can be stably maintained at the timing of the output scan signal.

[0172] By stably maintaining the low level of node Q1, the conducting state of the first switching transistors T11 and T12 can be stably maintained.

[0173] Even if the threshold voltages of the first switching transistors T11 and T12 change due to the degradation of the first switching transistors T11 and T12, the QB node refresh can be performed stably and the scan signal can be output normally.

[0174] Reference Figure 10In the driving timing diagram of the gate circuit, during the period corresponding to ⑤, the first gate clock signal GCLK1 can be high, the second gate clock signal GCLK2 can be low, and the gate start signal VST can be high.

[0175] The third switching transistor T3 can be turned off by the first gate clock signal GCLK1. The second switching transistors T21 and T22 and the fifth switching transistor T5 can be turned on by the second gate clock signal GCLK2.

[0176] The Q1 node and the Q node can be brought high by a high-level gate start signal VST.

[0177] The QB node can be brought low by a low-level second gate drive voltage VGL.

[0178] Since node Q is high, the pull-up transistor Tup can be turned off, and since node QB is low, the pull-down transistor Tdn can be turned on.

[0179] Therefore, the high-level first gate drive voltage VGH can be output to the output terminal of the scan signal through the pull-down transistor Tdn.

[0180] Reference Figure 11 In the driving timing diagram of the gate circuit, during the period corresponding to ⑥, the first gate clock signal GCLK1 can be low, the second gate clock signal GCLK2 can be high, and the gate start signal VST can be high.

[0181] The third switching transistor T3 can be turned on by the first gate clock signal GCLK1. The second switching transistors T21 and T22 and the fifth switching transistor T5 can be turned off by the second gate clock signal GCLK2.

[0182] The Q1 node and the Q node can be kept high by the first gate drive voltage VGH provided via the fourth switching transistor T4 and the third switching transistor T3.

[0183] Since node Q1 is at a high level, the first switching transistors T11 and T12 can remain off. Therefore, node QB can remain at a low level.

[0184] Since the Q node remains high and the QB node remains low, the pull-up transistor Tup can remain off and the pull-down transistor Tdn can remain on.

[0185] Therefore, after the gate circuit outputs a low-level scan signal, a high-level scan signal can be maintained.

[0186] As described above, since the gate circuit stably maintains the voltage level of node Q1 through node capacitor CQ1 at the timing of the output scan signal, the gate circuit can output the scan signal normally at a predetermined timing and can stably maintain the off-level scan signal in subsequent time periods.

[0187] Note that, although in Figures 5 to 11 The diagram shows a gate circuit comprising multiple transistors T11, T12, T21, T22, T3, T4, T5, and Tdmy. However, in some embodiments, the gate circuit may include only a subset of transistors T11, T12, T21, T22, T3, T4, T5, and Tdmy. Furthermore, as those skilled in the art will understand, the arrangement of the individual transistors is not limited to... Figures 5 to 11 The specific example shown is shown below.

[0188] Furthermore, while reducing the size of the switching transistor by arranging the Q1 node capacitor CQ1, a wider output margin can be configured according to the threshold voltage variation of the switching transistor.

[0189] Figure 12 It is shown Figure 5 The diagram shows an example of the W / L ratio of the switching transistor included in the gate circuit. The W / L ratio refers to the ratio of the width to the length of the channel region of the switching transistor.

[0190] Reference Figure 12 It shows the output margin based on the W / L ratio of the first switching transistor T1 and the W / L ratio of the second switching transistor T2, with and without the application of the Q1 node capacitor CQ1.

[0191] When the capacitor CQ1 at node Q1 is not applied to the gate circuit, it can be seen that when the W / L ratio of the second switching transistor T2 is 1.5, the output margin of the second switching transistor T2 is the largest, which is Δ11V. It can also be seen that when the W / L ratio of the first switching transistor T1 is 1.5, the output margin of the first switching transistor T1 is the largest, which is Δ9V.

[0192] When the Q1 node capacitor CQ1 is applied to the gate circuit, it can be seen that, at the same W / L ratio, the output margin of the second switching transistor T2 and the first switching transistor T1 is increased compared to the case where the Q1 node capacitor CQ1 is not applied to the gate circuit.

[0193] Furthermore, when the Q1 node capacitor CQ1 is applied to the gate circuit, and the W / L ratio is configured to be 0.8 to 1.0, it can be seen that the output margin of the first switching transistor T1 shifts along the (+) direction.

[0194] Therefore, when the Q1 node capacitor CQ1 is applied to the gate circuit, by configuring at least one of the W / L ratios of the first switching transistor T1 and the second switching transistor T2 to be 0.8 to 1.0, the output margin of the corresponding switching transistor can be configured more flexibly while reducing the size of the corresponding switching transistor.

[0195] According to embodiments of this disclosure, since the voltage levels of the Q1 node and the Q node are controlled differently by the dummy transistor Tdmy at the output timing of the scan signal, the stress applied to the first switching transistors T11 and T12 controlled by the Q1 node can be reduced.

[0196] Furthermore, by placing a capacitor CQ1 at the Q1 node between the Q1 node and the input terminal of the first gate clock signal GCLK1 used for the scan signal of the output gate circuit, the voltage level of the Q1 node can be stably maintained at the output timing of the scan signal.

[0197] Therefore, by stably controlling the driving states of the first switching transistors T11 and T12 controlled by the Q1 node and performing the refresh of the QB node, a scan signal with a conduction level can be stably output, and the reliability of the gate circuit can be improved.

[0198] For example, this disclosure may also include the following technical solutions.

[0199] Option 1. A display device, comprising:

[0200] A display panel, wherein the display panel is provided with multiple gate lines, multiple data lines and multiple sub-pixels; and

[0201] Multiple gate circuits that drive the multiple gate lines

[0202] Each of the plurality of gate circuits includes:

[0203] A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal;

[0204] A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage;

[0205] A first switching transistor, controlled by a Q1 node electrically connected to the Q node and electrically connected between the input terminal of the second gate clock signal and the QB node; and

[0206] A bootstrap capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal.

[0207] Option 2. The display device according to Option 1, wherein each of the plurality of gate circuits further includes:

[0208] The second switching transistor is controlled by the second gate clock signal and electrically connected between the input terminal of the gate start signal and the Q1 node.

[0209] Solution 3. The display device according to Solution 2, wherein, during a first time period in which the gate start signal is a level that turns on the first switching transistor, the first switching transistor and the second switching transistor are in the on state.

[0210] Option 4. The display device according to Option 3, wherein the pull-up transistor and the pull-down transistor are in the on state during the first time period.

[0211] Option 5. The display device according to Option 3, wherein, in the second time period following the first time period, the Q1 node and the Q node are maintained at a level that enables the pull-up transistor to conduct.

[0212] Solution 6. The display device according to Solution 5, wherein the first gate clock signal is at the on level during the second time period.

[0213] Solution 7. The display device according to Solution 5, wherein the voltage level of the Q1 node and the voltage level of the Q node are different from each other during the second time period.

[0214] Option 8. The display device according to Option 2, wherein at least one of the ratio of the width to the length of the channel region of the first switching transistor and the ratio of the width to the length of the channel region of the second switching transistor is greater than or equal to 0.8 and less than or equal to 1.

[0215] Option 9. The display device according to Option 2, wherein each of the plurality of gate circuits further includes:

[0216] A third switching transistor, the third switching transistor being controlled by the first gate clock signal and electrically connected to the Q1 node; and

[0217] A fourth switching transistor, which is controlled by the QB node and electrically connected between the third switching transistor and the input terminal of the first gate drive voltage.

[0218] Solution 10. The display device according to Solution 9, wherein, during a second time period following a first time period in which the gate start signal is at a level that turns on the first switching transistor, the third switching transistor is in an on state and the fourth switching transistor is in an off state.

[0219] Option 11. The display device according to Option 9, wherein the gate node of the third switching transistor is electrically connected to the bootstrap capacitor.

[0220] Option 12. The display device according to Option 1, wherein each of the plurality of gate circuits further includes:

[0221] A pseudo transistor electrically connected between the Q1 node and the Q node.

[0222] Option 13. The display device according to Option 12, wherein the dummy transistor is controlled by a second gate drive voltage.

[0223] Option 14. The display device according to Option 12, wherein the dummy transistor remains in an on state during the period when the gate circuit is driven.

[0224] Option 15. A gate circuit, comprising:

[0225] A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal;

[0226] A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage;

[0227] A switching transistor, said switching transistor being controlled by a Q1 node electrically connected to said Q node and electrically connected between the input terminal of the second gate clock signal and said QB node; and

[0228] A bootstrap capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal.

[0229] Option 16. The gate circuit according to Option 15, wherein, in the first time period, the switching transistor is turned on, the Q node is at a level that turns on the pull-up transistor, and the QB node is at a level that turns on the pull-down transistor, and

[0230] During the second period following the first period, the switching transistor remains on, the Q node remains at the level that turns on the pull-up transistor, and the QB node is at the level that turns off the pull-down transistor.

[0231] Option 17. The gate circuit according to Option 16, wherein the voltage level of the Q1 node and the voltage level of the Q node are different from each other during the second time period.

[0232] Solution 18. The gate circuit according to Solution 17, wherein, during the second time period, the voltage level of the Q1 node is maintained or changed according to the voltage level of the first gate clock signal, and the voltage level of the Q node is changed according to the voltage level of the output terminal of the scan signal.

[0233] Option 19. A gate circuit, comprising:

[0234] A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal;

[0235] A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage;

[0236] A pseudo transistor, which is electrically connected between the Q node and the Q1 node;

[0237] A Q-node capacitor, the Q-node capacitor being electrically connected between the Q-node and the output terminal of the scan signal; and

[0238] A bootstrap capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal.

[0239] Option 20. The gate circuit according to Option 19, wherein the dummy transistor remains in the on state during the period when at least one of the pull-up transistor and the pull-down transistor is in the on state.

[0240] Option 21. A display device comprising the gate circuit according to Option 19 or 20,

[0241] The display device further includes a display panel, on which multiple gate lines, multiple data lines, and multiple sub-pixels are disposed; and

[0242] The plurality of gate lines are driven by a plurality of gate circuits.

[0243] Option 22. The display device according to Option 21, wherein the gate circuit further includes a first switching transistor, the first switching transistor being controlled by the Q1 node and electrically connected between the input terminal of the second gate clock signal and the QB node.

[0244] The above description has been provided to enable any person skilled in the art to implement and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and figures provide examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as included within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel has multiple gate lines, multiple data lines and multiple sub-pixels. as well as Multiple gate circuits that drive the multiple gate lines Each of the plurality of gate circuits includes: A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal; A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage; The first switching transistor is controlled by a Q1 node electrically connected to the Q node and electrically connected between the input terminal of the second gate clock signal and the QB node. The second switching transistor, controlled by the second gate clock signal and electrically connected between the input terminal of the gate start signal and the Q1 node; and A first capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal. Wherein, at least one of the first switching transistor and the second switching transistor comprises two or more transistors.

2. The display device according to claim 1, wherein Each of the plurality of gate circuits further includes: A third switching transistor, the third switching transistor being controlled by the first gate clock signal and electrically connected to the Q1 node; and A fourth switching transistor, which is controlled by the QB node and electrically connected between the third switching transistor and the input terminal of the first gate drive voltage.

3. The display device according to claim 2, wherein The gate node of the third switching transistor is electrically connected to the first capacitor.

4. The display device according to claim 1, wherein At least one of the ratio of the width to the length of the channel region of the first switching transistor and the ratio of the width to the length of the channel region of the second switching transistor is greater than or equal to 0.8 and less than or equal to 1.

5. The display device according to claim 1, wherein Each of the plurality of gate circuits further includes: A pseudo transistor is electrically connected between the Q1 node and the Q node.

6. The display device according to claim 5, wherein, The pseudo-transistor is controlled by a second gate drive voltage.

7. The display device according to claim 1, wherein, Each of the plurality of gate circuits further includes: A second capacitor is electrically connected between the Q node and the output terminal of the scan signal.

8. The display device according to claim 7, wherein, The capacitance of the first capacitor is equal to the capacitance of the second capacitor.

9. The display device according to claim 7, wherein, The capacitance of the first capacitor is different from that of the second capacitor.

10. The display device according to claim 1, wherein, Each of the plurality of gate circuits further includes: A third capacitor is electrically connected between the QB node and the input terminal of the first gate drive voltage.

11. The display device according to claim 1, wherein, The phase of the first gate clock signal is different from the phase of the second gate clock signal.

12. A display device, comprising: The display panel has multiple gate lines, multiple data lines, and multiple sub-pixels. as well as Multiple gate circuits that drive the multiple gate lines Each of the plurality of gate circuits includes: A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal; A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage; The first switching transistor is controlled by a Q1 node electrically connected to the Q node and electrically connected between the input terminal of the second gate clock signal and the QB node. A first capacitor, electrically connected between the Q1 node and the input terminal of the first gate clock signal; and A second capacitor is electrically connected between the Q node and the output terminal of the scan signal.

13. The display device according to claim 12, wherein, Each of the plurality of gate circuits further includes: The second switching transistor is controlled by the second gate clock signal and is electrically connected between the input terminal of the gate start signal and the Q1 node.

14. A gate circuit, comprising: A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal; A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage; A switching transistor, which is controlled by a Q1 node electrically connected to the Q node and electrically connected between the input terminal of the second gate clock signal and the QB node; as well as A first capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal. The switching transistor includes two or more transistors.

15. The gate circuit according to claim 14, wherein, During the first time period, the switching transistor is turned on, the Q node is at a level that turns on the pull-up transistor, and the QB node is at a level that turns on the pull-down transistor. During the second period following the first period, the switching transistor remains on, the Q node remains at the level that turns on the pull-up transistor, and the QB node is at the level that turns off the pull-down transistor.

16. The gate circuit according to claim 15, wherein, The voltage level of the Q1 node and the voltage level of the Q node are different from each other during the second time period.

17. The gate circuit according to claim 16, wherein, During the second time period, the voltage level of the Q1 node changes or remains constant according to the voltage level of the first gate clock signal, and the voltage level of the Q node changes according to the voltage level of the output terminal of the scan signal.

18. A gate circuit, comprising: A pull-up transistor, which is controlled by a Q node and electrically connected between the input terminal of the first gate clock signal and the output terminal of the scan signal; A pull-down transistor, which is controlled by a QB node and electrically connected between the output terminal of the scan signal and the input terminal of the first gate drive voltage; A pseudo transistor, which is electrically connected between the Q node and the Q1 node; A first capacitor is electrically connected between the Q1 node and the input terminal of the first gate clock signal; as well as The first switching transistor is controlled by the Q1 node and electrically connected between the input terminal of the second gate clock signal and the QB node.

19. The gate circuit according to claim 18, wherein, The dummy transistor remains in the on state during the period when at least one of the pull-up transistor and the pull-down transistor is in the on state.

20. A display device comprising the gate circuit according to claim 18 or 19, in, The display device further includes a display panel, on which multiple gate lines, multiple data lines and multiple sub-pixels are disposed; Wherein, the plurality of gate lines are driven by a plurality of the gate circuits; and The first switching transistor includes two or more transistors.

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