Method, apparatus, storage medium and device for delay compensation of synchronous serial communication

Abstract

The present application relates to the field of communication technology, especially a method for compensating delay of synchronous serial communication, a compensated clock is generated in a host, the compensated clock is clk_compensation, the starting time of the compensated clock clk_compensation is the same as the edge time of the starting bit of received data, so the data sent by a slave is received by using the compensated clock clk_compensation, without calculating the specific time of line delay, the data sent by the slave can be accurately received; and since the communication is compensated in real time each time, even if the same host product uses different baud rates at different time, the data can be correctly read.The present application is applicable to different products of synchronous serial communication, has strong compatibility, and can greatly improve the speed of synchronous serial communication and the physical line length.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method for compensating for delays in synchronous serial communication. Background Technology

[0002] Synchronous serial communication is widely used because of its simple wiring (one clock line and one data line) and the fact that each bit of data is transmitted strictly according to the clock frequency during communication, making it less prone to errors. For example, encoders with communication protocols such as SSI and BISS-C are developed based on synchronous serial communication.

[0003] With the rapid development of technology, the amount of data being communicated is increasing, the communication speed is getting higher, and the physical communication lines are getting longer. Since both the master and slave devices in synchronous serial communication strictly follow the clock signal sent by the master to receive and send data, the longer the physical line, the greater the line delay. When the line delay exceeds the transmission time of one bit, the master will receive incorrect communication data. This phenomenon becomes increasingly pronounced as communication speeds increase (the transmission time per bit becomes shorter). Summary of the Invention

[0004] This invention addresses the problems of existing technologies by providing a method for compensating for delay in synchronous serial communication. It can generate a line delay compensation clock in real time based on the received data, and sample the received data using the compensation clock. This method is unaffected by line delay and can ensure the accuracy of the received data.

[0005] To address the aforementioned technical problems, the first aspect of this invention discloses the following technical solution: a method for synchronous serial communication delay compensation, comprising the following methods:

[0006] The master sends a communication request to the slave, and the communication transmission clock is CLK1. The slave sends data according to the received master communication request, which is set as data DATA1. The clock used by the slave to receive the master communication request is CLK2. The period of clock CLK1 and clock CLK2 is t.

[0007] The master receives data sent from the slave. The received data is designated as data DATA2, where the start bit of data DATA2 has an edge time of T0. Data DATA2 includes a start bit, data bits, and a stop bit.

[0008] The host generates a compensation clock clk_compensation for line delay, where the clock period of the compensation clock clk_compensation is t and the start edge time is T0;

[0009] After the master receives the start bit of data DATA2, it continues to send communication requests to the slave according to the transmission clock CLK1 for the slave to send data, and at the same time receives the sampled data DATA2 according to the generated compensation clock clk_compensation;

[0010] Upon receiving the stop bit of data DATA2, the master stops sending communication requests to the slave.

[0011] Preferably, the generation of the compensation clock clk_compensation is stopped after the host receives the stop bit of data DATA2.

[0012] Preferably, data DATA1 includes a 1-bit start bit, N-bit data bits, and a 1-bit stop bit, and data DATA2 includes a 1-bit start bit, N-bit data bits, and a 1-bit stop bit, wherein the edge time of the start bit of data DATA1 is t1, and the edge time of the start bit of data DATA2 is t2.

[0013] Preferably, the number of line delay compensation clocks clk_compensation generated by the host is (1+N+1) bits.

[0014] Preferably, the starting edge time of the transmission clock CLK1 is t0, then T0 = t0 + t1 + t2.

[0015] A second aspect of the present invention discloses a communication device, including a host and a slave device signal-connected to the host;

[0016] The host is used to send a communication request clock to the slave. After the slave receives the communication request clock and sends data to the host, the host receives the data from the slave and generates a compensation clock based on the start time of the received data. The host then uses the compensation clock to sample the received data.

[0017] A third aspect of the present invention discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for synchronous serial communication delay compensation.

[0018] A fourth aspect of the present invention discloses an electronic device, wherein the electronic device comprises:

[0019] Processor; and,

[0020] A memory is configured to store computer-executable instructions, which, when executed, cause the processor to perform the synchronous serial communication delay compensation method described above. The beneficial effects of this invention are:

[0021] This invention provides a method for delay compensation in synchronous serial communication. A compensation clock, clk_compensation, is generated internally by the host machine after line delay compensation. The start time of clk_compensation coincides with the edge time of the start bit of the received data. Therefore, by using the compensated clk_compensation to receive data sent by the slave machine, it is possible to accurately receive the data without calculating the specific line delay. Furthermore, since compensation is performed in real-time for each communication, data can be correctly read even if the same host product uses different baud rates at different times. This invention is applicable to various synchronous serial communication products, exhibiting strong compatibility and significantly improving the speed and physical line length of synchronous serial communication. Attached Figure Description

[0022] Figure 1 This is a flowchart of the method of the present invention;

[0023] Figure 2 A schematic diagram of synchronous serial communication when line delay is ignored;

[0024] Figure 3 This is a schematic diagram of synchronous serial communication with line delay.

[0025] Figure 4 This is a schematic diagram of synchronous serial communication after line delay compensation according to the present invention. Detailed Implementation

[0026] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention. The present invention will be described in detail below with reference to the accompanying drawings.

[0027] Example 1:

[0028] This embodiment provides a method for compensating for delays in synchronous serial communication, such as... Figure 1 and Figure 4 It includes the following methods and steps:

[0029] S1. The master sends a communication request to the slave, with the transmission clock being CLK1. The slave then sends data, denoted as DATA1, based on the received master communication request. The slave uses CLK2 to receive the master's communication request, and the period of both CLK1 and CLK2 is t. DATA1 includes a 1-bit start bit, N bits of data, and a 1-bit stop bit. Since the master's transmission of clock CLK1 to the slave takes time, a first line delay occurs during this process. Therefore, the actual signal received by the slave at clock CLK2 is delayed by a factor of the master's transmission clock CLK1. Figure 4 As shown.

[0030] S2. The master receives data transmitted from the slave device. The received data is designated as data DATA2, where the start bit of data DATA2 has an edge time of T0. Data DATA2 includes a start bit, data bits, and a stop bit. Since data DATA2 is transmitted from the slave device, it is identical to data DATA1, i.e., data DATA2 includes a 1-bit start bit, N-bit data bits, and a 1-bit stop bit. However, a second line delay occurs during the process of the slave device transmitting data DATA1 to the master device receiving it. Therefore, data DATA2 is delayed compared to data DATA1. Thus, in this embodiment, data DATA1 and data DATA2 are used to represent the two data. Figure 4 As shown.

[0031] S3. The host generates a compensation clock clk_compensation for line delay, where the clock period of the compensation clock clk_compensation is t, and the start edge time is T0. The compensation clock clk_compensation is generated in real time when the host receives data; it is a virtual clock. Simultaneously with the host receiving data DATA2 (although there is a delay, the host has not yet sampled the data), a compensation clock clk_compensation with the same edge time as the start bit of data DATA2 is generated. Data reception sampling of data DATA2 is performed using this compensation clock clk_compensation, for example, sampling data on the rising edge of the compensation clock clk_compensation. Figure 4 As shown, since the compensation clock generates a clock signal after compensating for the first and second line delays, it can maintain consistency with the data DATA2. Therefore, by reading data based on the compensation clock clk_compensation, the line delay time can be ignored, and the data can be read accurately without being affected by the line delay.

[0032] S4. After the master receives the start bit of data DATA2, it continues to send a communication request to the slave according to the transmission clock CLK1 for the slave to send data, and at the same time receives the sampled data DATA2 according to the generated compensation clock clk_compensation.

[0033] S5. When the stop bit of data DATA2 is received, the host stops sending communication requests to the slave and also stops generating the compensation clock clk_compensation to avoid wasting the host's resources. In this embodiment, as long as the start bit and stop bit of data DATA2 are read, the compensation clock clk_compensation can be continuously generated. That is, the number of compensation clocks is consistent with the number of bits of data DATA2. For example, in this embodiment, the number of compensation clocks clk_compensation is (1+N+1) bits.

[0034] Optionally, all method steps in this embodiment are implemented in an FPGA.

[0035] Specifically, in this embodiment, a compensation clock clk_compensation with line delay compensation is generated internally by the host. The start time of the compensation clock clk_compensation is the same as the edge time of the start bit of the received data. Therefore, by using the compensation clock clk_compensation to receive data sent by the slave device, it is not necessary to calculate the specific time of the line delay to accurately receive the data sent by the slave device. For example, if the start edge time of the transmit clock CLK1 is t0, the edge time of the start bit of data DATA1 is t1, and the edge time of the start bit of data DATA2 is t2, then the start time of the compensation clock clk_compensation is T0 = t0 + t1 + t2. Since this embodiment performs real-time compensation for each communication, even if the same host product uses different baud rates at different times, it can still read data correctly. Moreover, since the theoretical line delay is eliminated, the method of this embodiment allows users to arbitrarily set the communication speed and the physical length of the communication line, provided that the hardware circuit supports it.

[0036] like Figure 2 As shown in the diagram, the synchronous serial communication ignores line delay. Under this condition, the start edge time of the transmit clock CLK1 is t0, the start bit time of data DATA1 is t1, and the start bit time of data DATA2 is t2, which are the same, that is, at the same time.

[0037] Furthermore, a schematic diagram of synchronous serial parallel operation after taking into account actual line delay is shown below. Figure 3 As shown, when the host receives data DATA2, it is delayed by two lines. When this line delay increases, the host's transmit clock CLK1 may sample data DATA2 for more than one bit, which may result in the start bit not being read or the subsequent data bits being read directly.

[0038] Therefore, this embodiment compensates for the line delays generated during the sending and receiving processes, generating a real-time compensation clock clk_compensation, such as... Figure 4 The diagram illustrates the clock and signal configuration for data transmission and reception in this embodiment. The compensation clock clk_compensation is synchronized with the received data DATA2. Therefore, by reading data DATA2 based on the compensation clock clk_compensation, data accuracy is guaranteed, and there is no need to consider whether the delay between the two preceding lines exceeds one bit. Consequently, this embodiment is applicable to various synchronous serial communication products, exhibiting strong compatibility and significantly improving the speed and physical line length of synchronous serial communication.

[0039] Example 2:

[0040] This embodiment provides a synchronous serial communication delay compensation communication device, including a host and a slave device signal-connected to the host; the host is used to send a communication request clock to the slave device. After the slave device receives the communication request clock and sends data to the host, the host receives the data from the slave device and generates a compensation clock according to the start time of the received data. The host then uses the compensation clock to sample the received data.

[0041] Specifically, the host of a product that enables synchronous serial communication has two clock signals: a data request transmission clock CLK1 and a real-time compensation clock clk_compensation generated after receiving data from the slave. The transmission clock CLK1 is used to send a communication request to the slave, and the compensation clock clk_compensation is used to read the data received from the slave. The compensation clock clk_compensation is consistent with the received data, so the host can accurately read the data fed back by the slave without being affected by the delay of the physical line.

[0042] Example 3:

[0043] This embodiment discloses a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform the steps of the synchronous serial communication delay compensation method described in Embodiment 1.

[0044] Example 4:

[0045] This embodiment discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps in the synchronous serial communication delay compensation method described in Embodiment 1.

[0046] Example 5:

[0047] This embodiment discloses an electronic device, wherein the electronic device includes:

[0048] The processor; and a memory arranged to store computer-executable instructions (program code), which may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory has storage space for storing program code for performing any method steps in the embodiments. For example, the storage space for program code may include various program codes for implementing the various steps in the methods described above. This program code can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact discs (CDs), memory cards, or floppy disks. Such computer program products are typically the computer-readable storage medium of Embodiment 4. This computer-readable storage medium may have storage units such as storage segments, storage spaces, etc., arranged similarly to the memory in the electronic device of this embodiment. The program code may be compressed, for example, in a suitable form. Typically, the storage units store program code for performing the method steps according to the invention, i.e., program code that can be read by a processor such as [processor name missing], which, when run by the electronic device, causes the electronic device to perform the various steps in the methods described above.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present invention without departing from the scope of the present invention are within the scope of the present invention.

Claims

1. A method for compensating delay in synchronous serial communication, characterized in that, Including the following methods: The master sends a communication request to the slave, and the communication transmission clock is CLK1. The slave sends data according to the received master communication request, which is denoted as DATA1. The clock used by the slave to receive the master communication request is CLK2. The period of clock CLK1 and clock CLK2 is t. Data DATA1 includes 1 bit start bit, N bits data bits and 1 bit stop bit. The master receives data sent from the slave, and the received data is designated as DATA2. The start bit of DATA2 is edged at time T0. DATA2 includes a start bit, data bits, and a stop bit. DATA2 includes a 1-bit start bit, N-bit data bits, and a 1-bit stop bit. The host generates a compensation clock clk_compensation for line delay, where the clock period of the compensation clock clk_compensation is t and the start edge time is T0; The compensation clock clk_compensation is generated in real time when the host receives data. It is a virtual clock. At the same time that the host receives data DATA2, it generates a compensation clock clk_compensation with the same edge time as the start bit of data DATA2. Data DATA2 is sampled by this compensation clock clk_compensation. Since the compensation clock is a clock signal generated after compensating for the first and second line delays, it is consistent with data DATA2. After the master receives the start bit of data DATA2, it continues to send communication requests to the slave according to the transmission clock CLK1 for the slave to send data, and at the same time receives the sampled data DATA2 according to the generated compensation clock clk_compensation; Upon receiving the stop bit of data DATA2, the master stops sending communication requests to the slave. After the host receives the stop bit of data DATA2, it stops generating the compensation clock clk_compensation. The number of clock clk_compensation values ​​generated by the host for line delay compensation is (1+N+1) bits; The start edge time of data DATA1 is t1, and the start edge time of data DATA2 is t2; the start edge time of the transmission clock CLK1 is t0, then T0 = t0 + t1 + t2.

2. A communication device based on the synchronous serial communication delay compensation method according to claim 1, characterized in that: Includes the main unit and the slave unit connected to the main unit via signals; The host is used to send a communication request clock to the slave. After the slave receives the communication request clock and sends data to the host, the host receives the data from the slave and generates a compensation clock based on the start time of the received data. The host then uses the compensation clock to sample the received data.

3. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program that, when executed by a processor, implements the synchronous serial communication delay compensation method as described in claim 1.

4. An electronic device, wherein, The electronic device includes: Processor; and, A memory configured to store computer-executable instructions, which, when executed, cause the processor to perform the synchronous serial communication delay compensation method as described in claim 1.

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