Packet forwarding table query method and electronic device

Abstract

The application provides a packet forwarding table query method and electronic equipment. An ASIC chip calculates a corresponding hash value for a to-be-forwarded packet, and takes the hash value modulo a storage value of a forwarding table to obtain an index value corresponding to the to-be-forwarded packet. Then, the ASIC chip stores all the to-be-forwarded packets in a packet cache queue in sequence based on the index value size. A CPU determines a corresponding forwarding behavior in the forwarding table according to the index value, and stores a forwarding behavior corresponding to at least one index value after the index value in a cache. Since the data read next time is likely to be data connected with the forwarding behavior this time, the probability of hitting the cache when reading data next time is greatly improved, and the situation that the CPU repeatedly reads the memory forwarding table due to the random arrangement of data in the packet cache queue is avoided, and the forwarding efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a message forwarding table query method and electronic device. Background Technology

[0002] In existing technologies, to perform packet forwarding, the CPU needs to maintain a software forwarding table, which is stored in memory. Each time the CPU accesses the forwarding table index, it is actually a process of the CPU reading from memory. However, memory access efficiency is often low. To solve this problem, a cache is usually used to cache frequently used data to improve read and write performance.

[0003] However, in message forwarding scenarios, due to the randomness of the data in the cache, the CPU often needs to query the forwarding table in memory to send the message if the data in the cache is not hit, thus reducing the overall efficiency of message sending. Summary of the Invention

[0004] The purpose of this application is to provide a message forwarding table query method and electronic device to improve the efficiency of forwarding table query, thereby improving the efficiency of message forwarding.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a message forwarding table query method, the method being applied to an electronic device, the electronic device including a CPU and an ASIC chip, the method comprising:

[0007] The ASIC chip receives the message to be forwarded.

[0008] The ASIC chip calculates the corresponding hash value for the packet to be forwarded, and takes the hash value modulo the stored value in the forwarding table to obtain the index value corresponding to the packet to be forwarded; the forwarding table is stored in the memory of the CPU, and the index value corresponds to the forwarding table;

[0009] The ASIC chip stores all the packets to be forwarded in the packet buffer queue in sequence according to the index value corresponding to each packet to be forwarded;

[0010] The CPU reads the packet to be forwarded and the index value from the packet buffer queue;

[0011] The CPU determines the corresponding forwarding behavior in the forwarding table based on the index value, and stores the forwarding behavior corresponding to at least one index value after the index value into the cache.

[0012] In conjunction with the first aspect, in a first possible implementation, after the step of the CPU reading the packet to be forwarded and the index value from the packet buffer queue, the method further includes:

[0013] The CPU determines whether the cache caches the forwarding behavior corresponding to the index value based on the index value;

[0014] If so, the CPU reads the forwarding behavior and stores the forwarding behavior corresponding to at least one index value after the index value into the cache;

[0015] If not, then the CPU performs the step of determining the corresponding forwarding behavior in the forwarding table based on the index value.

[0016] In conjunction with the first aspect, in the second possible implementation, the step of the ASIC chip storing all the packets to be forwarded in sequence in the packet buffer queue according to the index value corresponding to each packet to be forwarded includes:

[0017] The ASIC chip stores each packet to be forwarded and its corresponding index value to the storage location corresponding to the write index, according to the index value of each packet to be forwarded. The write index points to an empty storage location in the packet buffer queue. After each write operation is completed, the write index is configured to point to the next empty storage location.

[0018] In conjunction with the first aspect, in a third possible implementation, the step of the CPU reading the packet to be forwarded and the index value from the packet buffer queue includes:

[0019] The CPU reads the packet to be forwarded and the index value at the storage location pointed to by the read index; the read index points to the storage location of the content already stored in the packet buffer queue, and each time a read is completed, the write index is configured to point to the storage location of the next stored content;

[0020] Once the CPU has finished reading, the ASIC chip clears the data in the corresponding storage location.

[0021] In combination with the first aspect or any of the possible implementations of the first aspect described above, the fourth possible implementation further includes:

[0022] The CPU edits the corresponding message to be forwarded according to the forwarding behavior;

[0023] The CPU sends the edited message to be forwarded and the target physical port to the ASIC chip;

[0024] The ASIC chip sends the edited message to be forwarded to the target physical port.

[0025] Secondly, embodiments of this application provide an electronic device, which includes a CPU and an ASIC chip;

[0026] The ASIC chip is used to receive packets to be forwarded; calculate the corresponding hash value for the packet to be forwarded, and take the hash value modulo the stored value of the forwarding table to obtain the index value corresponding to the packet to be forwarded; the forwarding table is stored in the memory of the CPU, and the index value corresponds to the forwarding table; according to the index value corresponding to each packet to be forwarded, all the packets to be forwarded are stored in the packet buffer queue in order.

[0027] The CPU is configured to read the packet to be forwarded and the index value from the packet buffer queue; determine the corresponding forwarding behavior in the forwarding table based on the index value; and store the forwarding behavior corresponding to at least one index value after the index value into the cache.

[0028] In conjunction with the second aspect, in the first possible implementation, the CPU is specifically configured to determine whether the cache caches the forwarding behavior corresponding to the index value based on the index value; if yes, it reads the forwarding behavior and stores the forwarding behavior corresponding to at least one index value after the index value into the cache; if no, it determines the corresponding forwarding behavior in the forwarding table based on the index value.

[0029] In conjunction with the second aspect, in the second possible implementation, the ASIC chip is specifically used to store each packet to be forwarded and its corresponding index value to the storage location corresponding to the write index, according to the index value size of each packet to be forwarded; the write index points to an empty storage location in the packet buffer queue, and each time a write is completed, the write index is configured to point to the next empty storage location.

[0030] In conjunction with the second aspect, in the third possible implementation, the CPU is specifically used to read the packet to be forwarded and the index value at the storage location pointed to by the read index; the read index points to the storage location of the content already stored in the packet buffer queue, and each time a read is completed, the write index is configured to point to the storage location of the next stored content;

[0031] The ASIC chip is also used to clear the data in the corresponding storage location when the CPU finishes reading.

[0032] In a fourth possible implementation, in conjunction with the second aspect or any of the above-mentioned possible implementations of the second aspect, the CPU is further configured to edit the corresponding message to be forwarded according to the forwarding behavior; and send the edited message to be forwarded and the target physical port to the ASIC chip;

[0033] The ASIC chip is also used to send the edited message to be forwarded to the target physical port.

[0034] Compared to existing technologies, the message forwarding table query method and electronic device provided in this application involves an ASIC chip calculating a hash value for the message to be forwarded, and then taking the hash value modulo the stored value in the forwarding table to obtain an index value corresponding to the message to be forwarded. The ASIC chip then stores all messages to be forwarded sequentially in a message cache queue based on the index value. The CPU then reads the message to be forwarded and the index value from the message cache queue. Since the CPU determines the corresponding forwarding behavior in the forwarding table based on the index value and stores at least one forwarding behavior corresponding to the index value after the current index value in the cache, the probability of the next data read hitting the cache is greatly increased. This avoids the situation where the CPU repeatedly reads the memory forwarding table due to random data arrangement in the message cache queue, thus improving forwarding efficiency.

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart illustrating a message forwarding table query method provided in an embodiment of the present invention;

[0038] Figure 2 A flowchart illustrating another message forwarding table query method provided in an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a message buffer queue provided in an embodiment of the present invention.

[0040] Figure 4 A schematic diagram of another message buffer queue provided in an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of a message forwarding process provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0044] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0045] In existing technologies, certain types of switches require CPU-based message forwarding decisions. These devices consist of an ASIC chip hardware system and a CPU software system. The ASIC chip is primarily responsible for receiving messages and buffering them, waiting for the CPU to read them. The CPU is primarily responsible for reading messages from the buffer queue, deciding on message forwarding behavior, and processing messages based on the forwarding behavior.

[0046] The CPU determines forwarding behavior through a forwarding table, which can be a Layer 2 forwarding table, a Layer 3 forwarding table, an OpenFlow flow table, etc. The forwarding table is typically implemented as a linear array in a contiguous block of memory. The array index is the hash value calculated based on the packet header, modulo the array size, and the array members represent the packet forwarding behavior. Therefore, the CPU's packet forwarding decision process is as follows: calculate the hash value based on the packet header fields, take the hash value modulo the forwarding table size, and use the modulo result as the array index to read the forwarding behavior. For ease of description, this process is generally referred to as looking up the forwarding table based on the hash value to obtain the forwarding behavior.

[0047] The message processing flow is as follows:

[0048] 1. The ASIC chip receives packets from the physical port of the switch, buffers them in a queue, and waits for the CPU to read them;

[0049] 2. The CPU reads the message from the queue, calculates the hash value based on the fields in the message header, and uses the hash value to look up the software forwarding table to obtain the forwarding behavior;

[0050] Third, the CPU edits the packet based on the received forwarding behavior and sends the edited packet to the ASIC chip, while specifying the output port;

[0051] IV. The ASIC chip sends the message to the designated physical output;

[0052] Because CPU hash calculation is relatively inefficient and consumes significant CPU resources, it leads to poor packet forwarding performance. ASIC chips, being part of the hardware, are highly efficient at hash calculation. Therefore, to improve CPU packet processing performance, the hash calculation logic is typically moved to the ASIC chip. The packet processing flow changes as follows:

[0053] 1. The ASIC chip receives packets from the physical port of the switch, calculates the hash value, and caches the packet and its hash value together in a queue, waiting for the CPU to read them;

[0054] 2. The CPU reads packets from the queue and simultaneously reads the hash value. Based on this hash value, it looks up the software forwarding table to obtain the forwarding behavior.

[0055] Third, the CPU edits the packet based on the received forwarding behavior and sends the edited packet to the ASIC chip, while specifying the output port.

[0056] IV. The ASIC chip sends the message to the designated physical exit.

[0057] However, since the software forwarding table is stored in memory, the process of the CPU indexing the forwarding table is essentially a CPU reading from memory. Memory access efficiency is relatively low, so most CPUs implement a cache between the CPU and main memory to improve memory access efficiency. Cache read / write performance is very high, typically tens of times faster than main memory. However, cache is expensive, so its storage space is relatively small, usually used to cache frequently accessed memory content. When the CPU needs to read a block of memory, it will first try to read it from the cache; only if the memory is not in the cache (called a cache miss) will it read it from main memory. After reading from main memory, the CPU will also cache a copy in the cache, because the memory that was just accessed is likely to be accessed again.

[0058] The CPU also predicts the next memory access it might make and prefetches it into the cache to improve the cache hit probability. That is, it caches a small portion of memory following the currently accessed memory location, because after accessing one block of memory, it's very likely that subsequent blocks of memory will be accessed again. This way, the next time the CPU accesses memory, it may be able to read it directly from the cache, without having to access the main memory again.

[0059] However, in existing technologies, CPU access to memory is very inefficient. In order to ensure the forwarding bandwidth of the switch, it is necessary to ensure that as many forwarding table accesses as possible can be read directly from the cache, and to avoid direct access to memory as much as possible.

[0060] To address the aforementioned issues, this embodiment of the invention sorts the cached packet queue according to the hash value modulo the forwarding table size when the ASIC chip caches packets. This ensures that the forwarding tables corresponding to adjacent packets in the queue are as close as possible in memory, reducing the probability of cache misses and improving forwarding performance.

[0061] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0062] Figure 1 This is a flowchart illustrating a message forwarding table query method provided in an embodiment of the present invention. The method is applied to an electronic device, which includes a CPU and an ASIC chip; see also... Figure 1 The method includes:

[0063] Step 100: The ASIC chip receives the message to be forwarded;

[0064] Step 102: The ASIC chip calculates the corresponding hash value for the packet to be forwarded, and takes the modulo of the hash value with the stored value in the forwarding table to obtain the index value corresponding to the packet to be forwarded;

[0065] The size of the forwarding table is fixed during system initialization and can be denoted as "FwdTblSize". This "FwdTblSize" can be recorded in the ASIC chip, and the forwarding table is stored in the CPU's memory. The index value corresponds to the forwarding table.

[0066] Step 104: The ASIC chip stores all packets to be forwarded in the packet buffer queue in order according to the index value corresponding to each packet to be forwarded;

[0067] Optionally, the message buffer queue can be a contiguous storage space, which can be an array consisting of messages and hash values. The ASIC chip stores the data to be buffered into the message buffer queue, and the CPU reads the data from the message buffer queue. In one possible implementation, the read and write operations of the message buffer queue are mutually exclusive, and simultaneous operations will not cause conflicts.

[0068] Step 106: The CPU reads the packet to be forwarded and its index value from the packet buffer queue;

[0069] Step 109: The CPU determines the corresponding forwarding behavior in the forwarding table based on the index value, and stores the forwarding behavior corresponding to at least one index value after the index value into the cache.

[0070] The message forwarding table query method provided in this embodiment of the invention involves an ASIC chip calculating a hash value for the message to be forwarded, and then taking the modulo of the hash value with the stored value in the forwarding table to obtain the index value corresponding to the message to be forwarded. The ASIC chip then stores all messages to be forwarded in a message cache queue in sequence based on the index value. The CPU then reads the message to be forwarded and the index value from the message cache queue. Since the CPU determines the corresponding forwarding behavior in the forwarding table based on the index value and stores at least one forwarding behavior corresponding to the index value after the current index value in the cache, the probability of the next data read hitting the cache is greatly increased. This avoids the situation where the CPU repeatedly reads the memory forwarding table due to the random arrangement of data in the message cache queue, thus improving forwarding efficiency.

[0071] In one possible implementation, when the CPU performs packet forwarding, it first checks if the corresponding entry for the forwarded packet is cached in the cache. If so, it reads it directly from the cache, thereby improving read efficiency. Figure 1 On this basis, Figure 2 A flowchart illustrating another message forwarding table query method provided in this embodiment of the invention is shown below. Figure 2 Following step 106, the following is also included:

[0072] Step 107: The CPU checks whether the cache caches the forwarding behavior corresponding to the index value; if yes, proceed to step 108; otherwise, proceed to step 109.

[0073] Step 108: The CPU reads the forwarding behavior and stores the forwarding behavior corresponding to at least one index value after the index value into the cache.

[0074] Optionally, Figure 3 This is a schematic diagram of a message buffer queue provided in an embodiment of the present invention. See also... Figure 3 To enable read and write operations on the message buffer, two index values ​​are introduced: the write index (hwIndex) and the read index (swIndex). These are explained below with examples. See also... Figure 2 Step 104 includes:

[0075] Step 104-1: The ASIC chip stores each packet to be forwarded and its corresponding index value into the storage location corresponding to the write index, according to the index value of each packet to be forwarded.

[0076] The write index (hwIndex) points to an empty storage location in the message buffer queue. After each write operation is completed, the write index is configured to point to the next empty storage location.

[0077] The hwIndex has the following special cases:

[0078] 1) If hwIndex is already the last storage unit in the message buffer queue, hwIndex will be moved to the first position in the message buffer queue.

[0079] 2) If hwIndex and swIndex are equal and the current storage space they point to is not empty, it means that the message buffer queue is full and no more data will be stored in the message buffer queue.

[0080] 3) Initially, the message buffer queue is empty, and hwIndex points to storage unit 0.

[0081] See also Figure 2 Step 106 includes:

[0082] Step 106-1: The CPU reads the packet to be forwarded and the index value at the storage location pointed to by the index;

[0083] The read index (swIndex) points to the storage location of the content already stored in the message buffer queue. After each read is completed, the write index is configured to point to the storage location of the next stored content.

[0084] The swIndex has the following special cases:

[0085] 1) If swIndex is already the last storage unit in the message buffer queue, swIndex will be moved to the first position in the message buffer queue.

[0086] 2) If swIndex and hwIndex point to the same memory unit and the memory space they are pointing to is empty, it means that the message buffer queue is empty and the CPU will not read data from the message buffer queue.

[0087] 3) Initially, the message buffer queue is empty, and swIndex points to storage unit 0.

[0088] Step 106-2: When the CPU finishes reading, the ASIC chip clears the data in the corresponding storage location.

[0089] As shown in the example above, if swIndex is smaller than hwIndex, the packets between swIndex and hwIndex are currently being buffered. If swIndex is larger than hwIndex, then the packets between swIndex and the end of the queue, and between the head of the queue and hwIndex, are currently being buffered.

[0090] This is a general implementation of the message buffer queue. Since this invention adds a sorting function to the message buffer queue, there will be some special cases to handle. Figure 4 This is a schematic diagram of another message buffer queue provided in an embodiment of the present invention, which is described below in conjunction with... Figure 4 The following explanations will be provided for each situation:

[0091] 1) If the message buffer queue is empty, place it at the first position in the message buffer queue, and move hwIndex to the next adjacent storage space.

[0092] 2) If a packet with the same HashIndex exists in the packet buffer queue, insert it after the current packet. Then, shift all packets originally following the current packet one position to the right, and move their HashIndex accordingly.

[0093] 3) If there are two adjacent packets in the packet buffer queue such that the hash index of the preceding packet is smaller than that of the current packet, and the hash index of the following packet is larger than that of the current packet, insert the packet between these two packets, and shift the following packet and all subsequent packets one position to the right, with the hash index shifted accordingly.

[0094] 4) If the hash index of all packets in the packet buffer queue is smaller than the hash index of the current packet, place it in the position after the last buffered packet in the queue, and move its hash index accordingly.

[0095] 5) If the hash index of all packets in the packet buffer queue is greater than the hash index of the current packet, insert it before the first buffered packet in the packet buffer queue. All existing packets in the queue are shifted one position to the right, and their hash indexes are shifted accordingly.

[0096] 6) If the message buffer queue is full, this message will not be put into the buffer queue.

[0097] See Figure 4 In one example, the message to be cached is message i, and the hash value is hash value i. Figure 2 This refers to the situation where the ASIC chip inserts a message into the message buffer queue when index i equals index i, or when index i is less than HashIndex3 and index i is greater than index i. The data for messages 3 and 4 are shifted backward to free up storage unit 4 to store the data for message i. HwIndex is then shifted to storage unit 7.

[0098] Furthermore, Figure 5 This is a schematic diagram of a message forwarding process provided in an embodiment of the present invention. See also: Figure 5 As in the example above, after receiving message i, ASIC chip 20 calculates a hash value i for message i, then takes the modulo of the hash value i with the stored value M in the forwarding table to obtain an index value i. Based on the size of the index value i, message i and hash value i are then stored in the message buffer queue.

[0099] Then, CPU 10 reads the message i and hash value i to determine the index value i. Based on this index value i, it reads the forwarding table. Referring to steps 107 and 108 in the previous example, CPU 10 first checks the cache 11. If a cache hit occurs, the corresponding forwarding action in the forwarding table is directly determined from the cache 11. If a cache miss occurs, CPU 10 checks memory 12 to determine the corresponding forwarding action in the forwarding table and stores the forwarding action corresponding to at least one index value after the current index value in the cache 11. For example, the forwarding actions corresponding to index values ​​i+1 and i+2 are stored in the cache 11 so that they can be read directly from the cache 11 next time, improving read efficiency.

[0100] Then, CPU 10 edits the corresponding message to be forwarded according to the forwarding behavior; CPU 10 sends the edited message to be forwarded (message i) and the target physical port to ASIC chip 20; ASIC chip 20 sends the edited message to be forwarded (message i) to the target physical port.

[0101] The technical effects of the embodiments of the present invention will be explained below with reference to specific examples.

[0102] Specifically, the conditions for this example are as follows:

[0103] 1) Assume that the CPU cache can cache 4 forwarding tables. When there are not enough entries, the old entries are overwritten in a loop.

[0104] 2) Assume that when the CPU reads the forwarding table from memory or cache, it will prefetch the next adjacent forwarding table entry into the cache. For example, after the CPU reads the 100th entry of the forwarding table from the cache or memory, it will prefetch the 101st entry of the forwarding table into the cache.

[0105] Here is an example of the scenario: The device receives 7 messages, and the message indexes (HashIndex) are 5, 50, 53, 6, 51, 52, and 7 in sequence.

[0106] I. For existing technologies, the following scenarios do not involve message sorting:

[0107] In the buffer queue, the packet index values ​​are in the following order: 5, 50, 53, 6, 51, 52, 7; the CPU will read and process these packets in sequence, and the reading of the forwarding table will be as follows:

[0108] The cache is empty before a message is received;

[0109] ● The index value 5 of the first message: cache miss. Directly read from memory and cache forwarding table 5 and 6 in the cache. The cache content is 5,6,0,0;

[0110] ● The index value 50 of the second message: cache miss. Directly read from memory and cache forwarding table 50 and 51 in the cache. The cache content is 5, 6, 50, 51.

[0111] ● The index value 53 of the third message: cache miss. Directly read from memory and cache forwarding table 53 and 54 in the cache. The cache content is 53, 54, 50, 51;

[0112] ● The index value 6 of the 4th message: cache miss. Directly read from memory and cache forwarding table 6 and 7 in the cache. The cache content is 53, 54, 6, 7.

[0113] ● The index value 51 of the 5th message: cache miss. Directly read from memory and cache forwarding table 51 and 52 in the cache. The cache content is 51, 52, 6, 7.

[0114] ● The index value 52 of the 6th message: cache hit, and the forwarding table 53 is cached in the cache, with the cache contents being 51, 52, 53, 7;

[0115] ● The index value 7 of the 7th message: cache hit, and forwarding table 8 is cached in the cache, the cache content is 8,52,53,7;

[0116] As can be seen, the above technical solutions were missed 5 times and hit 2 times.

[0117] II. Sorting messages using the technical solution provided in the embodiments of the present invention:

[0118] In the message buffer queue, the messages are ordered based on their index values ​​as follows: 5, 6, 7, 50, 51, 52, 53; the CPU will read and process these messages sequentially, and the reading of the forwarding table will be as follows:

[0119] The cache is empty before a message is received;

[0120] ● The index value 5 of the first message indicates a cache miss. The message is read directly from memory, and forwarding table 5 and 6 are cached in the cache. The cache content is 5,6,0,0.

[0121] ● The second message index 6: cache hit, and forwarding table 7 is cached in the cache, the cache content is 5,6,7,0

[0122] ● The index value 7 of the third message: cache hit, and forwarding table 8 is cached in the cache, with cache contents of 5, 6, 7, and 8.

[0123] ● The index value 50 of the 4th message indicates a cache miss. The message is read directly from memory, and forwarding table 50 and 51 are cached in the cache. The cached content is 50, 51, 7, and 8.

[0124] ● The index value 51 of the 5th message: cache hit, and forwarding table 52 is cached in the cache. The cache content is 50, 51, 52, 8.

[0125] ● Index value 52 of the 6th message: cache hit, and forwarding table 53 is cached in the cache, with cache contents being 50, 51, 52, 53.

[0126] ● The index value 53 of the 7th message: cache hit, and forwarding table 54 is cached in the cache. The cache content is 54, 51, 52, 53.

[0127] As can be seen, for the technical solution provided in the embodiments of the present invention, there are a total of 2 misses and 5 hits; obviously, the probability of consecutive index values ​​of packets in the sorted cache queue is higher, and the CPU has a higher probability of prefetching the memory that will be used later into the cache, avoiding direct access to memory when the cache misses.

[0128] Further, see Figure 5The present invention also provides an electronic device, which includes a CPU 10 and an ASIC chip 20;

[0129] ASIC chip 20 is used to receive packets to be forwarded; calculate the corresponding hash value for the packets to be forwarded, and take the modulo of the hash value with the stored value of the forwarding table to obtain the index value corresponding to the packets to be forwarded; the forwarding table is stored in the memory of CPU 10, and the index value corresponds to the forwarding table; according to the index value corresponding to each packet to be forwarded, all packets to be forwarded are stored in the packet buffer queue in order.

[0130] CPU 10 is used to read the packets to be forwarded and their index values ​​from the packet buffer queue; determine the corresponding forwarding behavior in the forwarding table based on the index value; and store the forwarding behavior corresponding to at least one index value after the index value into the cache.

[0131] The electronic device provided in this embodiment of the invention uses an ASIC chip to calculate the corresponding hash value for the packet to be forwarded, and then modulo the hash value with the stored value in the forwarding table to obtain the index value corresponding to the packet to be forwarded. The ASIC chip then stores all packets to be forwarded in sequence in a packet cache queue based on the index value. The CPU then reads the packet to be forwarded and the index value from the packet cache queue. Since the CPU determines the corresponding forwarding behavior in the forwarding table based on the index value, and stores at least one forwarding behavior corresponding to an index value after the current index value in the cache, the probability of the next data read hitting the cache is greatly increased. This avoids the situation where the CPU repeatedly reads the memory forwarding table due to the random arrangement of data in the packet cache queue, thus improving forwarding efficiency.

[0132] Optionally, CPU 10 is specifically used to determine whether the cache caches the forwarding behavior corresponding to the index value based on the index value; if yes, it reads the forwarding behavior and stores the forwarding behavior corresponding to at least one index value after the index value into the cache; if no, it determines the corresponding forwarding behavior in the forwarding table based on the index value.

[0133] Optionally, the ASIC chip 20 is specifically used to store each packet to be forwarded and its corresponding index value to the storage location corresponding to the write index, according to the index value size of each packet to be forwarded; the write index points to an empty storage location in the packet buffer queue, and each time a write is completed, the write index is configured to point to the next empty storage location.

[0134] Optionally, CPU 10 is specifically used to read the packet to be forwarded and the index value at the storage location pointed to by the read index; the read index points to the storage location of the content already stored in the packet buffer queue, and after each read is completed, the write index is configured to point to the storage location of the next stored content;

[0135] Optionally, the ASIC chip 20 is also used to clear the data in the corresponding storage location when the CPU 10 finishes reading.

[0136] Optionally, the CPU 10 is also used to edit the corresponding message to be forwarded according to the forwarding behavior; and to send the edited message to be forwarded and the target physical port to the ASIC chip;

[0137] The ASIC20 chip is also used to send edited messages to be forwarded to the target physical port.

[0138] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0139] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0140] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0142] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for querying a message forwarding table, characterized in that, The method is applied to an electronic device, the electronic device including a CPU and an ASIC chip, the method comprising: The ASIC chip receives the message to be forwarded; The ASIC chip calculates the corresponding hash value for the packet to be forwarded, and takes the hash value modulo the stored value in the forwarding table to obtain the index value corresponding to the packet to be forwarded; the forwarding table is stored in the memory of the CPU, and the index value corresponds to the forwarding table; The ASIC chip stores all the packets to be forwarded in the packet buffer queue in sequence according to the index value corresponding to each packet to be forwarded; The CPU reads the packet to be forwarded and the index value from the packet buffer queue; The CPU determines whether the cache should cache the forwarding behavior corresponding to the index value based on the index value. If so, the CPU reads the forwarding behavior and stores the forwarding behavior corresponding to at least one index value after the index value into the cache; If not, the CPU determines the corresponding forwarding behavior in the forwarding table based on the index value, and stores the forwarding behavior corresponding to at least one index value after the index value into the cache.

2. The method as described in claim 1, characterized in that, The step of the ASIC chip storing all the packets to be forwarded in order in the packet buffer queue according to the index value corresponding to each packet to be forwarded includes: The ASIC chip stores each packet to be forwarded and its corresponding index value to the storage location corresponding to the write index, according to the index value of each packet to be forwarded. The write index points to an empty storage location in the packet buffer queue. After each write operation is completed, the write index is configured to point to the next empty storage location.

3. The method as described in claim 1, characterized in that, The step of the CPU reading the packet to be forwarded and the index value from the packet buffer queue includes: The CPU reads the packet to be forwarded and the index value at the storage location pointed to by the read index; the read index points to the storage location of the content already stored in the packet buffer queue, and each time a read is completed, the write index is configured to point to the storage location of the next stored content; Once the CPU has finished reading, the ASIC chip clears the data in the corresponding storage location.

4. The method according to any one of claims 1 to 3, characterized in that, Also includes: The CPU edits the corresponding message to be forwarded according to the forwarding behavior; The CPU sends the edited message to be forwarded and the target physical port to the ASIC chip; The ASIC chip sends the edited message to be forwarded to the target physical port.

5. An electronic device, characterized in that, Electronic devices include: CPU and ASIC chips; The ASIC chip is used to receive packets to be forwarded; calculate the corresponding hash value for the packet to be forwarded, and take the hash value modulo the stored value of the forwarding table to obtain the index value corresponding to the packet to be forwarded; the forwarding table is stored in the memory of the CPU, and the index value corresponds to the forwarding table; according to the index value corresponding to each packet to be forwarded, all the packets to be forwarded are stored in the packet buffer queue in order. The CPU is configured to read the packet to be forwarded and the index value from the packet cache queue; determine whether the cache caches the forwarding behavior corresponding to the index value based on the index value; if yes, read the forwarding behavior; and store the forwarding behavior corresponding to at least one index value after the index value into the cache; if no, determine the corresponding forwarding behavior in the forwarding table based on the index value, and store the forwarding behavior corresponding to at least one index value after the index value into the cache.

6. The electronic device as claimed in claim 5, characterized in that, The ASIC chip is specifically used to store each packet to be forwarded and its corresponding index value to the storage location corresponding to the write index, according to the index value of each packet to be forwarded. The write index points to an empty storage location in the packet buffer queue. After each write operation is completed, the write index is configured to point to the next empty storage location.

7. The electronic device as claimed in claim 5, characterized in that, The CPU is specifically used to read the packet to be forwarded and the index value at the storage location pointed to by the read index; the read index points to the storage location of the content already stored in the packet buffer queue, and each time a read is completed, the write index is configured to point to the storage location of the next stored content; The ASIC chip is also used to clear the data in the corresponding storage location when the CPU finishes reading.

8. The electronic device according to any one of claims 5 to 7, characterized in that, The CPU is also configured to edit the corresponding message to be forwarded according to the forwarding behavior; and send the edited message to be forwarded and the target physical port to the ASIC chip. The ASIC chip is also used to send the edited message to be forwarded to the target physical port.

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