A method for manufacturing a semiconductor barrier layer and a barrier layer film

Abstract

The application provides a preparation method of a semiconductor barrier layer and a barrier layer film. The preparation method comprises the following steps: in each cycle of preparing the barrier layer by using an atomic layer deposition process, heating a semiconductor substrate, introducing a metal compound gas into the semiconductor substrate in a reaction chamber in a first pulse time, then introducing a carrier gas for purging in a second pulse time, introducing NH3 in a third pulse time, and introducing the carrier gas for purging again in a fourth pulse time, repeating multiple cycles until a preset process requirement is met; after one or more cycles of the reaction, the silicon source gas is introduced simultaneously in the first pulse time; and as the reaction proceeds, the flow ratio of the silicon source gas and the metal compound gas is gradually increased, so that the content of silicon nitride and metal nitride obtained by deposition reaction forms a concentration gradient in the barrier layer along the direction close to the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processes, and more particularly to a method for preparing a semiconductor barrier layer and a barrier layer thin film. Background Technology

[0002] In semiconductor manufacturing processes, semiconductors are typically constructed by stacking multiple layers of materials. Different materials between layers, such as metals and oxygen atoms, can diffuse into each other at the junctions between layers, thereby affecting the functional performance of semiconductor devices.

[0003] To address the issue of interlayer diffusion, additional barrier layers are typically fabricated between the layers to prevent interlayer atomic diffusion. For example, in the TiSiN fabrication process, the diffusion channels between layers are mainly the grain boundaries of the TiN matrix. SiN is usually used as the barrier layer material, as it can reduce diffusion at the grain boundaries.

[0004] In existing technologies, thermal atomic layer deposition (ALD) is commonly used to deposit the barrier layer structure in TiSiN fabrication. However, the periodic deposition process results in a multi-layered structure, where layered SiN is less likely to diffuse to the grain boundaries to form a reinforcing structure, thus limiting its barrier effect. Furthermore, in existing TiSiN fabrication processes using ALD, the ratio of titanium to silicon atoms is adjusted by regulating the cycle time of TiN and SiN. This adjustment range is narrow and cannot adapt to diverse needs to optimize the TiSiN structure, thus hindering the improvement of the barrier layer's barrier performance.

[0005] In order to overcome the above-mentioned defects in the existing technology, there is an urgent need in the field for a method for preparing a semiconductor barrier layer and a barrier layer film, which can be used to block the interlayer diffusion of oxygen, silicon and metal atoms in the upper and lower layers of a semiconductor structure. At the same time, the deposition formula ratio can be adjusted over a wide range to form a concentration gradient of silicides inside the barrier layer, thereby reducing the internal stress of the film and making it easier for silicides to accumulate in the grain boundaries, thereby optimizing the structure of the barrier layer and improving the barrier effect. Summary of the Invention

[0006] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0007] To overcome the aforementioned deficiencies in the prior art, the present invention provides a method for preparing a semiconductor barrier layer. This barrier layer is used to block the interdiffusion of materials between upper and lower semiconductor layers. The preparation method employs an atomic layer deposition (ALD) process, comprising: heating a semiconductor substrate in each cycle of preparing the barrier layer using the ALD process; introducing a metal compound gas into the semiconductor substrate within a reaction chamber for deposition during a first pulse time; then introducing a carrier gas for purging during a second pulse time; introducing NH3 for deposition reaction during a third pulse time; and introducing the carrier gas again for purging during a fourth pulse time, repeating this process multiple times until a preset process requirement is met; after one or more cycles of the initial reaction, simultaneously introducing a silicon source gas and the metal compound gas for deposition during the first pulse time; and gradually increasing the flow rate ratio of the silicon source gas and the metal compound gas as the reaction proceeds, so that a concentration gradient is formed in the silicon nitride content of the metal nitride in the barrier layer along the direction close to the semiconductor substrate.

[0008] In one embodiment, preferably, in the method for preparing the semiconductor barrier layer provided by the present invention, the gradual increase in the flow ratio of the silicon source gas and the metal compound gas includes: as the reaction proceeds, the flow ratio of the metal compound gas and the silicon source gas introduced into the reaction chamber gradually changes from 100:1 to 1:100.

[0009] In one embodiment, preferably, in the method for preparing the semiconductor barrier layer provided by the present invention, the ratio of silicon nitride to metal nitride obtained by the deposition reaction is between 0% and 60%.

[0010] In one embodiment, optionally, in the method for preparing the semiconductor barrier layer provided by the present invention, the metal compound gas includes TiCl4, the silicon source gas includes DCS gas, and the silicon nitride and metal nitride obtained by the deposition reaction include TiN and SiN, respectively.

[0011] In one embodiment, optionally, in the method for preparing the semiconductor barrier layer provided by the present invention, the carrier gas includes Ar or N2, and the flow rate of each gas introduced into the reaction chamber in each cycle ranges from 50 to 10000 sccm.

[0012] In one embodiment, preferably, in the method for preparing the semiconductor barrier layer provided by the present invention, the temperature range of the heated semiconductor substrate is 300 to 700°C.

[0013] In one embodiment, optionally, in the method for preparing the semiconductor barrier layer provided by the present invention, the duration of each cycle ranges from 0.1 to 20 s, and the duration of a single pulse ranges from 0.02 to 10 s.

[0014] In one embodiment, optionally, in the method for preparing the semiconductor barrier layer provided by the present invention, the semiconductor substrate includes a high-k dielectric, silicon and silicides, and elemental metals and alloys.

[0015] In one embodiment, optionally, in the method for preparing the semiconductor barrier layer provided by the present invention, the high-k dielectric includes Al2O3, TiO2, Ta2O3 and HfO2, the silicon and silicides include polycrystalline silicon, SiO2, SiON, SiCO, SiN and SiCON, and the elemental metals and alloys include W, Al, Cu, Co, Ni, Pb, Ti and their alloys.

[0016] In one embodiment, optionally, the method for preparing the semiconductor barrier layer provided by the present invention is carried out using an atomic layer deposition apparatus with a dual-pulse gas intake function or a pre-mixing chamber.

[0017] Another aspect of the present invention provides a barrier layer thin film for a semiconductor, which is prepared on the semiconductor substrate using the preparation method described in any of the above descriptions, wherein the content of silicon nitride obtained by the deposition reaction and the content of metal nitride form a concentration gradient along the direction close to the semiconductor substrate.

[0018] In one embodiment, preferably, in the barrier layer thin film of the semiconductor provided by the present invention, the ratio of silicon nitride to metal nitride obtained by the deposition reaction is between 0% and 60%. Attached Figure Description

[0019] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0020] Figure 1 This is a schematic diagram of time pulses for introducing various gases in one cycle during the process of preparing a barrier layer using atomic layer deposition, according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of a semiconductor barrier layer device structure according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram illustrating the working principle of an atomic layer deposition apparatus with dual-pulse air intake function for preparing a barrier layer according to an embodiment of the present invention; and

[0023] Figures 4A to 4D This is a schematic diagram illustrating the working principle of preparing a barrier layer using an atomic layer deposition apparatus equipped with a pre-mixing chamber, according to an embodiment of the present invention.

[0024] For clarity, a brief explanation of the reference numerals in the accompanying drawings is provided below:

[0025] 200 barrier layers

[0026] 201SiN

[0027] 202TiN

[0028] 203 substrate

[0029] 301 Flow Meter

[0030] 302 reaction chamber

[0031] 401 Pre-mixing chamber

[0032] 402 reaction chamber Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0036] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0037] To overcome the aforementioned defects in the prior art, the present invention provides a method for preparing a semiconductor barrier layer and a barrier layer film, which is used to block the interlayer diffusion of oxygen, silicon and metal atoms between the upper and lower layers in a semiconductor structure. At the same time, the deposition formula ratio can be adjusted over a wide range to form a concentration gradient of silicides inside the barrier layer, thereby reducing the internal stress of the film and making it easier for silicides to accumulate in the grain boundaries, thus optimizing the structure of the barrier layer and improving the barrier effect.

[0038] The present invention provides a method for preparing a semiconductor barrier layer, which is used to block the inter-layer diffusion of substances such as oxygen, silicon and metal atoms between upper and lower semiconductor layers. It can be applied to scenarios such as metal gates, polysilicon gates, contact holes and metal interconnects in integrated circuits.

[0039] This preparation method can employ atomic layer deposition (ALD) technology. In each cycle of preparing the barrier layer using ALD, the semiconductor substrate is first heated. In one embodiment, the temperature range for heating the semiconductor substrate is 300–700°C, thereby achieving better deposition reaction results. The following describes the process in conjunction with... Figure 1 The deposition steps of the process are described in detail.

[0040] Figure 1 This is a schematic diagram of time pulses for introducing various gases in one cycle during the process of preparing a barrier layer using atomic layer deposition, according to an embodiment of the present invention.

[0041] Please refer to Figure 1 The deposition reaction begins by introducing a reactive gas. First, within the first pulse time t1, a metal compound gas is introduced into the semiconductor substrate within the reaction chamber for deposition. For example, in... Figure 1 In the examples shown, the metal compound gas can be TiCl4.

[0042] Then, during the second pulse time t2, a carrier gas is introduced for purging. This carrier gas can be Ar or N2.

[0043] Then, NH3 is introduced during the third pulse time t3 to carry out the deposition reaction. Finally, the carrier gas is introduced again during the fourth pulse time t4 for purging. Corresponding to the second pulse time t2, the carrier gas can be Ar or N2.

[0044] In one embodiment, the flow rate of each gas entering the reaction chamber in each cycle can be in the range of 50 to 10000 sccm. During the reaction, the flow rate of each gas can be adjusted in real time according to the process requirements.

[0045] Repeat the above steps multiple times until the preset process requirements are met.

[0046] At the same time, such as Figure 1 As shown, after the initial reaction has passed through one or more cycles, silicon source gas is simultaneously introduced during the first pulse time t1 to deposit the metal compound gas simultaneously. Figure 1 In the illustrated embodiment, the silicon source gas can be a DCS gas, and the silicon nitride and metal nitride obtained by the deposition reaction include TiN and SiN, respectively.

[0047] In other words, during the initial one or more cycles of the reaction, only a metal compound gas, such as TiCl4 gas, is introduced into the reaction chamber for deposition during the first pulse time t1. Subsequently, while the metal compound gas is introduced during the first pulse time t1, a silicon source gas, such as DCS gas, is also introduced simultaneously, and the deposition reaction proceeds concurrently. In other words, a dual-gas pulse deposition reaction is used during the first pulse time t1.

[0048] In one embodiment, optionally, in the semiconductor barrier layer preparation method provided by the present invention, the duration of each cycle of the atomic layer deposition process ranges from 0.1 to 20 s, and the duration of a single pulse ranges from 0.02 to 10 s, which can be adjusted according to different specific process requirements.

[0049] In addition, and more importantly, in the method for preparing the semiconductor barrier layer provided by this invention, as the reaction proceeds, the flow rate ratio of the silicon source gas and the metal compound gas is gradually increased, so that a concentration gradient is formed in the silicon nitride content of the metal nitride deposited in the barrier layer along the direction close to the semiconductor substrate. Combined with Figure 2 It can more clearly show the process steps and results.

[0050] Figure 2 This is a schematic diagram of a semiconductor barrier layer device structure according to an embodiment of the present invention.

[0051] Please refer to Figure 2 In the semiconductor barrier layer 200 deposited using the process described above by the present invention, since only a metal compound gas such as TiCl4 is introduced for deposition in the initial one or more cycles, a crystalline TiN thin film is formed near the substrate 203, which can reduce the resistivity of the semiconductor structure.

[0052] Subsequently, a silicon source gas, such as DCS gas, is simultaneously introduced during the first pulse time t1. As the reaction proceeds and the TiN film grows, the flow rate ratio of the silicon source gas and the metal compound gas, i.e. the ratio of DCS gas to TiCl4, is gradually increased. The atomic layer deposition process cycle is executed cyclically, so that amorphous SiN can accumulate at the grain boundaries of TiN, thus reinforcing the inherent defects of the barrier layer composed only of TiN.

[0053] like Figure 2 As shown, in this process, the barrier layer 200 formed along the direction close to the semiconductor substrate 203 deposits a concentration gradient of silicon nitride (SiN 201) content in the metal nitride TiN 202. That is, in... Figure 2 In the embodiment shown, the concentration of SiN 201 in the barrier layer 200 gradually decreases from top to bottom. Correspondingly, the Si / Ti ratio also forms a concentration gradient from top to bottom, which can reduce the internal stress of the barrier layer 200 and optimize the internal structure of the barrier layer.

[0054] Compared to the existing barrier layer structure in which SiN and TiN are stacked layer by layer, this barrier layer with SiN concentration gradient can enhance the ability of SiN to be enriched at the grain boundaries, thereby improving the longitudinal electron transport efficiency and thus enhancing the barrier performance of the barrier layer.

[0055] In one embodiment, optionally, the gradual increase in the flow ratio of the silicon source gas and the metal compound gas may include: as the reaction proceeds, the flow ratio of the metal compound gas and the silicon source gas introduced into the reaction chamber may be gradually changed from 100:1 to 1:100. The flexible adjustment of the flow ratio can maximize the satisfaction of process requirements, thereby providing operable space for optimizing the internal structure of the barrier layer.

[0056] Accordingly, by adjusting the flow rate of the introduced reaction gas, in one embodiment, the ratio of silicon nitride to metal nitride obtained by the deposition reaction ranges from 0% to 60%.

[0057] It should be noted that both the ratio of reactant gas flow rate and the ratio of deposited compounds mentioned above are exemplary descriptions intended to illustrate that the ratio of reactants in the semiconductor barrier layer preparation method provided by the present invention has a large adjustable range, rather than being used to limit the scope of protection of the present invention. In practical applications, the ratio can be adjusted according to actual process requirements to obtain the optimal performance effect.

[0058] Similarly, in the embodiments provided by this invention, the metal compound gas and silicon source gas are exemplified by TiCl4 and DCS gas, respectively, and the deposits are exemplified by TiN and SiN. The reactant gases and deposited reactants are only illustrative examples and are not intended to limit the scope of protection of this invention. In reality, the metal compound in the deposited reactants can also be TiN, TaN, AlN, GaN, or InN, and SiN can be other silicides. The precursor gas used for atomic layer deposition can also be adjusted and selected accordingly based on actual needs.

[0059] Similarly, the method for preparing the semiconductor barrier layer provided by the present invention does not impose specific limitations on the substrate material. The substrate 200 can be a high-k dielectric, such as Al2O3, TiO2, Ta2O3 or HfO2, or silicon and silicides, such as polycrystalline silicon (poly-Si), SiO2, SiON, SiCO, SiN or SiCON, or elemental metals and alloys, such as W, Al, Cu, Co, Ni, Pb, Ti and their alloys, etc.

[0060] In one embodiment, the method for preparing the semiconductor barrier layer provided by the present invention can optionally be performed using an atomic layer deposition apparatus equipped with a dual-pulse gas intake function or a pre-mixing chamber. The following description, in conjunction with schematic diagrams of the deposition apparatus, will elaborate on these points.

[0061] Figure 3 This is a schematic diagram illustrating the working principle of an atomic layer deposition apparatus with dual-pulse air intake function for preparing a barrier layer according to an embodiment of the present invention.

[0062] Please refer to Figure 3 The reaction equipment is a conventional atomic layer deposition equipment with dual-pulse gas inlet function. It employs a dual-pulse gas inlet process, controlling the flow rate and ratio of DCS gas and TiCl4 introduced into the reaction chamber 302 via flow meters 301 in the corresponding gas pipelines. The inflow and direction of the gas are controlled by various control valves. Figure 1 The cyclic process shown executes deposition, for example, by sequentially introducing TiCl4 and DCS at a set ratio; introducing purge gas; introducing NH3; introducing purge gas again, repeating this cycle multiple times, ultimately yielding the following result: Figure 2 The semiconductor barrier layer structure shown.

[0063] Figures 4A to 4D This is a schematic diagram illustrating the working principle of preparing a barrier layer using an atomic layer deposition apparatus equipped with a pre-mixing chamber, according to an embodiment of the present invention.

[0064] like Figures 4A to 4DAs shown, the semiconductor barrier layer fabrication method provided by this invention can also employ a deposition apparatus with a pre-mixing chamber 401. Similarly, the flow rate and ratio of DCS and TiCl4 entering the reaction chamber 402 can be controlled by a flow meter in the corresponding gas pipeline, and the inflow and outflow of gas in the pre-mixing chamber can be controlled by a control valve. This apparatus can execute the barrier layer fabrication method provided by this invention according to the following steps.

[0065] Step A, as follows Figure 4A As shown, a carrier gas is introduced into the reaction chamber 402 to purge the gas, and the two pre-mixing chambers 401 are introduced with the reaction precursor in proportion.

[0066] Step B, as follows Figure 4B As shown, the precursor gas TiCl4 and DCS in the left pre-mixing chamber 401 are introduced into the reaction chamber 402.

[0067] Step C, as Figure 4C As shown, close the outflow valve of the left pre-mixing chamber 401, and re-introduce the reaction gas into the pre-mixing chamber 401 according to the specified ratio. Only the purging gas remains in the reaction chamber 402; and

[0068] Step D, as follows Figure 4D As shown, the precursor gas NH3 in the right pre-mixing chamber 401 is introduced into the reaction chamber 402.

[0069] Repeat the above loop until you get the following result: Figure 2 The semiconductor barrier layer structure shown.

[0070] The two devices described above are merely illustrative examples and are not intended to limit the scope of protection of this invention. Any equipment or apparatus that can implement the semiconductor barrier layer preparation method provided by this invention can be used to prepare the barrier layer structure and should also be included within the scope of protection of this invention.

[0071] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0072] Another aspect of the present invention provides a barrier layer thin film for a semiconductor, which is prepared on the semiconductor substrate using the preparation method described in any of the above descriptions, wherein the content of silicon nitride obtained by the deposition reaction and the content of metal nitride form a concentration gradient along the direction close to the semiconductor substrate.

[0073] In one embodiment, preferably, in the barrier layer thin film of the semiconductor provided by the present invention, the ratio of silicon nitride to metal nitride obtained by the deposition reaction is between 0% and 60%.

[0074] You can refer to this. Figure 2 , Figure 2 This is a schematic diagram of a semiconductor barrier layer device structure according to an embodiment of the present invention. The specific details have been described in detail in the method section above and will not be repeated here.

[0075] The semiconductor barrier layer preparation method and barrier layer film provided by the present invention are used to block the interlayer diffusion of oxygen, silicon and metal atoms in the upper and lower layers of a semiconductor structure. At the same time, the deposition formula ratio can be adjusted over a wide range to form a concentration gradient of silicides inside the barrier layer, thereby reducing the internal stress of the film and making it easier for silicides to accumulate in the grain boundaries, thus optimizing the structure of the barrier layer and improving the barrier effect.

[0076] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a semiconductor barrier layer, wherein the barrier layer is used to block the interdiffusion of materials between upper and lower semiconductor layers, the fabrication method employing atomic layer deposition (ALD) technology, comprising: In each cycle of preparing the barrier layer using atomic layer deposition (ALD), the semiconductor substrate is heated, and a metal compound gas is introduced into the reaction chamber onto the semiconductor substrate during a first pulse time for deposition. Then, a carrier gas is introduced for purging during a second pulse time, followed by the introduction of NH3 during a third pulse time for deposition reaction, and finally, the carrier gas is introduced again for purging during a fourth pulse time. This process is repeated multiple times until the preset process requirements are met. During the first pulse time of one or more of the initial cycles, only the metal compound gas is introduced for TiN deposition. During the first pulse time after one or more initial cycles, silicon source gas and metal compound gas are simultaneously introduced to aggregate amorphous SiN at the grain boundaries of TiN, and the flow rate ratio of silicon source gas to metal compound gas is gradually increased as the deposition proceeds, so that the content of amorphous SiN in the barrier layer forms a concentration gradient that decreases from top to bottom.

2. The production method according to claim 1, wherein The step of gradually increasing the flow rate ratio of the silicon source gas to the metal compound gas as the deposition proceeds includes: As the reaction proceeds, the flow rate ratio of the metal compound gas and the silicon source gas introduced into the reaction chamber gradually changes from 100:1 to 1:

100.

3. The preparation method according to claim 1, characterized in that, The ratio of SiN to TiN obtained from the deposition reaction ranges from 0% to 60%.

4. The preparation method according to claim 1, characterized in that, The metal compound gas includes TiCl4, and the silicon source gas includes DCS gas.

5. The preparation method according to claim 1, characterized in that, The carrier gas includes Ar or N2. The flow rate of each gas introduced into the reaction chamber during each cycle ranges from 50 to 10,000 sccm.

6. The preparation method according to claim 1, characterized in that, The temperature range of the heated semiconductor substrate is 300~700℃.

7. The preparation method according to claim 1, characterized in that, The duration of each cycle ranges from 0.1 to 20 seconds, and the duration of a single pulse ranges from 0.02 to 10 seconds.

8. The preparation method according to claim 1, characterized in that, The semiconductor substrate includes high-k dielectric, silicon and silicides, as well as elemental metals and alloys.

9. The preparation method according to claim 8, characterized in that, The high-k medium includes Al2O3, TiO2, Ta2O3 and HfO2, the silicon and silicides include polycrystalline silicon, SiO2, SiON, SiCO, SiN and SiCON, and the elemental metals and alloys include W, Al, Cu, Co, Ni, Pb, Ti and their alloys.

10. The preparation method according to any one of claims 1 to 9, characterized in that, The atomic layer deposition equipment with dual-pulse air intake function or a pre-mixing chamber is used.

11. A barrier layer thin film for a semiconductor, prepared on the semiconductor substrate using the preparation method according to any one of claims 1 to 10, wherein, Along the direction close to the semiconductor substrate, the SiN and TiN content obtained by the deposition reaction form a concentration gradient.

12. The barrier layer film as claimed in claim 11, characterized in that, The ratio of SiN to TiN obtained from the deposition reaction ranges from 0% to 60%.

Images