Detecting repetitive patterns in an instruction pipeline of a processor to reduce repetitive fetches

Abstract

Exemplary aspects disclosed herein include detecting a repeating pattern in an instruction pipeline of a processor to reduce repeated fetches. The processor includes a pattern recording circuit configured to receive information in a data stream (e.g., instructions or consumed data) in the instruction pipeline. The pattern recording circuit includes a first-in-first-out (FIFO) table circuit containing an input record column and a plurality of additional adjacent record columns. As new data appears in the data stream, the data recording circuit is configured to sequentially record next incoming data from the data stream into a next input entry of the input record column and then move previously recorded data to adjacent entries of the adjacent record columns. A distance between the input record column and an additional record column having matching data is a distance between repeated occurrences of data in the data stream.

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