Detection circuit and detection method
By designing a detection circuit to simulate the critical path of an integrated circuit and adjusting the signal delay and slew rate, the problem of hold-time violations in integrated circuits was solved, enabling effective detection and avoidance of hold-time violations and improving the stability and reliability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2021-10-28
- Publication Date
- 2026-05-19
AI Technical Summary
When integrated circuits are in operation, factors such as manufacturing process, voltage, temperature and aging may cause signal transmission delays to exceed the design margin, resulting in violations of preparation time or hold time. Existing technologies are difficult to effectively detect and avoid these violations.
Design a detection circuit including a signal generation circuit, a delay-adjustable circuit, and a signal detector. By simulating the critical path of the target circuit, adjust the delay and slew rate of the signal to generate an indication signal to indicate whether a hold-time violation will occur.
It can effectively detect and prevent hold-time violations during integrated circuit operation, ensuring normal circuit operation. By setting a threshold range for the operating voltage, violations can be avoided, improving the stability and reliability of the circuit.
Smart Images
Figure CN116047258B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a detection circuit and a detection method, and more particularly to a detection circuit and a detection method for time violations. Background Technology
[0002] The operating speed of an integrated circuit depends on the degree of signal transmission delay caused by a critical path in the circuit. This critical path is affected by factors such as manufacturing process, voltage, temperature, aging (PVTA). When the transmission delay exceeds the circuit's design slack, the circuit may experience setup time violation or hold time violation. Summary of the Invention
[0003] This invention discloses a detection circuit for detecting whether a target circuit will experience a time violation during operation. The target circuit operates based on a clock signal. The detection circuit includes a signal generation circuit, a first delay adjustable circuit, a second delay adjustable circuit, and a signal detector. The signal generation circuit generates a test signal. The first delay adjustable circuit delays the test signal according to the operating conditions of the target circuit to generate a first delayed signal. The second delay adjustable circuit delays the clock signal according to the operating conditions to generate a second delayed signal. The signal detector generates an indication signal based on the first delayed signal, the second delayed signal, the test signal, and the clock signal. The indication signal indicates whether the operating voltage of the target circuit causes a hold-time violation, a time violation, in the target circuit.
[0004] This invention discloses a detection method for detecting whether a target circuit will experience a timing violation during operation. The target circuit operates based on a clock signal. The detection method includes the following steps: generating a test signal; delaying the test signal according to the operating conditions of the target circuit to generate a first delayed signal; delaying the clock signal according to the operating conditions to generate a second delayed signal; and generating an indication signal based on the first delayed signal, the second delayed signal, the test signal, and the clock signal, wherein the indication signal is used to indicate whether the operating voltage of the target circuit causes a hold-time violation in the target circuit.
[0005] The detection circuit and detection method of the present invention can detect whether the hold time of the target circuit can be coordinated with the operation of the clock signal, so as to avoid the occurrence of hold time violations. Attached Figure Description
[0006] The various embodiments of this application can be best understood after reading the following description and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the drawings are not drawn to scale. In fact, the dimensions of certain features may have been intentionally enlarged or reduced for clarity of description.
[0007] Figure 1 This is a schematic diagram of the detection circuit in some embodiments of the present invention;
[0008] Figure 2 This is a schematic diagram of a delay-adjustable circuit in some embodiments of the present invention;
[0009] Figure 3 This is a schematic diagram of a delay-adjustable circuit in some embodiments of the present invention;
[0010] Figure 4 This is a schematic diagram illustrating the operating voltage range in some embodiments of the present invention.
[0011] Explanation of reference numerals in the attached figures:
[0012] 10 - Detection circuit; 100 - Signal generation circuit; 200 - Adjustable delay circuit
[0013] 210 - Adjustable slew rate and transient rate circuit; 211 - Multiplexer; 220 - Timing-adjustable circuit
[0014] 221-Multiplexer
[0015] 300 - Adjustable delay circuit; 310 - Adjustable slew rate circuit; 311 - Multiplexer
[0016] 320 - Timing Adjustable Circuit; 321 - Multiplexer; 400 - Signal Detector
[0017] 410-Reaction Unit 420-Reaction Unit b-Buffer
[0018] clk - clock signal; g - floating gate; ll - lower limit value
[0019] p1-path p2-path p3-path
[0020] p4-path p5-path p6-path
[0021] p7-path p8-path p9-path
[0022] p10-path p11-path p12-path
[0023] p13-path p14-path r1-operating voltage range
[0024] r2 - Operating voltage range r3 - Operating voltage range sd1 - Delay signal
[0025] sd2 - Delayed signal sd3 - Delayed signal sd4 - Delayed signal
[0026] si - indicator signal sr1 - response signal sr2 - response signal
[0027] st - test signal; ul - upper limit value; vmax - maximum value
[0028] vmin - minimum value; vth1 - first threshold; vth2 - second threshold Detailed Implementation
[0029] Figure 1 This is a schematic diagram of an embodiment of the detection circuit 10 of the present invention. The detection circuit 10 is used to detect whether a target circuit (not shown) will violate timing rules during operation, wherein the target circuit operates according to a clock signal clk. The detection circuit 10 and the target circuit are disposed in the same integrated circuit, but the present invention is not limited thereto.
[0030] The operation of the target circuit is affected by operating conditions, which include at least one of the target circuit's manufacturing process, current operating voltage, current temperature, and current aging level. Under different operating conditions, the signal delay within the target circuit varies. When the signal delay within the target circuit exceeds its design margin, a timing violation may occur. More specifically, when the signal delay is too severe, it may cause deviations in the target circuit's setup time and hold time, or even prevent it from operating normally in sync with the clock signal, resulting in setup time or hold time violations. To avoid timing violations, the detection circuit 10 detects whether a timing violation will occur based on the target circuit's operating conditions. In some embodiments, the detection circuit 10 is used to detect whether a hold time violation will occur.
[0031] In some embodiments, the target circuit has a critical path, which is the signal path with the smallest delay or the path with the largest timing offset among any two consecutive flip-flops in the target circuit; that is, the critical path is the place in the target circuit most prone to hold-time violations. The detection circuit 10 and the target circuit are housed on the same chip, and both have almost identical process drift, voltage, and ambient temperature variability factors. Therefore, they can be used to simulate the delay caused by the critical path to detect whether timing violations will occur in the target circuit.
[0032] The detection circuit 10 operates based on a clock signal clk. The detection circuit 10 may include a signal generation circuit 100, a delay-adjustable circuit 200, a delay-adjustable circuit 300, and a signal detector 400. The signal generation circuit 100 generates a test signal st, which is delayed by the delay-adjustable circuit 200 to become a delayed signal sd1 and then transmitted to the signal detector 400. The clock signal clk is delayed by the delay-adjustable circuit 300 to become a delayed signal sd2 and then transmitted to the signal detector 400. In other words, the delayed signals sd1 and sd2 are the delayed test signal st and clock signal clk, respectively.
[0033] In some embodiments, the test signal st is a rising signal, such as a digital signal represented by the digital sequence "01", but the invention is not limited thereto. The test signal st can also be a falling signal, such as a digital signal represented by the digital sequence "10".
[0034] Adjustable delay circuits 200 and 300 delay the test signal *st* and clock signal *clk* respectively, based on the operating conditions of the target circuit. Generally, signal delay is related to the trace length of the transmission path. However, due to advancements in process technology and circuit speed, setup time and hold time violations must also consider the signal slew rate and the timing skew of the clock reaching each flip-flop. For example, when the operating voltage of the target circuit increases, the signal slew rate increases, thus shortening the time it takes for the signal to reach a predetermined voltage value (e.g., the time from 0 to 1 becomes shorter). Conversely, when the operating voltage decreases, the signal slew rate decreases, thus lengthening the time it takes for the signal to reach the predetermined voltage value (e.g., the time from 0 to 1 becomes longer). Adjustable delay circuits 200 and 300 are used to adjust the slew rate and timing skew of the test signal *st* and clock signal *clk*, respectively.
[0035] As mentioned above, since the detection circuit 10 is used to simulate the critical path in the target circuit, the delay adjustable circuit 200 and the delay adjustable circuit 300 adjust the timing offset and slew rate of the test signal st and the clock signal clk respectively according to the load and trace length of the critical path.
[0036] Generally, the slew rate of a signal is related to both the load of the transmission path and the operating voltage of the circuit; in some embodiments, the operating voltage and the signal slew rate are positively correlated. Therefore, the delay adjustable circuit 200 and the delay adjustable circuit 300 can also adjust the slew rates of the test signal st and the clock signal clk respectively according to the operating voltage of the target circuit. In some embodiments, when the operating voltage of the target circuit is too high, the hold time of the data signal will be insufficient, resulting in a hold time violation. The detection circuit 10 is used to obtain the maximum value of the operating voltage when the target circuit does not experience a hold time violation (e.g., Figure 4 The first threshold (vth1) is shown. In other embodiments, when the operating voltage of the target circuit is too low, the slew rate of the clock signal will be too low, causing the predetermined voltage level to be reached too slowly, resulting in a hold-time violation. The detection circuit 10 is used to obtain the minimum value of the operating voltage in which the target circuit does not experience a hold-time violation (e.g., ...). Figure 4 The second threshold (vth2) is shown. It should be noted that establishment time violations are not within the scope of this application.
[0037] The signal detector 400 includes a response unit 410, a response unit 420, and a comparator 430. In some embodiments, the response units 410 and 420 are triggers, such as D-type triggers. For ease of understanding, the response units 410 and 420 are described below using D-type triggers as an example.
[0038] Response unit 410 receives the delayed signal sd1 and generates a response signal sr1 from the delayed signal sd2 (the delayed clock signal clk) when the rising edge of the delayed signal sd2 arrives at response unit 410. Response unit 420 receives the test signal st and generates a response signal sr2 from the test signal st when the rising edge of the clock signal clk arrives at response unit 420. When the test signal st is the digital sequence "01", response unit 420 generates a response signal sr2 with the digital sequence "01" sequentially according to the clock signal clk. Similarly, response unit 410 receives the delayed signal sd1 (the delayed test signal st, which is still the digital sequence "01") and generates a response signal sr1 with the digital sequence "01" according to the delayed signal sd2.
[0039] When the hold time of the delayed signal sd1 in the reaction unit 410 can be coordinated with the delayed signal sd2 to enable the reaction unit 410 to operate normally, the reaction unit 410 generates a reaction signal sr1 that is the same as the reaction signal sr2, i.e., the reaction signal sr1 is the digital sequence "01". Therefore, when there is no hold time violation, the reaction signal sr1 is the same as the reaction signal sr2. The comparator 430 receives the reaction signal sr1 and the reaction signal sr2 and generates an indication signal si with a first level, wherein the indication signal si with the first level is used to indicate that no hold time violation has occurred.
[0040] A hold-time violation occurs when the hold time of the delayed signal sd1 in the response unit 410 cannot be synchronized with the hold time of the delayed signal sd2 to enable the response unit 410 to operate normally. When the response unit 410 receives the rising edge of the delayed signal sd2, since the delayed signal sd1 received by the response unit 410 is no longer held at the correct voltage level, the response signal sr1 generated by the response unit 410 is different from the response signal sr2. The comparator 430 receives the response signals sr1 and sr2 and generates an indication signal si with a second level, which is used to indicate that a hold-time violation has occurred.
[0041] refer to Figure 2 . Figure 2 This is a schematic diagram of an embodiment of the delay-adjustable circuit 200. The delay-adjustable circuit 200 includes a slew rate adjustable circuit 210 and a timing adjustable circuit 220. The slew rate adjustable circuit 210 and the timing adjustable circuit 220 are connected in series. Figure 2 In this embodiment, the timing-adjustable circuit 220 is connected in series after the slew rate-adjustable circuit 210; however, the invention is not limited thereto. In other embodiments, the slew rate-adjustable circuit 210 is connected in series after the timing-adjustable circuit 220.
[0042] The slew rate adjustable circuit 210 includes a multiplexer 211, path p1, path p2, and path p3. The multiplexer 211 receives a test signal st through one of the paths p1, p2, and p3. When the slew rate adjustable circuit 210 receives the test signal st, paths p1, p2, and p3 delay the test signal st according to their respective loads. The multiplexer 211 selects whether the test signal st transmitted by path p1, p2, or p3 is output as a delayed signal sd3 and transmitted to the timing adjustable circuit 220.
[0043] Paths p1, p2, and p3 each include a different number of floating gates g. For example... Figure 2As shown, paths p1, p2, and p3 include 4, 2, and 1 floating gates g, respectively. The more floating gates g there are, the greater the load on paths p1, p2, and p3. Therefore, when the test signal st passes through paths p1, p2, and p3, the test signal st will be adjusted to different slew rates due to the different loads.
[0044] The timing-adjustable circuit 220 includes a multiplexer 221 and paths p4, p5, p6, and p7. Multiplexer 221 receives a delayed signal sd3 via one of paths p4, p5, p6, or p7. When the timing-adjustable circuit 220 receives the delayed signal sd3, paths p4, p5, p6, and p7 respectively delay the delayed signal sd3. Multiplexer 221 selects whether the delayed signal sd3 transmitted via path p4, p5, p6, or p7 is output as a delayed signal sd1 and transmitted to the signal detector 400.
[0045] Paths p4, p5, p6, and p7 each include a different number of buffers b. For example... Figure 2 As shown, paths p4, p5, p6, and p7 include 0, 1, 2, and 3 buffers b, respectively. The more buffers b there are, the greater the timing offset on paths p4, p5, p6, and p7. Therefore, when the delayed signal sd3 passes through paths p4, p5, p6, and p7, the delayed signal s3 will be adjusted to have different timing offsets due to the different numbers of buffers b it passes through.
[0046] The number of paths included in the slew rate adjustable circuit 210 and the timing adjustable circuit 220, as well as the number of components (e.g., floating gates, buffers) on those paths, are not limited to the following. Figure 2 As shown. Various numbers of paths are all within the scope and consideration of this invention.
[0047] Figure 3 This is a schematic diagram of an embodiment of the delay-adjustable circuit 300. The delay-adjustable circuit 200 is similar to the delay-adjustable circuit 300; for simplicity, the structure and operation of the delay-adjustable circuit 300 will not be described in detail here.
[0048] Please also refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 The detection circuit 10 is used to determine a first threshold vth1 and a second threshold vth2 of the operating voltage of the target circuit, wherein the first threshold and the second threshold represent the upper limit and lower limit of the operating voltage of the target circuit, respectively.
[0049] The target circuit's specifications include a range of operating voltages (with a maximum value vmax and a minimum value vmin). However, due to different manufacturing processes, temperatures, and aging levels, the circuit characteristics of the target circuit deviate, causing the operating voltage range r1 determined by the specifications to exceed the actual feasible operating voltage range r2 (defined by a first threshold vth1 and a second threshold vth2). Therefore, a detection circuit is used to detect the characteristics of the target circuit near the maximum value vmax and minimum value vmin of the operating voltage range r1 to determine the feasible operating voltage range r2 of the target circuit.
[0050] When the detection circuit 10 determines the first threshold vth1, the multiplexer 211 selects to output the test signal st transmitted through path p3 as a delayed signal sd3, where path p3 has the smallest load among paths p1 to p3, and the load of path p3 corresponds to the operating voltage vmax. Next, the multiplexer 321 selects to output the delayed signal sd4 transmitted through path p14 as a delayed signal sd2, where the timing offset caused by path p14 to the delayed signal sd4 corresponds to the timing offset caused by the critical path in the target circuit. More specifically, when the operating voltage vmax is applied to the target circuit, the change in slew rate on the critical path is equivalent to the delay of path p3 on the test signal st, and the resulting timing offset is equivalent to the delay of path p14 on the delayed signal sd4. Based on the simulated operating voltage vmax and the critical path operating conditions, the detection circuit 10 then uses at least one of multiplexers 211, 221, 311, and 321 to adjust the delay level of the delay signals sd1 and / or sd2, thereby determining the first threshold vth1. In other words, when multiplexers 211, 221, 311, and 321 select different paths p1 to p14 to generate different levels of delay, these combinations of selected paths p1 to p14 correspond to different operating conditions of the target circuit (i.e., different operating voltages, temperatures, and / or aging levels), and different operating conditions correspond to different operating speeds of the target circuit.
[0051] Similarly, when the detection circuit 10 is used to determine the first threshold vth2, the multiplexer 211 is used to select the test signal st transmitted by path p1 as a delayed signal sd3, which corresponds to the operating voltage vmin. Under the simulated operating voltage vmin and the operating conditions of the critical path, the detection circuit 10 then uses at least one of multiplexers 211, 221, 311 and 321 to adjust the delay level of the delayed signals sd1 and / or sd2, thereby determining the first threshold vth2.
[0052] When the operating voltage exceeds Figure 4When the feasible operating voltage range r2 is shown, the target circuit experiences a hold-time violation. In a further embodiment, the detection circuit 10 is used to prevent the target circuit from experiencing a hold-time violation. Therefore, before a hold-time violation actually occurs, the detection circuit 10 generates an indicator signal si to indicate that a hold-time violation is about to occur. Specifically, to avoid an unstable situation where the operating voltage is exactly equal to either a first threshold vth1 or a second threshold vth2, the detection circuit 10 determines an operating voltage range r3, wherein the upper limit of the operating voltage range r3, ul, is less than the first threshold vth1, and the lower limit of the operating voltage range r3, ll, is greater than the second threshold vth2. When the operating voltage exceeds the operating voltage range r3, the detection circuit 10 generates an indicator signal si to indicate that a hold-time violation has occurred.
[0053] The foregoing description of this specification briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to more fully understand the various embodiments contained herein. Those skilled in the art should understand that they can easily use this application as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as these embodiments. Those skilled in the art should understand that these equivalent embodiments still fall within the spirit and scope of this application, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this application.
Claims
1. A detection circuit for detecting whether a timing violation has occurred in a target circuit, said target circuit operating according to a clock signal, comprising: A signal generation circuit is used to generate a test signal; A first delay adjustable circuit is used to delay the test signal according to an operating condition of the target circuit to generate a first delay signal; A second delay adjustable circuit is configured to delay the clock signal according to the operating conditions to generate a second delayed signal; and A signal detector is configured to generate an indication signal based on the first delayed signal, the second delayed signal, the test signal, and the clock signal, wherein the indication signal is used to indicate whether an operating voltage of the target circuit causes a hold-time violation in the time violation. The signal detector includes: A first reaction unit is configured to generate a first reaction signal based on the first delayed signal and the second delayed signal; A second reaction unit, configured to generate a second reaction signal based on the test signal and the clock signal; and A comparator is used to compare the first response signal with the second response signal to generate the indication signal. When the first reaction signal is different from the second reaction signal, the indication signal is used to indicate that the operating voltage of the target circuit causes the target circuit to experience the hold time violation; and when the first reaction signal is the same as the second reaction signal, the indication signal is used to indicate that the operating voltage of the target circuit does not cause the target circuit to experience the hold time violation.
2. The detection circuit according to claim 1, characterized in that, The first delay-adjustable circuit includes: A first slew rate adjustable circuit is used to adjust the slew rate of the test signal according to the operating conditions; and A first timing adjustable circuit is used to adjust a timing offset of the test signal according to the operating conditions.
3. The detection circuit according to claim 1, characterized in that, The second delay-adjustable circuit includes: A second slew rate adjustable circuit is used to adjust the slew rate of the clock signal according to the operating conditions; and A second timing-adjustable circuit is used to adjust a timing offset of the clock signal according to the operating conditions.
4. A detection method for detecting whether a timing violation has occurred in a target circuit, said target circuit operating according to a clock signal, comprising: Generate a test signal; The test signal is delayed according to an operating condition of the target circuit to generate a first delayed signal; The clock signal is delayed according to the operating conditions to generate a second delayed signal; and An indication signal is generated based on the first delay signal, the second delay signal, the test signal, and the clock signal, wherein the indication signal is used to indicate whether an operating voltage of the target circuit causes the target circuit to experience a hold-time violation among the time violations.
5. The detection method according to claim 4, characterized in that, The step of generating the indication signal based on the first delay signal and the clock signal includes: A first response signal is generated based on the first delayed signal and the second delayed signal; A second response signal is generated based on the test signal and the clock signal; and The first response signal is compared with the second response signal to generate the indication signal. When the first reaction signal is different from the second reaction signal, the indication signal is used to indicate that the operating voltage of the target circuit causes the target circuit to experience the hold time violation; and when the first reaction signal is the same as the second reaction signal, the indication signal is used to indicate that the operating voltage of the target circuit does not cause the target circuit to experience the hold time violation.
6. The detection method according to claim 4, characterized in that, The detection method further includes: A first threshold is determined based on the indication signal, wherein the first threshold represents an upper limit of the operating voltage of the target circuit, and wherein the first threshold is less than a maximum value of the operating voltage. The step of generating the indication signal based on the first delay signal, the second delay signal, the test signal, and the clock signal includes: Based on the maximum value of the operating voltage of the target circuit, the operating conditions are adjusted to adjust the first delay signal and the second delay signal; and The indication signal is generated based on the adjusted first delay signal, the adjusted second delay signal, the test signal, and the clock signal.
7. The detection method according to claim 6, characterized in that, The detection method further includes: A second threshold is determined based on the indication signal, wherein the second threshold represents a lower voltage operating limit of the operating voltage of the target circuit, and wherein the second threshold is greater than a minimum value of the operating voltage. The step of generating the indication signal based on the first delay signal, the second delay signal, the test signal, and the clock signal further includes: Based on the maximum value of the operating voltage of the target circuit, the operating conditions are adjusted to adjust the first delay signal and the second delay signal; and The indication signal is generated based on the adjusted first delay signal, the adjusted second delay signal, the test signal, and the clock signal.
8. The detection method according to claim 7, characterized in that, When the operating voltage of the target circuit exceeds a range defined by the first threshold and the second threshold, the indication signal is also used to indicate that the hold time violation has occurred.