Active element substrate

Abstract

An active element substrate includes a substrate, a first active element, and a second active element electrically connected to the first active element. The first active element includes a first bottom gate, a first semiconductor structure, a first top gate, a first source, and a first drain. The first source is electrically connected to the first bottom gate. The second active element includes a second bottom gate, a second semiconductor structure, a second top gate, a second source, and a second drain. The second semiconductor structure has a thickness less than a thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate.

Description

Technical Field

[0001] This invention relates to an active element substrate. Background Technology

[0002] Thin-film transistors (TFTs) are a type of field-effect transistor (FET), formed by depositing multiple layers of metal, semiconductor, and dielectric layers on a glass substrate. Currently, many electronic devices incorporate TFTs for various applications. For example, many display devices include TFT array substrates, which contain switching elements and driving elements. The switching elements control the gates of the driving elements. By cooperating with the driving elements, the magnitude of the current flowing through the driving elements can be controlled. Summary of the Invention

[0003] The present invention provides an active component substrate that can improve the reliability of the first active component being turned on for a long time, while increasing the turn-on current of the second active component.

[0004] At least one embodiment of the present invention provides an active element substrate. The active element substrate includes a substrate, a first active element, and a second active element electrically connected to the first active element. The first active element and the second active element are located on the substrate. The first active element includes a first bottom gate, a first semiconductor structure, a first top gate, a first source, and a first drain. The first semiconductor structure is located between the first bottom gate and the first top gate. The first source and the first drain are electrically connected to the first semiconductor structure. The first source is electrically connected to the first bottom gate. The second active element includes a second bottom gate, a second semiconductor structure, a second top gate, a second source, and a second drain. The second semiconductor structure is located between the second bottom gate and the second top gate. The thickness of the second semiconductor structure is less than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate. The second source and the second drain are electrically connected to the second semiconductor structure. Attached Figure Description

[0005] Figure 1A This is a top view schematic diagram of an active element substrate according to an embodiment of the present invention;

[0006] Figure 1B yes Figure 1A Cross-sectional schematic diagrams of lines a-a', b-b', and c-c';

[0007] Figure 2A These are experimental data graphs showing the thickness of the first semiconductor structure of the first active element versus the threshold voltage in some embodiments of the present invention.

[0008] Figure 2BThese are experimental data graphs showing the thickness and turn-on current of the first semiconductor structure of the first active element in some embodiments of the present invention.

[0009] Figure 3 This is a schematic diagram showing the decay of the turn-on current and the change of the threshold voltage of the first active element after long-term operation in some embodiments of the present invention.

[0010] Figures 4A to 4D This is a cross-sectional schematic diagram of the manufacturing method of the active component substrate shown in Figure 1;

[0011] Figure 5 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;

[0012] Figure 6 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;

[0013] Figures 7A to 7D yes Figure 6 A cross-sectional schematic diagram of the manufacturing method of the active component substrate;

[0014] Figure 8 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;

[0015] Figure 9 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;

[0016] Figure 10 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0017] Symbol Explanation

[0018] 10, 20, 30, 40: Active component substrate

[0019] a-a',b-b',c-c': lines

[0020] BG1: First bottom gate

[0021] BG2: Second bottom gate

[0022] BG3: Third bottom gate

[0023] BL: Buffer Layer

[0024] C: Capacitor

[0025] ch1: First Channel Area

[0026] ch2: Second Channel Area

[0027] ch3: Third Channel Area

[0028] D1: First drain electrode

[0029] D2: Second drain electrode

[0030] D3: Third drain electrode

[0031] dr1: First drain region

[0032] dr2: Second drain region

[0033] dr3: Third drain region

[0034] GI1: First gate dielectric layer

[0035] GI2: Second gate dielectric layer

[0036] GI3: Third gate dielectric layer

[0037] H1~H6, V1~V3, V2': Contact holes

[0038] ILD1: First interlayer dielectric layer

[0039] ILD2: Second interlayer dielectric layer

[0040] OS1, OS1': First semiconductor layer

[0041] OS2, OS2': Second semiconductor layer

[0042] P: Doping fabrication process

[0043] PL: Protective layer

[0044] PX: Pixel Circuit

[0045] S1: First Source

[0046] S2: Second source pole

[0047] S3: Third source pole

[0048] SB:Substrate

[0049] SM1, SM1': First semiconductor structure

[0050] SM2, SM2': Second semiconductor structure

[0051] SM3: Third semiconductor structure

[0052] sr1: First source region

[0053] sr2: Second source pole region

[0054] sr3: Third source pole region

[0055] TFT1: First active element

[0056] TFT2: Second active element

[0057] TFT3: Third active element

[0058] TG1: First top gate

[0059] TG2: Second top gate

[0060] TG3: Third top gate

[0061] t1~t3: Thickness

[0062] V COM Common line voltage

[0063] V DD V SS :Voltage

[0064] V DL Data line voltage

[0065] V SCAN1 First scan line voltage

[0066] V SCAN2 Second scan line voltage Detailed Implementation

[0067] Figure 1A This is a top view schematic diagram of an active element substrate according to an embodiment of the present invention. Figure 1B yes Figure 1A A schematic diagram of the cross-sections of lines a-a', b-b', and c-c'. For ease of explanation, Figure 1A The active element substrate 10 is shown with a first bottom gate BG1, a first top gate TG1, a first source S1, a first drain D1, a second bottom gate BG2, a second top gate TG2, a second source S2, and a second drain D2, with other components omitted.

[0068] Please refer to Figures 1A to 1B The active element substrate 10 includes a substrate SB, a first active element TFT1, and a second active element TFT2. In some embodiments, the second active element TFT2 is electrically connected to the first active element TFT1, but the present invention is not limited thereto.

[0069] The substrate SB can be made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., conductive materials, metals, wafers, ceramics, or other suitable materials) or other suitable materials. If conductive materials or metals are used, an insulating layer (not shown) is applied to the substrate SB to prevent short circuits. In some embodiments, the substrate SB is a flexible substrate, and the material of the substrate SB is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.

[0070] The buffer layer BL is located on the substrate SB. The buffer layer BL is a single layer or a multilayer structure, and the material of the buffer layer BL may include silicon oxide, silicon oxynitride or other suitable materials or a stack of the above materials.

[0071] The first active element TFT1 and the second active element TFT2 are located on the substrate SB. In this embodiment, the first active element TFT1 and the second active element TFT2 are located on the buffer layer BL.

[0072] The first active element TFT1 includes a first bottom gate BG1, a first semiconductor structure SM1, a first top gate TG1, a first source S1, and a first drain D1. The second active element TFT2 includes a second bottom gate BG2, a second semiconductor structure SM2, a second top gate TG2, a second source S2, and a second drain D2.

[0073] The first bottom gate BG1 and the second bottom gate BG2 are located on the buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 comprise the same or different materials. In some embodiments, the materials of the first bottom gate BG1 and the second bottom gate BG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first bottom gate BG1 and the second bottom gate BG2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.

[0074] A first gate dielectric layer GI1 is located on a first bottom gate BG1 and a second bottom gate BG2. In this embodiment, the first gate dielectric layer GI1 contacts the upper surfaces of the first bottom gate BG1 and the second bottom gate BG2. In some embodiments, the material of the first gate dielectric layer GI1 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials.

[0075] A first semiconductor structure SM1 and a second semiconductor structure SM2 are located on a first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between a first bottom gate BG1 and the first semiconductor structure SM1, and between a second bottom gate BG2 and the second semiconductor structure SM2. In some embodiments, the first semiconductor structure SM1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. Similarly, the second semiconductor structure SM2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 located between the second source region sr2 and the second drain region dr2. The first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2 are doped (e.g., hydrogen doped) to have a resistivity lower than that of the first channel region ch1 and the second channel region ch2.

[0076] In this embodiment, the thickness t2 of the second semiconductor structure SM2 is less than the thickness t1 of the first semiconductor structure SM1. In some embodiments, by increasing the thickness t1 of the first semiconductor structure SM1, the resistivity of the first channel region ch1 can be reduced, thereby reducing the threshold voltage (Vth) of the first active element TFT1 and increasing the turn-on current of the first active element TFT1.

[0077] The first semiconductor structure SM1 can be a single-layer structure or a multi-layer structure. In this embodiment, the first semiconductor structure SM1 is a multi-layer structure and includes a first semiconductor layer OS1 and a second semiconductor layer OS2. The second semiconductor layer OS2 overlaps the first semiconductor layer OS1, and the first semiconductor layer OS1 is closer to the substrate SB than the second semiconductor layer OS2. In some embodiments, the second semiconductor structure SM2 is a single-layer structure, and the second semiconductor layer OS2 and the second semiconductor structure SM2 belong to the same patterning layer.

[0078] In some embodiments, the materials of the first semiconductor layer OS1, the second semiconductor layer OS2, and the second semiconductor structure SM2 include quaternary metal compounds such as indium gallium tin zinc oxide (IGTZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO), or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or lanthanide rare earth doped metal oxides (e.g., Ln-IZO). In some embodiments, the first semiconductor layer OS1 and the second semiconductor layer OS2 may comprise the same or different materials.

[0079] The second gate dielectric layer GI2 is located on the first gate dielectric layer GI1, the first semiconductor structure SM1, and the second semiconductor structure SM2. The first semiconductor structure SM1 and the second semiconductor structure SM2 are sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2. In some embodiments, the material of the second gate dielectric layer GI2 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials.

[0080] The first top gate TG1 and the second top gate TG2 are located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1, and between the second top gate TG2 and the second semiconductor structure SM2. The first semiconductor structure SM1 is located between the first bottom gate BG1 and the first top gate TG1. The second semiconductor structure SM2 is located between the second bottom gate BG2 and the second top gate TG2. In some embodiments, the first top gate TG1 and the second top gate TG2 comprise the same or different materials. In some embodiments, the materials of the first top gate TG1 and the second top gate TG2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first top gate TG1 and the second top gate TG2 can also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

[0081] In this embodiment, the second active element TFT2 is a dual-gate thin-film transistor (hereinafter referred to as a TG-sync thin-film transistor) in which the second bottom gate BG2 is electrically connected to the second top gate TG2. For example, the second top gate TG2 is connected to the second bottom gate BG2 through a contact hole V1, wherein the contact hole V1 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

[0082] The first interlayer dielectric layer ILD1 is located on the first top gate TG1 and the second top gate TG2. The second interlayer dielectric layer ILD2 is located on the first interlayer dielectric layer ILD1. In some embodiments, the materials of the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 include silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials, or other suitable materials.

[0083] The first source S1, the first drain D1, the second source S2, and the second drain D2 are located on the second interlayer dielectric layer ILD2. The first source S1 and the first drain D1 are electrically connected to the first source region sr1 and the first drain region dr1 of the first semiconductor structure SM1 through contact holes H1 and H2, respectively. The second source S2 and the second drain D2 are electrically connected to the second source region sr2 and the second drain region dr2 of the second semiconductor structure SM2 through contact holes H3 and H4, respectively. The contact holes H1 to H4 pass through the second gate dielectric layer GI2, the first interlayer dielectric layer ILD1, and the second interlayer dielectric layer ILD2. In some embodiments, the materials of the first source S1, the first drain D1, the second source S2, and the second drain D2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first source S1, the first drain D1, the second source S2, and the second drain D2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties. A protective layer PL covers the first source S1, the first drain D1, the second source S2, and the second drain D2.

[0084] In this embodiment, the first active element TFT1 is a dual-gate thin-film transistor (referred to herein as a source-sync thin-film transistor) with its first source S1 electrically connected to the first bottom gate BG1. For example, the first source S1 is connected to the first bottom gate BG1 through a contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1, the second gate dielectric layer GI2, the first interlayer dielectric layer ILD1, and the second interlayer dielectric layer ILD2. In other embodiments, the first source S1 does not directly contact the first bottom gate BG1, and the first source S1 is electrically connected to the first bottom gate BG1 through other transition electrodes.

[0085] Table 1 compares the various characteristics of TG-sync and source-sync thin-film transistors with the same semiconductor structure. In Table 1, ◎ represents excellent, ○ represents acceptable, and ▽ represents poor.

[0086] Table 1

[0087]

[0088]

[0089] Table 1 shows that TG-Sync thin-film transistors are suitable for use as switching TFTs. Connecting the top gate to the bottom gate increases the turn-on current. Although TG-Sync thin-film transistors suffer from PBTS (Positive gate bias temperature stress), the relatively short turn-on time required for switching TFTs makes their use in switching TFTs less prone to reliability issues.

[0090] Furthermore, Source-Sync thin-film transistors are suitable for use as driving thin-film transistors (TFTs). The bottom gate is electrically connected to the source, which increases the reliability of long-term on-time operation. However, because the bottom gate is electrically connected to a low potential (e.g., ground), the turn-on current of the Source-Sync thin-film transistor is reduced.

[0091] exist Figures 1A to 1B In this embodiment, by increasing the thickness t1 of the first semiconductor structure SM1, the problem of low turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. Furthermore, since the thickness t2 of the second semiconductor structure SM2 is relatively small, the leakage current problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

[0092] Figure 2A This is an experimental data graph showing the thickness of the first semiconductor structure and the threshold voltage of a first active element (Source-Sync thin film transistor) according to some embodiments of the present invention. Figure 2A The relationship between the thickness of the first semiconductor structure and the threshold voltage is shown in a first condition and in a second condition. The difference between the first and second conditions is that in the first condition, the thickness of the first gate dielectric layer GI1 (see reference) is increased. Figure 1B In the first case, the ratio of nitrogen dioxide to silanol is relatively high, and the thickness of the first gate dielectric layer GI1 is 1800 angstroms; in the second case, during the deposition of the first gate dielectric layer GI1 (see reference...), Figure 1B When nitrogen dioxide is present, the ratio of nitrogen dioxide to silane is relatively low, and the thickness of the first gate dielectric layer GI1 is 2150 angstroms.

[0093] Figure 2B This is an experimental data graph showing the thickness and turn-on current of the first semiconductor structure of the first active element (Source-Sync thin film transistor) according to some embodiments of the present invention.

[0094] Depend on Figure 2A and Figure 2B It can be seen that with the first semiconductor structure SM1 (please refer to...) Figure 1B As the thickness t1 of the first active element TFT1 increases, the threshold voltage of the first active element TFT1 decreases and the turn-on current increases.

[0095] Figure 3 This refers to the decay of the turn-on current (Ion drop) and the change in the threshold voltage (Vth shift) of the first active element (Source-Sync thin-film transistor) after prolonged operation according to some embodiments of the present invention. Figure 3 In this process, the first active element operates at 90°C for 1 hour, wherein the voltage difference Vds between the first drain and the first source is 20V, and the operating current is 100uA. Furthermore, in... Figure 3 In the first active element, the width of the first channel region is 50 micrometers and the length is 6 micrometers.

[0096] Depend on Figure 3 It can be seen that as the thickness of the first semiconductor structure increases, the current decay of the first active element after long-term operation is smaller, and the decay of the threshold voltage is also smaller.

[0097] Figures 4A to 4D This is a cross-sectional schematic diagram of the manufacturing method of the active element substrate 10 in Figure 1.

[0098] Please refer to Figure 4A A first bottom gate BG1 and a second bottom gate BG2 are formed on a buffer layer BL. In some embodiments, the method of forming the first bottom gate BG1 and the second bottom gate BG2 includes: forming a conductive material layer (not shown) on the buffer layer BL; forming a patterned photoresist layer (not shown) on the conductive material layer; etching the conductive material layer using the patterned photoresist layer as a mask to form the first bottom gate BG1 and the second bottom gate BG2; and finally, removing the patterned photoresist layer. In other words, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterned layer.

[0099] Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2. Then, a first semiconductor layer OS1' is formed on the first gate dielectric layer GI1. The first semiconductor layer OS1' overlaps the first bottom gate BG1.

[0100] Please refer to Figure 4B A second semiconductor layer OS2' is formed on the first semiconductor layer OS1', and a second semiconductor structure SM2' is formed on the first gate dielectric layer GI1. The second semiconductor structure SM2' overlaps the second bottom gate BG2. In some embodiments, the method of forming the second semiconductor layer OS2' and the second semiconductor structure SM2' includes: forming a semiconductor material layer (not shown) on the first gate dielectric layer GI1 and the first semiconductor layer OS1'; forming a patterned photoresist layer (not shown) on the semiconductor material layer; etching the semiconductor material layer using the patterned photoresist layer as a mask to form the second semiconductor layer OS2' and the second semiconductor structure SM2'; and finally, removing the patterned photoresist layer. In other words, the second semiconductor layer OS2' and the second semiconductor structure SM2' belong to the same patterned layer.

[0101] In this embodiment, the first semiconductor structure SM1' includes a stack of a first semiconductor layer OS1' and a second semiconductor layer OS2'. Therefore, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

[0102] Please refer to Figure 4C A second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the second semiconductor structure SM2'.

[0103] Next, a first top gate TG1 and a second top gate TG2 are formed on the second gate dielectric layer GI2. In some embodiments, the method of forming the first top gate TG1 and the second top gate TG2 includes: forming a conductive material layer (not shown) on the second gate dielectric layer GI2; forming a patterned photoresist layer (not shown) on the conductive material layer; etching the conductive material layer using the patterned photoresist layer as a mask to form the first top gate TG1 and the second top gate TG2; and finally, removing the patterned photoresist layer. In other words, the first top gate TG1 and the second top gate TG2 belong to the same patterned layer.

[0104] Using the first top gate TG1 and the second top gate TG2 as masks, a doping fabrication process P is performed to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1, and a first channel region ch1, and a second semiconductor structure SM2 including a second source region sr2, a second drain region dr2, and a second channel region ch2. In some embodiments, the doping fabrication process P is, for example, hydrogen plasma doping or other suitable fabrication processes.

[0105] In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form a contact hole V1 that exposes the second bottom gate BG2. Then, the second top gate TG2 is formed in the contact hole V1 to electrically connect to the second bottom gate BG2.

[0106] Please refer to Figure 4D A first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2. A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Next, one or more etching processes are performed to form contact holes H1 to H4 that expose the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2. In some embodiments, a contact hole V2 exposing the first bottom gate BG1 is formed simultaneously with the formation of contact holes H1 to H4.

[0107] Finally, please return to Figures 1A to 1B A first source S1, a first drain D1, a second source S2, and a second drain D2 are formed on the second interlayer dielectric layer ILD2, and the first source S1, the first drain D1, the second source S2, and the second drain D2 are respectively filled into contact holes H1 to H4. In some embodiments, the first source S1 is also filled into contact hole V2.

[0108] Finally, a protective layer PL is selectively formed on the first source S1, the first drain D1, the second source S2, and the second drain D2. At this point, the active component substrate 10 is substantially complete.

[0109] Figure 5 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 5 The embodiments follow Figures 1A to 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0110] Figure 5 Active component substrate 20 and Figures 1A to 1B The main difference between the active element substrate 10 and the active element substrate 20 is that the first active element TFT1 selectively includes a transfer electrode TE.

[0111] Please refer to Figure 5The transition electrode TE is electrically connected to the first bottom gate BG1 and the first source S1. The transition electrode TE is separated from the first top gate TG1 and the second top gate TG2. For example, the transition electrode TE is connected to the first bottom gate BG1 through a contact hole V2, wherein the contact hole V2 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2. In some embodiments, the transition electrode TE, the first top gate TG1, and the second top gate TG2 belong to the same patterning layer; in other words, the transition electrode TE, the first top gate TG1, and the second top gate TG2 can be formed in the same patterning process. In addition, in this embodiment, before forming the first source S1, a contact hole V2' exposing the transition electrode TE is formed simultaneously with the formation of contact holes H1 to H4. Then, the first source S1 is formed in the contact hole V2' to connect the transition electrode TE.

[0112] Figure 6 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 6 The embodiments follow Figures 1A to 1B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0113] Figure 6 Active component substrate 30 and Figures 1A to 1B The main difference between the active element substrate 10 and the active element substrate 30 is that the first semiconductor structure SM1 and the second semiconductor structure SM2 belong to different patterning layers.

[0114] Please refer to Figure 6 The first gate dielectric layer GI1 is located on the first bottom gate BG1, the second bottom gate BG2, and the buffer layer BL. The first semiconductor structure SM1 is located on the first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1.

[0115] The second gate dielectric layer GI2 is located on the first semiconductor structure SM1 and the first gate dielectric layer GI1. The second semiconductor structure SM2 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 and the first gate dielectric layer GI1 are located between the second bottom gate BG2 and the second semiconductor structure SM2.

[0116] The third gate dielectric layer GI3 is located on the second gate dielectric layer GI2 and the second semiconductor structure SM2.

[0117] The first top gate TG1 and the second top gate TG2 are located on the third gate dielectric layer GI3. The second gate dielectric layer GI2 is located between the first top gate TG1 and the first semiconductor structure SM1. The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1, and between the second top gate TG2 and the second semiconductor structure SM2.

[0118] In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the present invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multilayer structure, while the second semiconductor structure SM2 is a single-layer structure.

[0119] exist Figure 6 In this embodiment, by increasing the thickness t1 of the first semiconductor structure SM1, the problem of low turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. Furthermore, since the thickness t2 of the second semiconductor structure SM2 is relatively small, the leakage current problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

[0120] Figures 7A to 7D yes Figure 6 A cross-sectional schematic diagram of the manufacturing method of the active element substrate 30.

[0121] Please refer to Figure 7A A first bottom gate BG1 and a second bottom gate BG2 are formed on a buffer layer BL. In some embodiments, the first bottom gate BG1 and the second bottom gate BG2 belong to the same patterning layer.

[0122] Next, a first gate dielectric layer GI1 is formed on the first bottom gate BG1 and the second bottom gate BG2. Then, a first semiconductor structure SM1' is formed on the first gate dielectric layer GI1. The first semiconductor structure SM1' overlaps the first bottom gate BG1.

[0123] Please refer to Figure 7B A second gate dielectric layer GI2 is formed on the first semiconductor structure SM1' and the first gate dielectric layer GI1. Next, a second semiconductor structure SM2' is formed on the second gate dielectric layer GI2. The second semiconductor structure SM2' overlaps the second bottom gate layer BG2.

[0124] In this embodiment, the thickness of the first semiconductor structure SM1' is greater than the thickness of the second semiconductor structure SM2'.

[0125] In this embodiment, the first semiconductor structure SM1', the second gate dielectric layer GI2, and the second semiconductor structure SM2' are formed sequentially, but the present invention is not limited thereto. In other embodiments, the second semiconductor structure SM2' is formed first, followed by the second gate dielectric layer GI2, and finally the first semiconductor structure SM1'. In other words, in other embodiments, the second gate dielectric layer GI2 is formed on the second semiconductor structure SM2', and the first semiconductor structure SM1' is formed on the second gate dielectric layer GI2.

[0126] Please refer to Figure 7C A third gate dielectric layer GI3 is formed on the second gate dielectric layer GI2 and the second semiconductor structure SM2'.

[0127] Next, a first top gate TG1 and a second top gate TG2 are formed on the second gate dielectric layer GI2. In some embodiments, the first top gate TG1 and the second top gate TG2 belong to the same patterning layer.

[0128] Using the first top gate TG1 and the second top gate TG2 as masks, a doping fabrication process P is performed to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1 and a first channel region ch1, and a second semiconductor structure SM2 including a second source region sr2, a second drain region dr2 and a second channel region ch2.

[0129] In some embodiments, before forming the first top gate TG1 and the second top gate TG2, an etching process is performed on the first gate dielectric layer GI1 and the second gate dielectric layer GI2 to form a contact hole V1 that exposes the second bottom gate BG2. Then, the second top gate TG2 is formed in the contact hole V1 to electrically connect to the second bottom gate BG2.

[0130] Please refer to Figure 7D A first interlayer dielectric layer ILD1 is formed on the first top gate TG1 and the second top gate TG2. A second interlayer dielectric layer ILD2 is formed on the first interlayer dielectric layer ILD1. Next, one or more etching processes are performed to form contact holes H1 to H4 that expose the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2. In some embodiments, a contact hole V2 exposing the first bottom gate BG1 is formed simultaneously with the formation of contact holes H1 to H4.

[0131] Finally, please return to Figure 6A first source S1, a first drain D1, a second source S2, and a second drain D2 are formed on the second interlayer dielectric layer ILD2. The first source S1, the first drain D1, the second source S2, and the second drain D2 are respectively filled into contact holes H1 to H4. In some embodiments, the first source S1 is also filled into contact hole V2 to electrically connect to the first bottom gate BG1.

[0132] Finally, a protective layer PL is selectively formed on the first source S1, the first drain D1, the second source S2, and the second drain D2. At this point, the active component substrate 30 is substantially complete.

[0133] Figure 8 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 8 The embodiments follow Figure 6 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0134] Figure 8 Active component substrate 40 and Figure 6 The main difference between the active element substrate 30 and the active element substrate 40 is that, in the active element substrate 40, the first semiconductor structure SM1 is located between the second gate dielectric layer GI2 and the third gate dielectric layer GI3, and the second semiconductor structure SM2 is located between the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

[0135] Please refer to Figure 8 The first gate dielectric layer GI1 is located between the first bottom gate BG1 and the first semiconductor structure SM1, and between the second bottom gate BG2 and the second semiconductor structure SM2.

[0136] The second gate dielectric layer GI2 is located between the first bottom gate BG1 and the first semiconductor structure SM1, and between the second top gate TG1 and the second semiconductor structure SM2.

[0137] The third gate dielectric layer GI3 is located between the first top gate TG1 and the first semiconductor structure SM1, and between the second top gate TG2 and the second semiconductor structure SM2.

[0138] In this embodiment, both the first semiconductor structure SM1 and the second semiconductor structure SM2 are single-layer structures, but the present invention is not limited thereto. In other embodiments, the first semiconductor structure SM1 is a multilayer structure, while the second semiconductor structure SM2 is a single-layer structure.

[0139] exist Figure 8In this embodiment, by increasing the thickness t1 of the first semiconductor structure SM1, the problem of low turn-on current of the first active element TFT1 (Source-Sync thin film transistor) can be improved. Furthermore, since the thickness t2 of the second semiconductor structure SM2 is relatively small, the leakage current problem of the second active element TFT2 (TG-Sync thin film transistor) can be improved.

[0140] Figure 9 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention. Figure 10 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0141] In this embodiment, the active element substrate includes a pixel circuit PX, which includes a first active element TFT1, a second active element TFT2, a third active element TFT3, a light-emitting diode (LED), and a capacitor C. The structures of the first active element TFT1 and the second active element TFT2 can be referred to... Figure 1A , Figure 1B And related content, which will not be elaborated here.

[0142] Please refer to Figure 1B and Figure 9 The third active element TFT3 has a structure similar to that of the second active element TFT2. The third active element TFT3 is located on the substrate SB and includes a third bottom gate BG3, a third semiconductor structure SM3, a third top gate TG3, a third source S3, and a third drain D3.

[0143] The third bottom gate BG3 is located on the buffer layer BL. In some embodiments, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 comprise the same or different materials. In some embodiments, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 belong to the same patterning layer. In other words, the first bottom gate BG1, the second bottom gate BG2, and the third bottom gate BG3 are formed simultaneously.

[0144] The first gate dielectric layer GI1 is located on the third bottom gate BG3. In this embodiment, the first gate dielectric layer GI1 contacts the upper surface of the third bottom gate BG3.

[0145] A third semiconductor structure SM3 is located on a first gate dielectric layer GI1. The first gate dielectric layer GI1 is located between a third bottom gate BG3 and the third semiconductor structure SM3. In some embodiments, the third semiconductor structure SM3 includes a third source region sr3, a third drain region dr3, and a third channel region ch3 located between the third source region sr3 and the third drain region dr3. The third source region sr3 and the third drain region dr3 are doped (e.g., hydrogen doped) to have a resistivity lower than that of the third channel region ch3.

[0146] In some embodiments, the third semiconductor structure SM3 and the second semiconductor structure SM2 belong to the same patterning layer. In other words, the third semiconductor structure SM3 and the second semiconductor structure SM2 are formed simultaneously. In some embodiments, the thickness t3 of the third semiconductor structure SM3 is the same as the thickness t2 of the second semiconductor structure SM2, and the third semiconductor structure SM3 and the second semiconductor structure SM2 comprise the same material.

[0147] The second gate dielectric layer GI2 is located on the third semiconductor structure SM3. The third semiconductor structure SM3 is sandwiched between the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

[0148] The third top gate TG3 is located on the second gate dielectric layer GI2. The second gate dielectric layer GI2 is located between the third top gate TG3 and the third semiconductor structure SM3. The third semiconductor structure SM3 is located between the third bottom gate BG3 and the third top gate TG3. In some embodiments, the first top gate TG1, the second top gate TG2, and the third top gate TG3 comprise the same or different materials. In some embodiments, the first top gate TG1, the second top gate TG2, and the third top gate TG3 belong to the same patterning layer. In other words, the first top gate TG1, the second top gate TG2, and the third top gate TG3 are formed simultaneously.

[0149] In this embodiment, the third active element TFT3 is a dual-gate thin-film transistor (TG-sync thin-film transistor) in which the third bottom gate BG3 is electrically connected to the third top gate TG3. For example, the third top gate TG3 is connected to the third bottom gate BG3 through a contact hole V3, wherein the contact hole V3 passes through the first gate dielectric layer GI1 and the second gate dielectric layer GI2.

[0150] The first interlayer dielectric layer ILD1 is located on the third top gate TG3. The second interlayer dielectric layer ILD2 is located on the first interlayer dielectric layer ILD1.

[0151] The third source S3 and the third drain D3 are located on the second interlayer dielectric layer ILD2. The third source S3 and the third drain D3 are electrically connected to the third source region sr3 and the third drain region dr3 of the third semiconductor structure SM3 through contact holes H5 and H6, respectively, wherein contact holes H5 and H6 pass through the second gate dielectric layer GI2, the first interlayer dielectric layer ILD1, and the second interlayer dielectric layer ILD2. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 are made of the same or different materials. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 belong to the same patterned layer. In other words, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 are formed simultaneously.

[0152] Please also refer to Figure 1B , Figure 9 as well as Figure 10 In the pixel circuit PX, the first drain D1 of the first active element TFT1 is electrically connected to the voltage V. DD The first source S1 is electrically connected to one end of the light-emitting diode (LED), one end of the capacitor C, and the third drain D3 of the third active element TFT3; the first top gate TG1 is electrically connected to the other end of the capacitor C and the second source S2 of the second active element TFT2. The other end of the LED is electrically connected to the voltage V. SS Voltage V DD Higher than V SS .

[0153] The second drain D2 of the second active element TFT2 is electrically connected to the data line voltage V. DL The second top gate TG2 is electrically connected to the first scan line voltage V. SCAN1 .

[0154] The third source S3 of the third active element TFT3 is electrically connected to the common line voltage V. COM The third top gate TG3 is electrically connected to the second scan line voltage V. SCAN2 .

[0155] In this embodiment, the second active element TFT2 serves as a switching thin-film transistor, and the first active element TFT1 serves as a driving thin-film transistor. The second active element TFT2 is used to control the switching of the first top gate TG1 of the first active element TFT1. The third active element TFT3 serves as a sensing thin-film transistor, used to transmit information about the driving current through the first active element TFT1 to an external chip.

[0156] In summary, the present invention can improve the reliability of the first active element during long-term operation, while increasing the turn-on current of the second and third active elements.

Claims

1. An active element substrate, comprising: substrate; A buffer layer is located on the substrate; A first active element, located above the buffer layer, includes: A first bottom gate, a first semiconductor structure, and a first top gate, wherein the first semiconductor structure is located between the first bottom gate and the first top gate, wherein the first semiconductor structure is a multilayer structure and includes a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer comprising different materials; and A first source and a first drain are electrically connected to the first semiconductor structure, and the first source is electrically connected to the first bottom gate; and A second active element is located above the buffer layer and electrically connected to the first active element, wherein the second active element includes: The second bottom gate, the second semiconductor structure, and the second top gate are provided, wherein the second semiconductor structure is located between the second bottom gate and the second top gate, and the thickness of the second semiconductor structure is less than the thickness of the first semiconductor structure. The second bottom gate is electrically connected to the second top gate through a contact hole. The second semiconductor layer and the second semiconductor structure belong to the same patterning layer. The materials of the first semiconductor layer, the second semiconductor layer, and the second semiconductor structure include indium gallium tin zinc oxide (IGTZO) or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or lanthanide rare earth doped metal oxides. The second source and the second drain are electrically connected to the second semiconductor structure; The third active element, located above the buffer layer, includes: A third bottom gate, a third semiconductor structure, and a third top gate, wherein the third semiconductor structure is located between the third bottom gate and the third top gate, and the third bottom gate is electrically connected to the third top gate, wherein the third semiconductor structure and the second semiconductor structure have the same thickness and material, the first bottom gate, the second bottom gate, and the third bottom gate belong to the same patterned layer, and the first top gate, the second top gate, and the third top gate belong to the same patterned layer; and The third source and the third drain are electrically connected to the third semiconductor structure, wherein the second source is electrically connected to the first top gate and the first source is electrically connected to the third drain; A first gate dielectric layer is located between the first bottom gate and the first semiconductor structure, between the second bottom gate and the second semiconductor structure, and between the third bottom gate and the third semiconductor structure, wherein the first gate dielectric layer contacts the lower surface of the first semiconductor layer, the lower surface of the second semiconductor structure, and the lower surface of the third semiconductor structure; and A second gate dielectric layer is located between the first top gate and the first semiconductor structure, between the second top gate and the second semiconductor structure, and between the third top gate and the third semiconductor structure. The second gate dielectric layer contacts the upper surface of the second semiconductor layer, the upper surface of the second semiconductor structure, and the upper surface of the third semiconductor structure. The contact hole passes through the first gate dielectric layer and the second gate dielectric layer. The first drain of the first active element is electrically connected to a first voltage, and the first source is electrically connected to one end of the light-emitting diode, one end of the capacitor, and the third drain of the third active element; the first top gate is electrically connected to the other end of the capacitor and the second source of the second active element, and the other end of the light-emitting diode is electrically connected to a second voltage, wherein the first voltage is higher than the second voltage; the second drain of the second active element is electrically connected to the data line voltage, and the second top gate is electrically connected to the first scan line voltage; the third source of the third active element is electrically connected to the common line voltage, and the third top gate is electrically connected to the second scan line voltage.

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