A digital filtering system for multi-domain analysis of a vector network analyzer

Abstract

The application provides a digital filtering system for multi-domain analysis of a vector network analyzer, and the specific process of the digital filtering system for processing signals is as follows: multiple analog intermediate frequency input signals enter an analog-digital conversion control and holding unit through a signal conditioning circuit, so as to convert the multiple analog intermediate frequency signals into multiple digital intermediate frequency signals; the multiple digital intermediate frequency signals enter a multi-channel data synchronization unit; under a non-modulation measurement domain, the signals enter a continuous filtering unit, under a synchronous modulation domain, the signals enter a synchronous modulation filtering unit, and when in a data storage mode, a spectrum mode or other special modes, the signals enter an ADC data storage unit; a filtering coefficient generation and control unit generates different FIR filtering coefficients according to input data modes, and sends the filtering coefficients into a multi-channel parallel FIR filtering unit. The technical scheme of the application overcomes the problem that the filtering system in the prior art cannot meet the digital filtering requirements of the vector network analyzer under different measurement modes.

Description

A digital filtering system for multi-domain analysis in a vector network analyzer Technical Field

[0001] This invention relates to the field of digital filtering technology for vector network analyzers in multi-domain analysis, and specifically to a digital filtering system for multi-domain analysis in vector network analyzers. Background Technology

[0002] Filtering is a fundamental and crucial technique in signal processing, serving as a means to accurately acquire information about the system's measured signal. With the rapid development of FPGA and DSP chips, digital filtering technology based on programmable hardware has found widespread application in fields such as communications, antennas, radar, satellite navigation, instrumentation, and biomedicine. In test instruments such as vector network analyzers, digital filters often employ FIR filters to process the system's intermediate frequency (IF) signal. Different measuring instruments have different IF bandwidths for their filters, but these are often limited to a few fixed bandwidths. Some systems use special algorithms to modulate the filter coefficients, but this results in high filter orders, and each change in IF bandwidth requires rewriting the filter coefficients, increasing data processing time.

[0003] There are two existing implementation modes for network instrument digital filtering systems that provide complex multi-domain analysis: one is to achieve better out-of-band rejection by reducing the intermediate frequency bandwidth; the other is to achieve a larger passband and a smaller stopband rejection through complex algorithms. The first method reduces the testing speed due to the small intermediate frequency bandwidth; the second method's complex algorithm implementation lacks universality, and may result in the inability to obtain calculation results or aliasing in the filter stopband, and the resulting cascaded filter may have high far-end out-of-band rejection.

[0004] Therefore, there is a need for a digital filtering system for a network analyzer that can meet the digital filtering requirements of different measurement modes of a vector network analyzer and achieve good test performance. Summary of the Invention

[0005] The main objective of this invention is to provide a digital filtering system for multi-domain analysis in a vector network analyzer, in order to solve the problem that existing filtering systems cannot meet the digital filtering requirements of different measurement modes in a vector network analyzer.

[0006] To achieve the above objectives, this invention provides a digital filtering system for multi-domain analysis in a vector network analyzer. The specific process of signal processing by the digital filtering system is as follows:

[0007] Multiple analog intermediate frequency input signals enter the analog-to-digital conversion control and hold unit through the signal conditioning circuit, converting the multi-channel analog intermediate frequency signals into multi-channel digital intermediate frequency signals;

[0008] The multi-channel digital intermediate frequency signal enters the multi-channel data synchronization unit. This unit realizes the synchronous reading and writing of data between different channels through clock synchronization, common time base and storage buffering, so as to ensure that the phase relationship between the multi-channel digital intermediate frequency signals remains unchanged.

[0009] In the unmodulated measurement domain, it enters the continuous filtering unit; in the synchronous modulation domain, it enters the synchronous modulation filtering unit; and in data storage mode, spectrum mode, or other special modes, it enters the ADC data storage unit.

[0010] The ADC data from the continuous filtering unit, after being buffered and shaped, is digitally down-converted with the digital intermediate frequency signal generated by the FPGA's NCO to obtain I-channel and Q-channel data. The data then enters the multi-channel parallel FIR filtering unit for filtering and is finally written into the multi-channel filtered data storage unit for further processing.

[0011] When the gate pulse is valid, the synchronous modulation filter unit starts processing the ADC data. After passing through the delay unit with a settable delay, it is mixed with the NCO to obtain I-channel and Q-channel data. Then, it enters the multi-channel parallel FIR filter unit for filtering. The filtering result is written to the multi-channel filter data storage unit for further processing.

[0012] In data storage mode, the raw ADC data is written into the multi-channel data integration and storage unit through a delay module according to the trigger command of the trigger control unit, i.e., the trigger condition and the number of storage units.

[0013] The filter coefficient generation and control unit generates different FIR filter coefficients based on the input data mode, i.e., continuous filtering mode or synchronous modulation filtering mode, and sends the filter coefficients to the multi-channel parallel FIR filtering unit.

[0014] Furthermore, the filter coefficient generation and control unit includes a first-stage filter and a second-stage filter cascaded therewith.

[0015] Furthermore, in continuous or synchronous modulation filtering mode, the specific process by which the filter coefficient generation and control unit generates different FIR filter coefficients based on the input data pattern is as follows:

[0016] S1, reads the current intermediate frequency bandwidth of the vector network analyzer;

[0017] S2, look up the FIR filter order in the table or dynamically generate the filter order according to the adaptive intermediate frequency filter design algorithm;

[0018] S3, determine if the filter order is less than 1024;

[0019] S4, if so, look up the filter coefficient address in the table according to the intermediate frequency bandwidth index, and then execute step S7;

[0020] S5, if not, look up the table to obtain the coefficients of the first-stage filter and the order of the second-stage filter;

[0021] S6, using the order of the second-level filter as the loop count, repeatedly reads the coefficients of the first-level filter;

[0022] S7 reads the filter coefficients sequentially and sends them to the multi-channel parallel FIR filter unit.

[0023] Furthermore, in synchronous modulation mode, the adaptive intermediate frequency filter design algorithm is used to generate the filter order, and then the filter coefficients are obtained. The specific steps are as follows:

[0024] S2.1, Calculate the initial filter order n according to formula (1) and the intermediate frequency bandwidth IFBW set by the user, where C is a constant;

[0025]

[0026] S2.2, calculate the initial filter order m according to formula (2) and modulation period Tw;

[0027]

[0028] S2.3. Based on the filter window type selected by the user, determine the formula for the approximate width of the main lobe. When the filter window type is a rectangular window, the formula for the approximate width of the main lobe is 4π(M+1). Substitute m and n into the filter order M, and take the value of the main lobe width that is closer to IFBW as the value of M for the next calculation.

[0029] S2.4, adjust the value of M according to formula (3) so that the calculated value of M is closest to the zero point;

[0030]

[0031] Furthermore, when a window type other than a rectangular window is selected, the filtering system will perform filtering in two stages. At this time, the value of M is decomposed into T1 and T2, such that M = T1 * T2, where T1 and T2 are prime numbers, and T1 is greater than 128 and less than 1024. T1 is the first-stage filtering order, and T2 is the second-stage filtering order.

[0032] Furthermore, in data storage mode, the digital filtering system splices the multi-channel digital intermediate frequency signals according to the signal input order, and then reads them into the host computer through the high-speed PCIe interface. The ADC data storage unit is controlled by the trigger control unit to store data, and the trigger control unit generates control timing according to the detection mode.

[0033] If the detection mode is external synchronization mode, the external input signal is detected using the sampling clock, and data storage begins when the input signal is valid;

[0034] If the detection mode is level mode, data storage will begin when the level of the ADC data storage unit meets the condition.

[0035] If the detection mode is a delay mode, the user starts the process and starts storing data after a specified delay.

[0036] The present invention has the following beneficial effects:

[0037] 1. The digital filtering system provided by this invention takes into account the filtering requirements of vector network analyzers in multi-domain modes. It includes a standard filtering mode with fixed intermediate frequency bandwidth, a dynamic filter generation algorithm with adaptive intermediate frequency bandwidth, and a custom filtering mode that generates filter coefficients based on a specified window function. The flexible filtering modes can meet the digital filtering requirements of vector network analyzers in different measurement modes and achieve good test performance requirements.

[0038] 2. The digital filtering system for multi-domain analysis of network instruments provided by this invention provides a filtering system that can be used for continuous wave testing, pulse testing, intermodulation distortion testing and FFT testing, and provides basic signal analysis and processing support for frequency domain analysis, time domain analysis, pulse modulation domain analysis and digital domain analysis of network instruments;

[0039] 3. In synchronous modulation filtering mode, the method of obtaining filter coefficients by using adaptive intermediate frequency filter design algorithm is relatively simple, the filtering time at each point is short and the resources occupied are less, which shortens the data processing time of digital filtering system;

[0040] 4. The digital filtering system provided by this invention includes an ADC data storage unit, which allows users to process the raw sampled data, facilitating application expansion.

[0041] 5. The multi-channel data synchronization unit ensures that the data obtained by users is relatively stable. Attached Figure Description

[0042] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0043] Figure 1 shows a signal processing flowchart of a digital filtering system for multi-domain analysis in a vector network analyzer according to the present invention.

[0044] Figure 2 shows a flowchart of the filtering mode in the filter coefficient transmission control unit of Figure 1. Detailed Implementation

[0045] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Figure 1 shows a digital filtering system for multi-domain analysis in a vector network analyzer. The specific process of the digital filtering system for signal processing is as follows:

[0047] Multiple analog intermediate frequency input signals enter the analog-to-digital conversion control and hold unit through the signal conditioning circuit, converting the multi-channel analog intermediate frequency signals into multi-channel digital intermediate frequency signals;

[0048] The multi-channel digital intermediate frequency signal enters the multi-channel data synchronization unit. This unit realizes the synchronous reading and writing of data between different channels through clock synchronization, common time base and storage buffering, so as to ensure that the phase relationship between the multi-channel digital intermediate frequency signals remains unchanged.

[0049] In the unmodulated measurement domain, it enters the continuous filtering unit; in the synchronous modulation domain, it enters the synchronous modulation filtering unit; and in data storage mode, spectrum mode, or other special modes, it enters the ADC data storage unit.

[0050] The ADC data from the continuous filtering unit, after being buffered and shaped, is digitally down-converted with the digital intermediate frequency signal generated by the FPGA's NCO to obtain I-channel and Q-channel data. The data then enters the multi-channel parallel FIR filtering unit for filtering and is finally written into the multi-channel filtered data storage unit for further processing.

[0051] When the gate pulse is valid, the synchronous modulation filter unit starts processing the ADC data. After passing through the delay unit with a settable delay, it is mixed with the NCO to obtain I-channel and Q-channel data. Then, it enters the multi-channel parallel FIR filter unit for filtering. The filtering result is written to the multi-channel filter data storage unit for further processing.

[0052] The multi-channel filtered data storage unit adopts a first-in-first-out queue. This queue does not require a large-capacity sampling memory because the amount of data after filtering is small. If a high-speed data interface is used, the filtering processing time can meet the data reading time.

[0053] In data storage mode, the raw ADC data is written to the multi-channel data integration and storage unit through the delay module according to the trigger command of the trigger control unit, i.e. the trigger condition and the number of storage units. This storage unit uses a large-capacity high-speed memory to implement a dual-port read and write mode to ensure that the ADC data can be read correctly while writing it. The capacity of the large-capacity memory needs to be at least greater than the capacity of the ADC sampling rate multiplied by the number of channels.

[0054] The filter coefficient generation and control unit generates different FIR filter coefficients based on the input data mode, i.e., continuous filtering mode or synchronous modulation filtering mode, and sends the filter coefficients to the multi-channel parallel FIR filtering unit.

[0055] The multi-channel parallel FIR filter unit is used to process the filtering process under different measurement modes. This invention adopts the FIR filtering mode, which can provide a linear phase filter passband and is relatively simple to implement and easy to implement in FPGA programming. Through the FIR mode, filters with different bandwidths, shapes and characteristics can be realized by simply changing the filter coefficients, which can meet the needs of multi-domain testing of network instruments.

[0056] Specifically, the filter coefficient generation and control unit includes a first-stage filter and a second-stage filter cascaded therewith.

[0057] Specifically, as shown in Figure 2, in continuous or synchronous modulation filtering mode, the specific process of the filter coefficient generation and control unit generating different FIR filter coefficients according to the input data pattern is as follows:

[0058] S1, reads the current intermediate frequency bandwidth of the vector network analyzer;

[0059] S2, look up the FIR filter order in the table or dynamically generate the filter order according to the adaptive intermediate frequency filter design algorithm;

[0060] S3, determine if the filter order is less than 1024;

[0061] S4, if so, look up the filter coefficient address in the table according to the intermediate frequency bandwidth index, and then execute step S7;

[0062] S5, if not, look up the table to obtain the coefficients of the first-stage filter and the order of the second-stage filter;

[0063] S6, using the order of the second-level filter as the loop count, repeatedly reads the coefficients of the first-level filter;

[0064] S7 reads the filter coefficients sequentially and sends them to the multi-channel parallel FIR filter unit.

[0065] In continuous filtering mode, the system retrieves filter coefficients sequentially from a pre-stored filter coefficient table based on the intermediate frequency bandwidth and coefficient address, and then sends them to the multi-channel parallel FIR filter unit. The filter coefficients are determined using Matlab's window function FIR design method. For large bandwidths, fewer filter coefficients are needed, and the coefficients are determined based on the 3dB intermediate frequency bandwidth, intermediate frequency, and out-of-band rejection frequency. Filter coefficients of different bandwidths are stored in descending order of bandwidth. During retrieval, the starting address of the filter coefficients for each bandwidth is obtained, and coefficients are read sequentially from that address. For small bandwidths, the filter coefficients are typically large. In this case, the filtering stage is divided into two stages. The first-stage filter has an order of N, and it is necessary to ensure that Fs / N*m = intermediate frequency, where m is an integer satisfying the condition. The second-stage filter is cascaded with the first-stage filter to achieve a small intermediate frequency bandwidth. The multi-channel filter data storage unit adopts a first-in, first-out queue mode. When a storage unit has data, it notifies the subsequent processing unit to read the data for the next step of processing.

[0066] Specifically, in synchronous modulation mode, the adaptive intermediate frequency filter design algorithm is used to generate the filter order, and then the filter coefficients are obtained. The specific steps are as follows:

[0067] S2.1, Calculate the initial filter order n according to formula (1) and the intermediate frequency bandwidth IFBW set by the user, where C is a constant;

[0068]

[0069] S2.2, calculate the initial filter order m according to formula (2) and modulation period Tw;

[0070]

[0071] S2.3. Based on the filter window type selected by the user, determine the formula for the approximate width of the main lobe. When the filter window type is a rectangular window, the formula for the approximate width of the main lobe is 4π(M+1). Substitute m and n into the filter order M, and take the value of the main lobe width that is closer to IFBW as the value of M for the next calculation.

[0072] S2.4, adjust the value of M according to formula (3) so that the calculated value of M is closest to the zero point;

[0073]

[0074] By using the M value calculated through the above steps for filtering, a high level of modulation signal spurious suppression can be achieved with the fewest filtering orders, and filtering requirements under different modulation conditions can be met with less filtering time.

[0075] Specifically, when a window type other than a rectangular window is selected, the filtering system will perform filtering in two stages. At this time, the value of M is decomposed into T1 and T2, such that M = T1 * T2, where T1 and T2 are prime numbers, and T1 is greater than 128 and less than 1024. T1 is the first-stage filtering order, and T2 is the second-stage filtering order.

[0076] When the system is in synchronous modulation mode, an adaptive intermediate frequency filter design algorithm is used to dynamically generate filter coefficients and filter order. This algorithm dynamically generates filter coefficients based on the window function characteristics shown in Table 1, and selectively filters the measured signal to obtain the measured signal.

[0077] The main parameters of the filter window type can be found in Table 1, which lists the maximum sidelobe amplitude, main lobe approximation width, maximum approximation error, and transition band width of the equivalent Kaiser window for different window functions.

[0078] Table 1. Approximate width of the main lobe for different window types.

[0079]

[0080] To fully utilize the limited storage space of the FPGA, the digital filtering system of the vector network analyzer, based on the symmetrical characteristics of the FIR filter coefficients, only stores half of the filter coefficients N. During filtering, it retrieves N from point 1 and then returns from N to 1. To achieve higher filtering accuracy and reduce system processing pressure, the FIR filtering of the digital filtering system of the vector network analyzer is also divided into two parts. The first part completes the first half of the filtering, and the second part completes the second half of the filtering. The two parts are then summed, and the sum is sent to the DSP for normalization and other processing, achieving a smaller filtering bandwidth with less resource consumption.

[0081] Specifically, in data storage mode, the digital filtering system splices the multi-channel digital intermediate frequency signals in the order of signal input, and then reads them into the host computer through the high-speed PCIe interface. The ADC data storage unit is controlled by the trigger control unit to store data, and the trigger control unit generates control timing according to the detection mode.

[0082] If the detection mode is external synchronization mode, the external input signal is detected using the sampling clock, and data storage begins when the input signal is valid;

[0083] If the detection mode is level mode, data storage will begin when the level of the ADC data storage unit meets the condition.

[0084] If the detection mode is a delay mode, the user starts the process and starts storing data after a specified delay.

[0085] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A digital filtering system for multi-domain analysis in a vector network analyzer, characterized in that, The specific process of signal processing in a digital filtering system is as follows: Multiple analog intermediate frequency input signals enter the analog-to-digital conversion control and hold unit through the signal conditioning circuit, which converts the multi-channel analog intermediate frequency signals into multi-channel digital intermediate frequency signals; the multi-channel digital intermediate frequency signals enter the multi-channel data synchronization unit, which realizes the synchronous reading and writing of data between different channels through clock synchronization, common time base and storage buffer, so as to ensure that the phase relationship between the multi-channel digital intermediate frequency signals remains unchanged; In the unmodulated measurement domain, it enters the continuous filtering unit; in the synchronous modulation domain, it enters the synchronous modulation filtering unit; and in data storage mode, spectrum mode, or other special modes, it enters the ADC data storage unit. The ADC data from the continuous filtering unit, after buffering and data shaping, is digitally down-converted with the digital intermediate frequency signal generated by the FPGA's NCO to obtain I-channel and Q-channel data. This data then enters the multi-channel parallel FIR filtering unit for filtering, and finally, the data is written to the multi-channel filtered data storage unit for further processing. When the gate pulse is valid, the synchronous modulation filtering unit begins processing the ADC data. After passing through a configurable delay unit, the data is mixed with the NCO to obtain I-channel and Q-channel data, which then enters the multi-channel parallel FIR filtering unit for filtering. The filtering result is written to the multi-channel filtered data storage unit for further processing. In data storage mode, the original ADC data, based on the trigger command from the trigger control unit (i.e., the trigger condition and the number of storage locations), is written to the multi-channel data integration and storage unit via a delay module. The filter coefficient generation and control unit generates different FIR filter coefficients based on the input data mode, i.e., continuous filtering mode or synchronous modulation filtering mode, and sends the filter coefficients to the multi-channel parallel FIR filtering unit.

2. The digital filtering system for multi-domain analysis in a vector network analyzer according to claim 1, characterized in that, The filter coefficient generation and control unit includes a primary filter and a secondary filter cascaded thereon.

3. A digital filtering system for multi-domain analysis in a vector network analyzer according to claim 2, characterized in that, In continuous or synchronous modulation filtering mode, the specific process of the filter coefficient generation and control unit generating different FIR filter coefficients according to the input data pattern is as follows: S1, read the current intermediate frequency bandwidth of the vector network analyzer; S2, look up the table to obtain the FIR filter order or dynamically generate the filter order according to the adaptive intermediate frequency filter design algorithm; S3, determine whether the filter order is less than 1024; S4, if so, look up the table according to the intermediate frequency bandwidth index to obtain the filter coefficient address, and then execute step S7; S5, if not, look up the table to obtain the first-stage filter coefficients and the second-stage filter order; S6, read the first-stage filter coefficients cyclically with the second-stage filter order as the loop count; S7, read the filter coefficients sequentially and send them to the multi-channel parallel FIR filtering unit.

4. A digital filtering system for multi-domain analysis in a vector network analyzer according to claim 3, characterized in that, In synchronous modulation mode, the filter order is generated by the adaptive intermediate frequency filter design algorithm, and then the filter coefficients are obtained. The specific steps are as follows: S2.1, calculate the initial filter order n according to formula (1) and the user-set intermediate frequency bandwidth IFBW, where C is a constant; S2.2, calculate the initial filter order m according to formula (2) and modulation period Tw; S2.

3. Based on the filter window type selected by the user, determine the formula for the approximate width of the main lobe. When the filter window type is a rectangular window, the formula for the approximate width of the main lobe is 4π(M+1). Substitute m and n into the filter order M, and take the value of the main lobe width that is closer to IFBW as the value of M for the next calculation. S2.4, adjust the value of M according to formula (3) so that the calculated value of M is closest to the zero point.

5. A digital filtering system for multi-domain analysis in a vector network analyzer according to claim 4, characterized in that, When a window type other than a rectangular window is selected, the filtering system will perform filtering in two stages. At this time, the value of M is decomposed into T1 and T2, such that M = T1 * T2, where T1 and T2 are prime numbers, and T1 is greater than 128 and less than 1024. T1 is the first-stage filtering order, and T2 is the second-stage filtering order.

6. A digital filtering system for multi-domain analysis in a vector network analyzer according to claim 1, characterized in that, In data storage mode, the digital filtering system splices the multi-channel digital intermediate frequency signals in the order of signal input, and then reads them into the host computer through the high-speed PCIe interface. The ADC data storage unit is controlled by the trigger control unit to store data. The trigger control unit generates control timing according to the detection mode. If the detection mode is external synchronization mode, the external input signal is detected by the sampling clock. When the input signal is valid, data storage begins. If the detection mode is level mode, data storage will begin when the level of the ADC data storage unit meets the condition. If the detection mode is a delay mode, the user starts the process and starts storing data after a specified delay.

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