A memory operation method, a memory and a storage system
By setting up multiplexer switch units and cache units in the peripheral circuit of the memory, the problem that the memory cannot complete the reading within a specified time when the data path width is small is solved, thus realizing efficient data storage and reading.
CN116189729BActive Publication Date: 2026-06-16YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-09-05
- Publication Date
- 2026-06-16
AI Technical Summary
⚠Technical Problem
When the data path width of an existing memory is smaller than the actual width of the data to be read, it cannot complete the read operation within the specified delay, resulting in incomplete data reading.
⚗Method used
Multiplexer switch groups and cache groups are set in the peripheral circuit of the memory. The read data is stored in a specific format according to different working modes to meet the latency requirements of different read commands.
🎯Benefits of technology
It enables data reading to be completed within a specified time even when the data path width is small, thus meeting the delay requirements of the circuit design.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN116189729B_ABST
Abstract
Embodiments of the present application provide a memory operation method, a memory and a storage system. The memory includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes a plurality of multiplexing switch unit groups and a plurality of cache unit groups. The plurality of multiplexing switch unit groups are electrically connected to the plurality of cache unit groups. The plurality of multiplexing switch unit groups are configured to start a setting mode in response to a received first enable signal. In the setting mode, the plurality of multiplexing switch unit groups are configured to store data in a first format in the plurality of cache unit groups according to a second format, wherein the data in the first format is obtained from the memory array.
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