Inverter structure and method for its failure response

Abstract

The application provides an inverter structure and a method for responding to faults thereof, and provides a main control chip of an MCU, peripherals, a driving chip for controlling multiple groups of switching tubes, and a hardware fault management main module; wherein the hardware fault management main module is integrated in a multi-core CPU in the main control chip; whether a hardware fault occurs is judged by the MCU peripherals, and if so, fault information is sent to the multi-core CPU; after receiving the fault information, the multi-core CPU sends a response signal to the driving chip, so that the driving chip controls at least one group of switching tubes to enter an open circuit or short circuit state. By integrating the logic of hardware CPLD fault influence and PWM output protection into the MCU, the CPLD chip and related peripheral circuits can be directly omitted, thereby reducing the cost of products and improving the production rhythm of products.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to an inverter structure and a method for fault response thereof. Background Technology

[0002] With the rapid development of the new energy vehicle industry, more and more pure electric and plug-in hybrid vehicles are entering consumers' lives, and they widely adopt the following... Figure 1 The inverter topology shown in the diagram transfers energy from the high-voltage battery to the IGBT (Insulated Gate Bipolar Transistor) module or the SiC (Silicon Carbide) device module through a voltage-regulating filter capacitor. After switching modulation, the energy drives the motor to output torque.

[0003] However, inverters may experience various hardware failures during power output, leading to torque runaway or high-voltage risks that threaten personal safety. Major hardware failures include hardware bus overvoltage, phase current hardware overcurrent, IGBT or SiC switch shoot-through, and IGBT gate drive power supply failures. When one or more hardware failures occur, power output needs to be stopped, and the IGBT or SiC switch response needs to be adjusted to a specific safety state. Common safety states include lower three-transistor short circuit (hereinafter referred to as lower ASC), upper three-transistor short circuit (hereinafter referred to as upper ASC), and both upper and lower transistors open circuit (hereinafter referred to as FW). ASC actively turns on the three switches of the upper or lower bridge to provide the motor phase current loop; FW turns all six switches off, cutting off the current loop flowing through the IGBT or SiC switch. FW is a commonly used safety state, but if the motor speed is high at this time, the motor back EMF voltage may reverse charge through the diodes, increasing the bus voltage. If the bus voltage is too high, it can cause undesirable high voltage, threatening high-voltage safety. Therefore, a hardware overvoltage fault should be responded to as a short circuit in the lower three transistors. If a hardware overvoltage and the low-side IGBT or (SiC) drive power supply occur simultaneously, it should be responded to as a short circuit in the upper three transistors.

[0004] Because faults such as overvoltage on the hardware bus or damage to the drive circuit hardware place high demands on the response time to safe conditions, most automotive inverters on the market currently use programmable logic devices (such as Complex Programmable Logic Devices, or CPLDs) for implementation. Figure 2The structure shown illustrates that the main control chip is responsible for the motor control algorithm and provides six switching signals to a programmable logic chip (such as a Complex Programmable Logic Device, or CPLD) responsible for hardware fault response. The programmable logic chip is responsible for transmitting the six switching signals to the driver chip, while the hardware fault response chip is responsible for hardware fault response. If a hardware fault is detected, it will no longer directly output the six switching signals from the main control chip, but will directly output the corresponding safety states such as short circuit of the lower / upper transistors (ASC) or full open circuit (FW).

[0005] However, programmable logic devices (PLDs) are expensive and require external circuitry, occupying a significant amount of circuit board space. This approach also necessitates maintaining additional CPLD hardware programs, requiring consideration of version upgrades and compatibility with MCU programs. With the increasing prevalence of remote software upgrades in the automotive industry, this will create some inconvenience. Furthermore, specific workstations are required for program updates during production, impacting the production cycle.

[0006] With the increasing computing power of MCUs, integrating fault response logic into the MCU brings many conveniences and reduces product costs. However, response speed and the reliability of fault signal capture present significant challenges. Furthermore, the MCU's existing status management and fault diagnosis modules also need to acquire information about past faults and implement corresponding fault recovery mechanisms.

[0007] To address the aforementioned issues, a novel inverter structure and its fault response method are required. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an inverter structure and a method for responding to its faults, in order to solve the problems of high cost of programmable logic devices, the need for external circuitry, large circuit board area, maintenance of additional CPLD hardware programs, the need to consider version upgrades and compatibility with MCU programs, which will bring certain inconveniences with the promotion of remote software upgrades in automobiles; the need for specific workstations to refresh programs during production, affecting the production cycle; and the need to ensure the MCU's fault response speed and the reliability of fault signal capture.

[0009] To achieve the above and other related objectives, the present invention provides a hardware fault response method, comprising:

[0010] The MCU's main control chip and peripherals, driver chips for controlling multiple sets of switching transistors, and hardware fault management main module;

[0011] in,

[0012] The hardware fault management main module is integrated into the multi-core CPU of the main control chip;

[0013] The MCU peripheral is used to determine whether a hardware failure has occurred. If so, the failure information is sent to the multi-core CPU.

[0014] The multi-core CPU receives the fault information and sends a response signal to the driver chip, causing the driver chip to control at least one group of the switching transistors to enter an open-circuit or short-circuit state.

[0015] Preferably, the switching transistor is at least one of IGBT and SiC switching transistor.

[0016] Preferably, the MCU peripheral includes a DC I / O module, a peripheral capture module, and a peripheral transport module. The DC I / O module is used to receive digital signals from an external MCU circuit. The peripheral information capture module is used to detect the digital signals to obtain the fault information. The peripheral transport module is used to receive the fault information.

[0017] Preferably, the hardware fault management main module includes a fault latch module, a fault response module, a shared memory module, and a fault management module.

[0018] Preferably, the method for the MCU peripheral to continuously acquire hardware fault information and send the fault information to the multi-core CPU includes: the MCU peripheral includes a DC I / O module, a peripheral capture module, and a peripheral transport module; the DC I / O module is used to receive digital signals from the circuits in the MCU; the peripheral capture module detects the digital signals to determine whether a fault has occurred; if so, the fault information is sent to the peripheral transport module; and the peripheral transport module stores the fault information in a specified memory address.

[0019] Preferably, the fault latch module, fault response module, and shared memory module are all located in the secondary core of the multi-core CPU.

[0020] Preferably, the fault management module is located in the main core of the multi-core CPU.

[0021] Preferably, the fault latching module is used to obtain the fault information from the peripheral device transport module, and then store the fault information in its memory address to obtain fault latching information.

[0022] Preferably, the fault response module is used to send the response signal to the driver chip after obtaining the fault latch information.

[0023] Preferably, the response signal is a PWM wave.

[0024] Preferably, the MCU peripheral further includes a dead-time protection module, and the response signal is sent to the DC IO module after the dead-time protection module eliminates its pass-through signal.

[0025] Preferably, the shared memory module includes a fault register and a configuration register. The fault register determines the location of the fault based on the fault latch information and sets the corresponding bit. The configuration register configures a fault clearing instruction, which is used to clear the fault latch information in the fault latch or reset the bit in the fault register.

[0026] Preferably, the fault management module includes a fault diagnosis module and a fault clearing module. The fault diagnosis module periodically reads the bit in the configuration register. When a fault occurs, it counts the number of times the fault occurs and determines whether the number of times exceeds a set threshold. If so, the fault clearing module does not work. The fault diagnosis module sends a response signal to the driver chip, causing the driver chip to control at least one group of the switching transistors to enter an open circuit or short circuit state.

[0027] Preferably, the fault management module includes a fault diagnosis module and a fault clearing module. The fault diagnosis module is used to periodically read the bit in the configuration register. When a fault occurs, it counts the number of times the fault occurs and determines whether the number of times is greater than a set threshold. If not, the fault clearing module controls the configuration register to send a fault clearing instruction to reset the fault latch information and the bit in the fault register.

[0028] Preferably, the MCU peripheral is used to determine whether a hardware fault has occurred. If not, the fault clearing module controls the configuration register to send a fault clearing instruction to reset the fault latch information and the bit in the fault register.

[0029] A fault response method for an inverter structure, the fault response method being used in the aforementioned inverter structure.

[0030] As described above, the inverter structure and fault response method of the present invention have the following beneficial effects:

[0031] This invention integrates the logic for hardware CPLD failure impact and PWM output protection into the MCU, which can directly eliminate the need for CPLD chips and related peripheral circuits, thereby reducing product costs and increasing production cycle time. Attached Figure Description

[0032] Figure 1 The diagram shows a structural schematic of an automotive inverter in the prior art.

[0033] Figure 2 The diagram shown is a schematic of an MCU protection device in the prior art.

[0034] Figure 3 The diagram shown is a schematic diagram of the MCU protection device of the present invention.

[0035] Figure 4 The diagram shown is a schematic diagram of the main control chip structure of the present invention.

[0036] Figure 5 The diagram shows the hardware fault diagnosis and repair response logic of the present invention.

[0037] Figure 6 The diagram shown is a schematic diagram of the dead zone protection of the present invention.

[0038] Figure 7 The diagram shows the main core of this invention for diagnosing hardware faults.

[0039] Figure 8 The diagram shown illustrates the core fault clearing configuration of this invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figure 5 The present invention provides an inverter structure, comprising:

[0042] Please see Figure 3 and 4 It provides an MCU main control chip 1 and peripherals 11, a driver chip 2 for controlling multiple sets of switching transistors 3 (not shown in the figure), and a hardware fault management main module; among which,

[0043] The hardware fault management main module 1221 is integrated into the multi-core CPU 12 in the main control chip 1. The MCU peripheral 11 is used to obtain hardware fault information and send the fault information to the multi-core CPU 12.

[0044] The MCU peripheral is used to determine whether a hardware failure has occurred. If so, the failure information is sent to the multi-core CPU.

[0045] The multi-core CPU 12 receives fault information and sends a response signal to the driver chip 2, causing the driver chip 2 to control at least one set of switching transistors to enter an open-circuit or short-circuit state, thereby entering a specific safe state.

[0046] In one possible implementation, the multiple sets of switching transistors 3 in step one are at least one of IGBT and SiC switching transistors.

[0047] It should be noted that the switching transistors here may be multiple IGBTs, multiple SiC switches, or a combination of multiple IGBTs and multiple SiC switches, depending on the actual process requirements. In addition, the switching transistors may also be other types of switching transistors.

[0048] For example, please refer to Figure 1 The IGBTs consist of two sets of transistors: one lower transistor in the upper bridge circuit and the other lower transistor in the lower bridge circuit. Common safety states include lower transistor short circuit (hereinafter referred to as lower ASC), upper transistor short circuit (hereinafter referred to as upper ASC), and both upper and lower transistors open circuit (hereinafter referred to as FW). ASC actively turns on the three switches of either the upper or lower bridge to provide the motor phase current loop; FW turns on all six switches, cutting off the current loop flowing through the IGBT switches. FW is a commonly used safety state, but if the motor speed is high at this time, the motor back EMF voltage may reverse charge through the diodes, increasing the bus voltage. If the bus voltage is high, it will cause an undesirable high voltage, threatening high-voltage safety. Therefore, a hardware overvoltage fault should be responded to as a lower transistor short circuit state. If a hardware overvoltage and the low-side IGBT drive power supply occur simultaneously, the response should be as an upper transistor short circuit state.

[0049] It should be noted that, depending on the different designs of the switching transistors in different hardware circuits, the switching transistors also correspond to more safety modes, and are not limited to the safety states mentioned above.

[0050] In one possible implementation, the MCU peripheral 11 includes a DC I / O (input / output) module, a peripheral capture module 112, and a peripheral transport module 113. Each fault, after passing through circuits such as comparators, can obtain a digital signal. The DC I / O module 111 is used to receive digital signals from the external MCU circuit and output control signals to the external MCU circuit. The peripheral capture module 112 is used to detect the falling edge of the digital signal to obtain fault information. When a falling edge occurs, it indicates that a hardware fault has occurred. The peripheral transport module 113 is used to receive the fault information.

[0051] In one possible implementation, the hardware fault master module integrated in the multi-core CPU 12 includes a fault latch module 1211, a fault response module 1212, a shared memory module 1213, and a fault management module 1221.

[0052] In one possible implementation, the fault latch module 1211, the fault response module 1212, and the shared memory module 1213 are all located in the secondary core 121 (CoreX) of the multi-core CPU 12.

[0053] In one possible implementation, the fault management module 1221 is located in the main core 122 (Core Y) of the multi-core CPU 12.

[0054] In one possible implementation, the main frequency of current mainstream MCUs is around 100MHz, which can meet the requirements of fault detection time. Event detection types can be configured, and interrupts can be requested directly through peripheral modules. After program initialization configuration is completed, whenever a fault occurs, the peripheral capture module 112 will detect the falling edge of the fault signal and then trigger the peripheral transfer module 113 to move the fault information to a specified memory address, obtaining fault latched information. Because it is only moved on the falling edge, even if the fault is repaired, the value in this memory will not be directly erased, thus achieving the latching of fault information.

[0055] In one possible implementation, the fault response module is used to send the response signal to the driver chip after acquiring the fault latch information.

[0056] However, for some special faults, it is necessary to detect both rising and falling edges. In this case, the occurrence and recovery of the fault will trigger the peripheral transfer module 113 to move the current fault information to the specified memory address, causing the fault information in memory to be erased when the fault is recovered. Therefore, the information of this type of fault must be latched in the software processing logic to ensure that the fault information does not disappear due to the fault recovery.

[0057] In addition, to prevent high-frequency disturbances in the signal, the peripheral acquisition module 112 can be configured with a filtering function to filter the fault signal appropriately. Therefore, a fault latch module 1211 is required to store the fault information in its memory address to obtain the fault latch information.

[0058] In one possible implementation, the event of peripheral device transport module 113's operation can serve as a source of CPU interrupt requests. Each time peripheral device transport module 113 is configured to operate, a CPU interrupt is triggered, handling a hardware fault. The hardware fault handling logic is controlled from... Figure 4 The fault latch module 1211 acquires information about one or more hardware faults that have occurred, then sets the fault response logic according to the fault priority, and then determines the final drive output state.

[0059] The corresponding output status can be achieved by driving the DC I / O module 111 through the MCU peripheral 11. The fault response module 1212 is used to obtain fault information and send a response signal to the driver chip 2 through the DC I / O module 111.

[0060] In one possible implementation, the response signal is a PWM wave, and the DC IO module 111 can output PWM to bring at least one set of switching transistors into the desired safe state.

[0061] In one possible implementation, hardware fault responses involve multiple gate state transitions, necessitating the avoidance of shoot-through signals. This requires inserting a dead time; otherwise, it could lead to shoot-through of the IGBT switch. The CPLD is programmed using a hardware language to design digital logic that ensures a safe hardware dead time during gate state transitions. Additionally, during normal torque control, the MCU outputs a PWM wave, which is then driven to the switch via the CPLD. The CPLD simultaneously performs a dead time check on the PWM wave; if the dead time is too small, a minimum safe dead time is forcibly inserted to prevent switch shoot-through.

[0062] This embodiment configures the peripheral driver output module of a mainstream MCU to form a dead-time protection module 114, achieving the same protection function as a CPLD. The configuration logic is as follows: Figure 6 As shown, when the emitted PWM wave has no dead zone or the dead zone is too small, the dead zone protection module 114 forcibly inserts a dead zone according to the pre-configured value during initialization to prevent shoot-through. The response signal is eliminated by the dead zone protection module 114 and then sent to the DC IO module 111.

[0063] In one possible implementation, the main core 122 diagnoses and repairs hardware faults, thus requiring information exchange with the fault interrupt response module. This embodiment uses memory interaction to achieve this information exchange. Two sets of registers are defined in the memory of the fault interrupt module: a fault register, which sets the corresponding bit according to the detected fault, allowing the main core 122 diagnostic management module to obtain fault information; and a configuration register, through which the main core 122 fault management module 1221 sends a fault clearing instruction to clear fault latch information. The two sets of registers are read and written separately to avoid multi-core data consistency issues. The shared memory module 1213 includes a fault register R1 and a configuration register R2. The fault register R1 determines the location of the fault based on the fault latch information and sets the corresponding bit. The configuration register R2 configures the fault clearing instruction, which is used to clear the fault latch information in the fault latch module 1211 or reset the bits in the fault register R1.

[0064] In one possible implementation, the main core 122 diagnoses and repairs hardware faults, such as... Figure 5 As shown, the fault management module 1221 manages hardware faults through the registers in the shared memory module 1213. The fault management process is as follows: Figure 7 and Figure 8As shown. The fault management module 1221 is used to acquire fault information and perform logical judgment. If a fault exists, it maintains the open circuit state. If there is no fault, it sends a fault clearing instruction to the configuration register to clear the fault latch information, thereby enabling at least one set of switching transistors to work normally.

[0065] Specifically, the shared memory module 1213 includes a fault register R1 and a configuration register R2. The fault register R1 determines the location of the fault based on the fault latch information and sets the corresponding bit. The configuration register R2 configures the fault clearing instruction, which is used to clear the fault latch information in the fault latch module 1211 or reset the bit in the fault register R1.

[0066] The fault management module 1221 includes a fault diagnosis module and a fault clearing module. The fault diagnosis module periodically reads the bits in the configuration register R2. When a fault occurs, it counts the number of fault occurrences and determines whether the count exceeds a set threshold. If so, the fault clearing module does not work. The fault diagnosis module sends a response signal to the driver chip, causing the driver chip to control at least one set of switching transistors to enter an open-circuit or short-circuit state. For example, if the threshold is set to 5 times, if the fault count exceeds 5 times, at least one set of switching transistors will enter an open-circuit or short-circuit state. In other words, by continuously detecting the fault status of the hardware, if the hardware is not detected as having a fault for a period of time, the hardware will be switched to a safe state.

[0067] The fault management module 1221 includes a fault diagnosis module and a fault clearing module. The fault diagnosis module periodically reads the bits in the configuration register R2. When a fault occurs, it counts the number of fault occurrences and determines whether the number of occurrences exceeds a set threshold. If not, the fault clearing module controls the configuration register R2 to send a fault clearing command to reset the fault latch information and the bits in the fault register R1.

[0068] In addition, the MCU peripheral 11 determines whether a hardware fault has occurred. If not, the fault clearing module controls the configuration register R2 to send a fault clearing instruction to reset the fault latch information and the bit bits in the fault register R1.

[0069] The present invention also provides a fault response method for an inverter structure corresponding to the above method, the fault response method being used for the above-described inverter structure.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] In summary, this invention integrates the logic for handling CPLD failures and protecting PWM outputs into the MCU, directly eliminating the need for a CPLD chip and related peripheral circuits. This reduces product costs and increases production cycle time. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An inverter structure, characterized in that, include: The MCU's main control chip and peripherals, driver chips for controlling multiple sets of switching transistors, and a hardware fault management main module; among them, The hardware fault management main module is integrated into the multi-core CPU of the main control chip; The MCU peripheral is used to determine whether a hardware failure has occurred. If so, the failure information is sent to the multi-core CPU. The multi-core CPU receives the fault information and sends a response signal to the driver chip, causing the driver chip to control at least one group of the switching transistors to enter an open-circuit or short-circuit state.

2. The inverter structure according to claim 1, characterized in that: The switching transistor is at least one of IGBT and SiC switching transistor.

3. The inverter structure according to claim 1, characterized in that: The MCU peripherals include a DC I / O module, a peripheral capture module, and a peripheral transport module. The DC I / O module is used to receive digital signals from an external MCU circuit. The peripheral capture module is used to detect the digital signals to obtain the fault information. The peripheral transport module is used to receive the fault information.

4. The inverter structure according to claim 1, characterized in that: The main hardware fault management module includes a fault latch module, a fault response module, a shared memory module, and a fault management module.

5. The inverter structure according to claim 4, characterized in that: The MCU peripheral is used to continuously acquire hardware fault information. The MCU peripheral includes a DC I / O module, a peripheral capture module, and a peripheral transport module. The DC I / O module is used to receive digital signals from the circuit in the MCU. Based on the detection of the digital signals by the peripheral capture module, it determines whether a fault has occurred. If so, it sends the fault information to the peripheral transport module, and the peripheral transport module stores the fault information in a specified memory address.

6. The inverter structure according to claim 4, characterized in that: The fault latch module, fault response module, and shared memory module are all located in the secondary core of the multi-core CPU.

7. The inverter structure according to claim 4, characterized in that: The fault management module is located in the main core of the multi-core CPU.

8. The inverter structure according to claim 5, characterized in that: The fault latching module is used to obtain the fault information from the peripheral device transport module, store the fault information in its memory address, and obtain fault latching information.

9. The inverter structure according to claim 8, characterized in that: The fault response module is used to send the response signal to the driver chip after obtaining the fault latch information.

10. The inverter structure according to claim 9, characterized in that: The response signal is a PWM wave.

11. The inverter structure according to claim 10, characterized in that: The MCU peripheral also includes a dead-time protection module. The response signal is sent to the DC IO module after the dead-time protection module eliminates its pass-through signal.

12. The inverter structure according to claim 9, characterized in that: The shared memory module includes a fault register and a configuration register. The fault register determines the location of the fault based on the fault latch information and sets the corresponding bit. The configuration register configures a fault clearing instruction, which is used to clear the fault latch information or reset the bit in the fault register.

13. The inverter structure according to claim 12, characterized in that: The fault management module includes a fault diagnosis module and a fault clearing module. The fault diagnosis module periodically reads the bit in the configuration register. When a fault occurs, it counts the number of fault occurrences and determines whether the number of occurrences is greater than a set threshold. If so, the fault clearing module does not work. The fault diagnosis module sends a response signal to the driver chip, causing the driver chip to control at least one group of the switching transistors to enter an open circuit or short circuit state.

14. The inverter structure according to claim 12, characterized in that: The fault management module includes a fault diagnosis module and a fault clearing module. The fault diagnosis module is used to periodically read the bit in the configuration register. When a fault occurs, it counts the number of times the fault occurs and determines whether the number of times exceeds a set threshold. If not, the fault clearing module controls the configuration register to send a fault clearing command to reset the fault latch information and the bit in the fault register.

15. The inverter structure according to claim 13 or 14, characterized in that: The MCU peripheral is used to determine whether a hardware fault has occurred. If not, the fault clearing module controls the configuration register to send a fault clearing instruction to reset the fault latch information and the bit in the fault register.

16. The fault response method for the inverter structure according to any one of claims 1 to 15, characterized in that, include: The MCU peripheral determines whether a hardware fault has occurred; if so, the MCU peripheral sends the fault information to the multi-core CPU; after receiving the fault information, the multi-core CPU sends a response signal to the driver chip; the driver chip controls at least one group of the switching transistors to enter an open-circuit or short-circuit state according to the response signal.

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