A method and apparatus for calibrating quadrature error of a zero intermediate frequency receiver

Abstract

The application discloses a zero intermediate frequency receiver quadrature error calibration method and device, in which an initial clock signal of a phase-locked loop of a zero intermediate frequency receiver is acquired; the initial clock signal is subjected to delay demodulation to determine a first clock signal and a second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°; whether there is a duty cycle deviation between the first clock signal and the second clock signal is detected; when the duty cycle deviation is detected, the initial clock signal is calibrated based on the duty cycle deviation. Thus, by subjecting the initial clock signal of the phase-locked loop to delay demodulation, two opposite phase clock signals are determined, the duty cycle deviation of the two signals is used to feed back and adjust the duty cycle of the initial clock signal, a stable closed loop system is formed, and higher precision quadrature error calibration can be realized under the premise of lower static power consumption.

Description

Technical Field

[0001] This application belongs to the field of digital communication technology, and in particular relates to a method and apparatus for calibrating the quadrature error of a zero intermediate frequency receiver. Background Technology

[0002] In recent years, CMOS process dimensions have been gradually decreasing according to Moore's Law, integrated circuit speeds have been increasing, and the data volume of mobile communications has been growing exponentially. Traditional transceivers are no longer sufficient to meet the ever-increasing data demands, making the research of broadband high-speed radio frequency transceivers an important and promising field. Zero-IF (ZIF) architecture has existed since the early days of radio and has undergone numerous engineering applications, but most have ended in failure. In recent years, with the increasing demands for lower cost, lower power consumption, smaller size, higher integration, and greater bandwidth in communication systems, the ZIF solution has been revived as a solution to these problems. The ZIF architecture directly converts baseband to radio frequency. Compared to superheterodyne solutions, it reduces the use of intermediate frequency (IF) and local oscillator (LO) circuits, IF filters, etc., resulting in advantages such as small size, low power consumption, and ease of integration for ZIF transceivers. Today, the ZIF architecture is widely used in the consumer electronics industry, such as in televisions, mobile phones, and Bluetooth technology. ZIF receivers can also cover a very wide range of radio frequencies, typically from hundreds of MHz to approximately 6 GHz. The latest advancements in zero-IF technology have challenged existing high-performance radio architectures, resulting in new products that have achieved performance breakthroughs and enable new applications that were previously unattainable with zero-IF technology.

[0003] While zero-IF architecture offers advantages such as high spectral efficiency, low filter requirements, and low common-mode interference, it also has some drawbacks, such as quadrature errors caused by I / Q mismatch. Due to amplitude and phase imbalances resulting from differences in the I / Q circuit structures, these imbalances manifest as image mirroring in the frequency domain. The position of this pure zero-IF image overlaps with the desired signal, significantly degrading system performance.

[0004] Currently, the industry has not proposed a better technical solution to the above problems. Summary of the Invention

[0005] This application provides a method and apparatus for calibrating the quadrature error of a zero intermediate frequency receiver, which is used to at least solve one of the above-mentioned technical problems.

[0006] In a first aspect, embodiments of this application provide a quadrature error calibration method for a zero-IF receiver, comprising: acquiring an initial clock signal from a phase-locked loop of a zero-IF receiver; performing delayed demodulation on the initial clock signal to determine a corresponding first clock signal and a second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°; detecting whether there is a duty cycle deviation between the first clock signal and the second clock signal; and calibrating the initial clock signal based on the duty cycle deviation when a duty cycle deviation is detected.

[0007] Secondly, embodiments of this application provide a zero-IF receiver quadrature error calibration device, comprising: an initial clock signal acquisition unit configured to acquire an initial clock signal from the phase-locked loop of a zero-IF receiver; a delay adjustment unit configured to perform delay demodulation on the initial clock signal to determine a corresponding first clock signal and a second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°; a duty cycle deviation detection unit configured to detect whether there is a duty cycle deviation between the first clock signal and the second clock signal; and a duty cycle calibration unit configured to calibrate the initial clock signal based on the duty cycle deviation when a duty cycle deviation is detected.

[0008] The beneficial effects of the embodiments of this application are as follows:

[0009] The initial clock signal of the phase-locked loop (PLL) of the zero-IF receiver is delayed and demodulated to determine two inverted clock signals. If the clock duty cycles of the two clock signals are exactly 50%, then the two clock signals should have the same common-mode level. However, in reality, the clock from the PLL often has a duty cycle deviation. The initial clock signal is then calibrated using the duty cycle deviation to adjust the duty cycle of the clock from the PLL to 50%, thus forming a stable closed-loop system. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart illustrating an example of a zero-IF receiver quadrature error calibration method according to an embodiment of this application is shown.

[0012] Figure 2 A schematic diagram of an example of an orthogonal error calibration loop according to an embodiment of this application is shown;

[0013] Figure 3 An embodiment according to this application is shown. Figure 2 A schematic diagram of an example of the clock duty cycle adjuster 220 in the diagram;

[0014] Figure 4 A structural block diagram of an example zero-IF receiver quadrature error calibration apparatus according to an embodiment of this application is shown;

[0015] Figure 5 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0018] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0019] In this application, "module," "system," etc., refer to relevant entities applied to a computer, such as hardware, combinations of hardware and software, software, or software in execution. More specifically, for example, an element can be, but is not limited to, a process running on a processor, a processor, an object, an executable element, an execution thread, a program, and / or a computer. Furthermore, an application program or script running on a server, and the server itself, can also be an element. One or more elements may be in an execution process and / or thread, and elements may be localized on a single computer and / or distributed across two or more computers, and may be run on various computer-readable media. Elements may also communicate via local and / or remote processes based on signals having one or more data packets, for example, signals from a system interacting with another element in a local system, a distributed system, and / or on a network of the Internet that interact with other systems via signals.

[0020] Finally, it should be noted that in this document, the terms "comprising" or "including" include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0021] It should be noted that quadrature error correction (QEC) technology is generally used to prevent image interference. Traditional QEC loops have two types: one directly amplifies the differential signal after analog output filtering and feeds it back to the tail current mirror at the clock input to adjust the clock duty cycle. However, due to the trade-off between system stability and sensitivity, it is difficult to achieve high accuracy, thus affecting the effectiveness of the QEC algorithm. The other type converts the differential signal after analog output filtering into a digital value through a comparator, and then uses this digital value to control a state machine that can automatically adjust and lock the duty cycle. The output of the state machine adjusts the clock duty cycle, but this method makes control cumbersome. Furthermore, the duty cycle adjuster in both of these QEC loops has a static current path, resulting in significant static power consumption, which does not meet the low-power requirements of today's portable devices. Therefore, a high-precision, low-power, and stable QEC solution is urgently needed.

[0022] In view of this, Figure 1 A flowchart illustrating an example of a zero-IF receiver quadrature error calibration method according to an embodiment of this application is shown.

[0023] Regarding the execution subject of the method in the embodiments of this application, it can be any one or more processors with processing capabilities. For example, multiple components can be integrated into one processor, or multiple different components can be set separately to implement the various operations as described in the embodiments of the method in this application. In addition, each step in the embodiments of this application can be implemented by one component or multiple integrated components, and this should not be limited in the embodiments of this application.

[0024] like Figure 1 As shown, in step S110, the initial clock signal of the phase-locked loop from the zero intermediate frequency receiver is obtained.

[0025] In step S120, the initial clock signal is delayed and demodulated to determine the corresponding first clock signal and second clock signal. Here, the phase difference between the first clock signal and the second clock signal is 180°.

[0026] For example, the initial clock signal can be delayed and demodulated by a delay adjustment circuit, and then split into two clock signals with a phase difference of 180° by an inverter.

[0027] In step S130, it is detected whether there is a duty cycle deviation between the first clock signal and the second clock signal.

[0028] In some examples of embodiments of this application, the first clock signal and the second clock signal are low-pass filtered based on preset low-pass filtering settings. Then, for the low-pass filtered first and second clock signals, a duty cycle deviation is detected. This filters out noise signals, ensuring high accuracy of the calculated duty cycle deviation.

[0029] In step S140, when a duty cycle deviation is detected, the initial clock signal is calibrated based on the duty cycle deviation.

[0030] In this embodiment, the initial clock signal of the phase-locked loop of the zero intermediate frequency receiver is delayed and demodulated to determine two inverted clock signals. If the clock duty cycle of the two clock signals is exactly 50%, then the two clock signals should be at the same common-mode level. However, in reality, the clock from the phase-locked loop often has a duty cycle deviation. The initial clock signal is then calibrated using the duty cycle deviation to adjust the duty cycle of the clock from the phase-locked loop to 50%, thus forming a stable closed-loop system.

[0031] Through the embodiments of this application, high-precision orthogonal error calibration can be achieved with low static power consumption, thereby improving the image rejection ratio of 5G receivers.

[0032] Regarding step 140 above, in some examples of embodiments of this application, a corresponding analog feedback signal is determined based on the duty cycle deviation. Then, based on the analog feedback signal, the duty cycle of the initial clock signal is calibrated. Therefore, by determining the analog feedback signal according to the duty cycle deviation, accurate correction of the clock signal output by the phase-locked loop is achieved.

[0033] Specifically, the differential signal corresponding to the duty cycle deviation can be determined, and then the differential signal can be modulated to determine the corresponding bit stream containing duty cycle information. The bit stream can then be converted from digital to analog to determine the corresponding analog feedback signal.

[0034] Figure 2 A schematic diagram of an example of an orthogonal error calibration loop according to an embodiment of this application is shown.

[0035] like Figure 2 As shown, the quadrature error calibration loop includes a phase-locked loop 210, a clock duty cycle adjuster 220, a delay adjustment circuit 230, two low-pass filters 241 / 243 with the same filtering settings, a DSM (delta-sigma modulate) modulator, a decimation filter 260, and a high-precision analog-to-digital converter 270.

[0036] Specifically, the quadrature error calibration loop operates as follows: The clock signal from the phase-locked loop 210 is split into two clock signals, P and N, with a phase difference of 180°, by an inverter after passing through the clock duty cycle adjustment circuit 220 and the delay adjustment circuit 230. These signals then flow into two identical low-pass filters (241 and 243). If the clock duty cycle is exactly 50%, the outputs of the two low-pass filters should be identical common-mode levels. However, in reality, the clock signal from the phase-locked loop often has a duty cycle deviation. Therefore, we can obtain a pair of differential signals based on the common-mode level. This differential signal is fed into the DSM modulator 250 to obtain a bitstream containing duty cycle information. After digital interpolation filtering by the decimation filter 260, the bitstream is converted into an analog signal by a high-precision digital-to-analog converter 270 and fed back to the clock duty cycle adjuster 220.

[0037] Figure 3 An embodiment according to this application is shown. Figure 2 A schematic diagram of an example of the clock duty cycle adjuster 220. (See attached diagram.) Figure 3 As shown, the clock duty cycle adjuster 220 receives analog feedback and adjusts the duty cycle of the clock from the phase-locked loop 210 to 50% based on this feedback, ultimately forming a stable closed-loop system. Thus, the clock duty cycle adjuster eliminates the static current path in the circuit and also overcomes the leakage current problem.

[0038] The embodiments of this application eliminate the static current path in the clock duty cycle regulator, overcoming the leakage problem. Furthermore, by utilizing the high precision of the DCM modulator, the quadrature error calibration accuracy is improved.

[0039] Figure 4 A structural block diagram of an example zero-IF receiver quadrature error calibration apparatus according to an embodiment of this application is shown.

[0040] like Figure 4 As shown, the zero intermediate frequency receiver quadrature error calibration device 400 includes an initial clock signal acquisition unit 410, a delay adjustment unit 420, a duty cycle deviation detection unit 430, and a duty cycle calibration unit 440.

[0041] The initial clock signal acquisition unit 410 is configured to acquire the initial clock signal from the phase-locked loop of the zero intermediate frequency receiver;

[0042] The delay adjustment unit 420 is configured to perform delay demodulation on the initial clock signal to determine the corresponding first clock signal and second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°.

[0043] Duty cycle deviation detection unit 430 is configured to detect whether there is a duty cycle deviation between the first clock signal and the second clock signal;

[0044] Duty cycle calibration unit 440 is configured to calibrate the initial clock signal based on the duty cycle deviation when a duty cycle deviation is detected.

[0045] In some examples of embodiments of this application, the duty cycle deviation detection unit 430 includes: a low-pass filtering module (not shown), configured to perform low-pass filtering processing on the first clock signal and the second clock signal respectively based on a preset low-pass filtering setting; and a duty cycle deviation detection module (not shown), configured to detect whether there is a duty cycle deviation for the first clock signal and the second clock signal after low-pass filtering processing.

[0046] In some examples of embodiments of this application, the duty cycle calibration unit 440 includes: an analog feedback signal determination module (not shown), configured to determine a corresponding analog feedback signal based on the duty cycle deviation; and a duty cycle calibration module (not shown), configured to calibrate the duty cycle of the initial clock signal based on the analog feedback signal.

[0047] In some examples of embodiments of this application, the analog feedback signal determination module includes: a differential signal determination component configured to determine the differential signal corresponding to the duty cycle deviation; a bitstream modulation component configured to modulate the differential signal to determine a corresponding bitstream containing duty cycle information; and a digital-to-analog converter configured to perform digital-to-analog conversion on the bitstream to determine the corresponding analog feedback signal.

[0048] In some examples of embodiments of this application, the bitstream modulation component includes a DSM modulator.

[0049] In some examples of embodiments of this application, an interpolation filter is also deployed in the zero intermediate frequency receiver quadrature error calibration device, which is used to digitally interpolate and filter the bit stream before performing digital-to-analog conversion on the bit stream.

[0050] In some embodiments, the present invention provides a non-volatile computer-readable storage medium storing one or more programs including execution instructions, which can be read and executed by electronic devices (including but not limited to computers, servers, or network devices) to perform any of the above-described zero-IF receiver quadrature error calibration methods of the present invention.

[0051] In some embodiments, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to perform any of the above-described zero intermediate frequency receiver quadrature error calibration methods.

[0052] In some embodiments, the present invention also provides an electronic device comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a zero intermediate frequency receiver quadrature error calibration method.

[0053] In some embodiments, the present invention also provides a storage medium storing a computer program thereon, characterized in that the program, when executed by a processor, implements a zero-IF receiver quadrature error calibration method.

[0054] The zero-IF receiver quadrature error calibration device described in the above embodiments of the present invention can be used to execute the zero-IF receiver quadrature error calibration method of the present invention, and accordingly achieve the technical effects achieved by the zero-IF receiver quadrature error calibration method described in the above embodiments of the present invention, which will not be elaborated further here. In the embodiments of the present invention, the relevant functional modules can be implemented by a hardware processor.

[0055] Figure 5 This is a schematic diagram of the hardware structure of an electronic device for performing a zero-IF receiver quadrature error calibration method according to another embodiment of this application, as shown below. Figure 5 As shown, the device includes:

[0056] One or more processors 510 and memory 520, Figure 5 Take the 510 processor as an example.

[0057] The apparatus for performing the zero intermediate frequency receiver quadrature error calibration method may further include: an input device 530 and an output device 540.

[0058] The processor 510, memory 520, input device 530, and output device 540 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0059] The memory 520, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the zero-IF receiver quadrature error calibration method in the embodiments of this application. The processor 510 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 520, thereby implementing the zero-IF receiver quadrature error calibration method described in the above embodiments.

[0060] Memory 520 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the zero-IF receiver quadrature error calibration device. Furthermore, memory 520 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 520 may optionally include memory remotely located relative to processor 510, and this remote memory may be connected to the zero-IF receiver quadrature error calibration device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0061] Input device 530 can receive input digital or character information, and generate signals related to user settings and function control of the zero intermediate frequency receiver quadrature error calibration device. Output device 540 may include a display screen or other display device.

[0062] The one or more modules are stored in the memory 520, and when executed by the one or more processors 510, they perform the zero intermediate frequency receiver quadrature error calibration method in any of the above method embodiments.

[0063] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the methods provided in the embodiments of this application.

[0064] The electronic devices in this application embodiments exist in various forms, including but not limited to:

[0065] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include: smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones, etc.

[0066] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0067] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes: audio and video players (such as iPods), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0068] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0069] (5) Other electronic devices with data interaction functions.

[0070] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for calibrating the quadrature error of a zero-IF receiver, comprising: The initial clock signal is obtained from the phase-locked loop of the zero intermediate frequency receiver; The initial clock signal is delayed and demodulated to determine the corresponding first clock signal and second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°. Detect whether there is a duty cycle deviation between the first clock signal and the second clock signal; When a duty cycle deviation is detected, the initial clock signal is calibrated based on the duty cycle deviation; The step of calibrating the initial clock signal based on the duty cycle deviation includes: Based on the duty cycle deviation, the corresponding analog feedback signal is determined; Based on the analog feedback signal, the duty cycle of the initial clock signal is calibrated; The step of determining the corresponding analog feedback signal based on the duty cycle deviation includes: Determine the differential signal corresponding to the duty cycle deviation; The differential signal is modulated to determine a corresponding bit stream containing duty cycle information; After the bitstream is digitally interpolated and filtered by an interpolation filter, it is converted into an analog signal by a high-precision digital-to-analog converter and fed back to the clock duty cycle adjuster.

2. The method according to claim 1, wherein, The detection of whether there is a duty cycle deviation between the first clock signal and the second clock signal includes: Based on the preset low-pass filtering settings, the first clock signal and the second clock signal are respectively subjected to low-pass filtering processing; For the first and second clock signals that have undergone low-pass filtering, detect whether there is a duty cycle deviation.

3. A zero-IF receiver quadrature error calibration device, characterized in that, The apparatus is used to implement a zero-IF receiver quadrature error calibration method as described in any one of claims 1-2, comprising: The initial clock signal acquisition unit is configured to acquire the initial clock signal from the phase-locked loop of the zero intermediate frequency receiver; The delay adjustment unit is configured to perform delay demodulation on the initial clock signal to determine the corresponding first clock signal and second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°. The duty cycle deviation detection unit is configured to detect whether there is a duty cycle deviation between the first clock signal and the second clock signal; A duty cycle calibration unit is configured to calibrate the initial clock signal based on the duty cycle deviation when a duty cycle deviation is detected.

4. The apparatus according to claim 3, wherein, The duty cycle deviation detection unit includes: The low-pass filter module is configured to perform low-pass filtering on the first clock signal and the second clock signal respectively based on preset low-pass filter settings; The duty cycle deviation detection module is configured to detect whether there is a duty cycle deviation for the first clock signal and the second clock signal after low-pass filtering.

5. The apparatus according to claim 3, wherein, The duty cycle calibration unit includes: The analog feedback signal determination module is configured to determine the corresponding analog feedback signal based on the duty cycle deviation. The duty cycle calibration module is configured to calibrate the duty cycle of the initial clock signal based on the analog feedback signal.

6. The apparatus according to claim 5, wherein, The analog feedback signal determination module includes: A differential signal determination component is configured to determine the differential signal corresponding to the duty cycle deviation; A bitstream modulation component is configured to modulate the differential signal to determine a corresponding bitstream containing duty cycle information; A digital-to-analog converter is configured to perform digital-to-analog conversion on the bitstream to determine a corresponding analog feedback signal.

7. The apparatus according to claim 6, wherein, The bitstream modulation component includes a DSM modulator.

8. The apparatus according to claim 6, further comprising: An interpolation filter is used to digitally interpolate and filter the bitstream before performing digital-to-analog conversion on the bitstream.

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