Apparatus and method for delay measurement initialization

Abstract

The present disclosure relates to apparatuses and methods for delay measurement initialization. An example apparatus includes a clock enable circuit that provides a first clock signal having one-half the frequency of an input clock signal and a second clock signal having one-quarter the frequency of the input clock signal, a coarse delay that provides the first clock signal with a coarse delay, a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal, a model delay that has a feedback delay equal to the sum of the delays of an input stage and an output stage and that provides a feedback signal that is the output clock signal with the feedback delay, and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes a synchronizer that receives the feedback signal and the second clock signal and provides a stop signal to the coarse delay.

Description

Technical Field

[0001] This application generally relates to semiconductor memories. More specifically, this application relates to apparatus and methods for delay measurement initialization. Background Technology

[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are the required characteristics of semiconductor memories. To achieve higher memory access speeds, a clock signal is used as a reference signal to adjust the timing of operations in the semiconductor memory.

[0003] When an external clock signal enters the circuit, the clock phase of the internal clock signal, based on the external clock signal, may be delayed due to the inherent delays of the circuit components. At high operating speeds, distortion of the clock signal duty cycle can adversely affect circuit operation. To accommodate these delay and distortion effects, the clock path may include delay circuitry. Delay circuitry, such as a delay-locked loop (“DLL”), can be used to adjust the clock phase to match the phase of the external clock. A typical DLL may include a coarse delay providing a coarser resolution for delay adjustment and a fine delay providing a finer resolution for delay adjustment.

[0004] To adjust the clock phase, measurements can be performed with a coarser resolution for delay adjustment. When the power is on, the DLL can perform measurement initialization. During initialization, the DLL may include detectors that detect a number of cycles longer than the inherent delay. The coarser resolution can be adjusted to have a delay matching the difference between the number of cycles and the inherent delay. The DLL may include a synchronizer in the circuit that indicates the detection timing to the detector. When an asynchronous signal is transmitted to a circuit operating with a synchronized signal, the asynchronous signal can be synchronized to cross into the synchronization domain. The synchronizer can receive the signal and provide a signal with timings for a reference signal. The synchronizer may include flip-flops (FFs). It is known that FFs can have a set time before receiving a signal. However, FFs can receive a signal before the set time is complete. Therefore, the output node of the FF can be metastable and the FF can provide a synchronized signal with a delay. To avoid this metastability, one or more additional FFs can be coupled in series to the first FF. By adding this(s) of FFs, even if the output signal of the first FF has a delay when addressing the metastability, the set time of the(s) additional FFs coupled to the first FF can be ensured, and therefore, the signals can be properly synchronized. However, the metastability of the additional FF will eventually lead to failure, which can be measured as the synchronizer's mean time between failures (MTBF). It is known that the MTBF decreases exponentially based on the difference between one period of the input clock signal and the settling time of the additional FF. To mitigate failure by increasing the synchronizer's MTBF, it is desirable for the synchronizer to have an input clock signal with a longer period. Summary of the Invention

[0005] On one hand, this application provides an apparatus comprising: a delay stage including: a clock enable circuit configured to receive first and second clock signals having a first frequency, and configured to provide third and fourth clock signals having a second frequency, the second frequency being half of the first frequency; a delay coupled to the clock enable circuit and configured to receive the first clock signal and provide the first clock signal having an adjustable delay as an output clock signal; a model delay circuit configured to receive the output clock signal and provide the output clock signal having a model delay as a feedback signal; and a measurement initialization circuit including: a stop control circuit configured to provide a first stop signal to stop measurement initialization in response to the third and fourth clock signals and further in response to the feedback signal, the stop control circuit including: a plurality of synchronizers configured to receive the third and fourth clock signals and a complementary clock signal of the third and fourth clock signals respectively, and further configured to provide a plurality of second stop signals, wherein the stop control circuit is configured to provide the first stop signal in response to the plurality of second stop signals.

[0006] On the other hand, this application provides an apparatus comprising: an input stage including a frequency divider configured to receive an internal clock signal having a first frequency and further configured to provide first and second clock signals having a second frequency, the second frequency being half of the first frequency; a delay stage including: a clock enable circuit configured to receive the first and second clock signals from the frequency divider, configured to provide the first clock signal, and further configured to provide third and fourth clock signals having a third frequency, the third frequency being half of the second frequency; a coarse delay coupled to the clock enable circuit and configured to receive the first clock signal and provide the first clock signal having an adjustable coarse delay as a first delayed clock signal; and a fine delay coupled to the coarse delay and configured to receive the first delayed clock signal and provide... The output clock signal includes a first delayed clock signal with an adjustable fine delay; a model delay circuit coupled to the delay stage and configured to receive the output clock signal and provide the output clock signal with the model delay as a feedback signal; and a measurement initialization circuit configured to perform measurement initialization using the coarse delay, the measurement initialization circuit including: a stop control circuit configured to provide first and second stop signals in response to the third and fourth clock signals and further in response to the feedback signal; and a detection circuit configured to receive the third and fourth clock signals and the first and second stop signals, configured to start detecting the number of cycles of the third frequency in response to the third and fourth clock signals, and further configured to stop detecting the number of cycles of the third frequency in response to the first stop signal or the second stop signal.

[0007] On the other hand, this application provides a method comprising: providing a first clock signal having a first frequency; delaying the first clock signal by a delay line to provide an output clock signal; delaying the output clock signal by a model delay to provide a feedback signal; providing third and fourth clock signals having a second frequency, the second frequency being half of the first frequency; and receiving the feedback signal by first, second, third, and fourth synchronizers; receiving the third and fourth clock signals and a complementary clock signal of the third and fourth clock signals by the first, second, third, and fourth synchronizers respectively; providing a plurality of first stop signals by the first, second, third, and fourth synchronizers in response to the feedback signal, the third and fourth clock signals, and the complementary clock signal of the third and fourth clock signals; and providing a second stop signal to the delay line in response to the plurality of first stop signals, the second stop signal indicating a stop to measurement initialization. Attached Figure Description

[0008] Figure 1This is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a block diagram of a DLL circuit in a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a block diagram of a DLL circuit in a semiconductor device including a measurement initialization circuit according to an embodiment of the present disclosure.

[0011] Figure 4 It is based on Figure 3 Timing diagrams of various signals during the measurement initialization operation of the DLL circuit in the embodiment.

[0012] Figure 5A Is Figure 3 A rough diagram of the delay before the initialization operation and the shift register (rough).

[0013] Figure 5B Is Figure 3 A rough diagram of the delay and shift register (rough) after the initialization operation.

[0014] Figure 6 This is a schematic diagram of a DLL circuit in a semiconductor device including a measurement initialization circuit according to an embodiment of the present disclosure.

[0015] Figure 7 This is a circuit diagram of a synchronizer according to an embodiment of the present disclosure.

[0016] Figure 8 This is a block diagram of a multi-cycle (N) detection circuit according to an embodiment of the present disclosure.

[0017] Figure 9 This is a circuit diagram of a binary counter according to an embodiment of the present disclosure. Detailed Implementation

[0018] The various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of this disclosure by way of illustration. This detailed description contains sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0019] Figure 1This is a schematic block diagram of a chip 101 in a semiconductor memory device 10 according to an embodiment of the present disclosure. In some embodiments, the semiconductor memory device 10 is a device that may include a plurality of chips including chip 101. Chip 101 may include clock input circuitry 105, internal clock generator 107, command and address input circuitry 11, address decoder 12, command decoder 125, a plurality of row decoders 13, a memory cell array 15 including a sense amplifier 151 and a transfer gate 152, a plurality of column decoders 14, a plurality of read / write amplifiers 16, input / output (I / O) circuitry 17, and voltage generator circuitry 19. The semiconductor memory device 10 may include a plurality of external terminals, including address and command terminals coupled to a command / address bus, clock terminals CK and CKB, data terminal DQ, data strobe terminal DQS, and data shield terminal DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0020] The memory cell array 15 includes multiple memory banks (e.g., memory banks 0 to 7), each memory bank including multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of the word lines WL for each memory bank is performed by the corresponding row decoder 13, and the selection of the bit lines BL is performed by the corresponding column decoder 14. Multiple sense amplifiers SAMP 151 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line (e.g., LIOT / B), which is further coupled to a corresponding one of at least two main I / O line pairs (e.g., MIOT / B) via a transfer gate TG 152 acting as a switch.

[0021] The command and address input circuit 11 can receive address signals and memory address signals from the outside via the command / address bus (C / A) at the command / address terminal and transmit the address signals and memory address signals to the address decoder 12. The address decoder 12 can decode the address signals received from the command and address input circuit 11 and provide an address signal ADD. The address signal ADD can include row address signals to the row decoder 13 and column address signals to the column decoder 14. The address decoder 12 can also receive memory address signals and provide memory address signals to the row decoder 13 and the column decoder 14.

[0022] The command and address input circuit 11 can receive command signals from the outside via the command / address bus at the command / address terminal and provide the command signals to the command decoder 125. The command decoder 125 can decode the command signals and generate various internal command signals. For example, the internal command signals may include row command signals for selecting word lines and column command signals for selecting bit lines, such as read commands or write commands.

[0023] Therefore, when an activation command is issued and a row address is supplied in a timely manner, and a read command is issued and a column address is supplied in a timely manner, read data is read from the memory cell array 15 specified by the row address and column address. The read / write amplifier 16 can receive the read data and provide it to the I / O circuit 17. The I / O circuit 17 can provide the read data, along with the data strobe signal at the data strobe terminal DQ and the data mask signal at the data mask terminal DM, to the outside via the data terminal DQ. Similarly, when an activation command is issued and a row address is supplied in a timely manner, and a write command is issued and a column address is supplied in a timely manner, the I / O circuit 17 can receive the write data at the data terminals DQ, DQS, and DM, along with the data strobe signal at DQS and the data mask signal at DM, and provide the write data to the memory cell array 15 via the read / write amplifier 16. Therefore, write data can be written to the memory cell specified by the row address and column address.

[0024] Turning to the explanation of the external terminals included in the semiconductor device 10, clock terminals CK and CKB can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK. In some embodiments, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 17. IO circuit 17 can use the phase-controlled internal clock signal LCLK as a timing signal for determining the output timing of read data.

[0025] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 19. Voltage generator circuit 19 can generate various internal voltages VKK, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. The internal voltage VKK can be used in the line decoder 13, the internal voltage VARY can be used in the sense amplifier 151 included in the memory cell array 15, and the internal voltage VPERI can be used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. I / O circuit 17 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as the power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 17.

[0026] In semiconductor devices with high-speed memory access, the read data to be provided on the data terminal DQ and the data strobe signal at the data strobe terminal DQS need to be synchronized with the external clock signals CK and CKB. Figure 2 This is a block diagram of a DLL circuit 200 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the DLL circuit 200 may be a DLL circuit used as an internal clock generator 107. The DLL circuit 200 may include an input stage 202, an output stage 206, and delay stages 204a and 204b coupled in parallel between the input stage 202 and the output stage 206. The DLL circuit 200 may further include a model delay 222 and a phase detector 224 coupled between the output node and the input node of the delay stage 204a.

[0027] Input stage 202 may include clock input circuitry 208 and frequency divider 210. In some embodiments, clock input circuitry 208 may be... Figure 1 The clock input circuit 105. A frequency divider 210 can receive an internal clock signal ICLK and its complementary signal ICLKB based on external clock signals CK and CKB from the clock input circuit 208 during normal operation. The frequency divider 210 can provide clock signals Ref0 and Ref90 with frequencies half the frequency of the internal clock signal ICLK. Clock signal Ref90 is delayed by approximately 90° phase difference from clock signal Ref0. Delay stages 204a and 204b may include a clock enable circuit 212. The clock enable circuit 212 can receive and provide clock signals Ref0 and Ref90. The clock enable circuit 212 can be enabled or disabled to provide some of the clock signals (e.g., Ref90) depending on whether the DLL circuit is in normal operation or in measurement initialization operation.

[0028] Delay stage 204a may include a delay line that provides a clock signal Ref0 from clock enable circuit 212 and provides a clock signal Ref0 with an adjustable delay as an output clock signal. For example, the delay line includes a coarse delay 214a and a fine delay 216a coupled in series. The coarse delay 214a receives the clock signal Ref0 from clock enable circuit 212. The coarse delay 214a is a variable (e.g., adjustable) delay with a coarse (e.g., relatively large) step size for delay adjustment. The fine delay 216a is another variable delay with a fine (e.g., relatively small) step size for delay adjustment, the fine step size being smaller than the coarse step size of the coarse delay 214a. Delay stage 204a may further include a duty cycle adjustment circuit 218a and a phase splitter 220a. The duty cycle adjustment circuit 218a adjusts the duty cycle of the clock signal Ref0 delayed by the coarse delay 214a and the fine delay 216a. After duty cycle adjustment by duty cycle adjustment circuit 218a, phase splitter 220a can provide output clock signal CK_Out 0 and its complementary clock signal CK_Out 2 based on delayed clock signal Ref0. Similarly, delay stage 204b may include a series-coupled coarse delay 214b and fine delay 216b. Coarse delay 214b receives clock signal Ref90 from clock enable circuit 212. Coarse delay 214b is a variable delay with a coarse (e.g., relatively large) step size for delay adjustment, while fine delay 216b is a variable delay with a fine (e.g., relatively small) step size for delay adjustment. Delay stage 204b may further include duty cycle adjustment circuit 218b and phase splitter 220b. After duty cycle adjustment by duty cycle adjustment circuit 218b, phase splitter 220b can provide output clock signal CK_Out 1 and its complementary clock signal CK_Out 3 based on delayed clock signal Ref90. The output clock signals CK_Out 0-3 from delay stages 204a and 204b can be provided to output stage 206.

[0029] Output stage 206 may include a data queue / data queue gating serializer 232 and a data queue / data queue gating output circuit 234. The data queue / data queue gating serializer 232 receives the output clock signal CK_Out 0-3 and serializes it into an internal clock signal LCLK. The internal clock signal LCLK may, for example, be provided to the data queue / data queue gating output circuit 234 in I / O circuit 17. The internal clock signal LCLK can be used as a reference signal for controlling the supply of... Figure 1 The timing of reading data DQ and data strobe signal DQS in the process.

[0030] The output clock signal CK_Out 0 from delay stage 204a can also be supplied to model delay 222. Model delay 222 can represent a delay equal to the sum of delays along the clock path, such as the sum of delay t1 in input stage 202 and delay t3 in output stage 206. In some embodiments, model delay 222 can represent Figure 1 The delay of the clock input circuit 105 is the sum of the delay of the I / O circuit 17. The feedback signal Fb from the model delay 222 can be provided to the phase detector 224 via the clock enable circuit 212. The phase detector 224 can detect the phase shift between the feedback signal Fb and the clock signal Ref0, and provide the phase shift signal to the delay control circuit 226. In response to the phase shift signal, the delay control circuit 226 can provide a control signal. The delay control circuit 226 may include a shift register (coarse) 228 and a shift register (fine) 230. The shift register (coarse) 228 can store the delay amount with coarse resolution and provide control signals representing the delay amount to the coarse delays 214a and 214b. The shift register (fine) 230 can store the delay amount with fine resolution and provide control signals representing the delay amount to the fine delays 216a and 216b. The sum of delay t2, which includes coarse delay 214a and fine delay 216a, is adjusted in such a way that the sum of delays t1, t2 and t3 becomes multiple cycles (N*tCK) of the clock signal Ref0.

[0031] The delays of delay stages 204a and 204b can be reduced when the phase of the feedback signal Fb from model delay 222 lags behind the phase of the clock signal Ref0. Conversely, the delays of delay stages 204a and 204b can be increased if the phase of the feedback signal Fb from model delay 222 leads the phase of the clock signal Ref0. Each of delay stages 204a and 204b can be controlled to lock the phase of the feedback signal Fb in sync with the phase of the clock signal Ref0. Each of coarse delays 214a and 214b may include series coupling to provide even / odd input clock signals to multiple delay units of fine delays 216a and 216b, respectively. Here, odd clock signals can be provided from selected odd-numbered units among the multiple delay units, and even clock signals can be provided from selected even-numbered units among the multiple delay units. The odd and even numbers are consecutive. In response to a control signal from shift register (coarse) 228, the even / odd input clock signals can have a phase difference relative to each other. Fine delays 216a and 216b can further receive control signals from shift register (fine) 230. Fine delays 216a and 216b can provide a locked clock signal in response to the even / odd input clock signals and the fine control signal. The corresponding locked clock signals are provided to duty cycle adjustment circuits 218a and 218b and further to phase splitters 220a and 220b to provide the internal clock signal LCLK, as described above for duty cycle adjustment and serialization. Therefore, the read data and data strobe signal DQS, timed by the internal clock signal LCLK, can be synchronized with the external clock signals CK and CKB.

[0032] Figure 3 This is a block diagram of a DLL circuit 300 in a semiconductor device including a measurement initialization circuit 308 according to embodiments of the present disclosure. The measurement initialization circuit 308 is used for measurement initialization operations. In some embodiments of the present disclosure, the DLL circuit 300 may be a DLL circuit used as an internal clock generator 107.

[0033] DLL circuit 300 may include input stage 302, output stage 306, and delay stage 304 coupled between input stage 302 and output stage 306. Output stage 306 can provide an internal clock signal LCLK. Output stage 306 is similar to the previously referenced... Figure 2 The description of output stage 206 is similar, so for the sake of brevity, a detailed description of output stage 306 is not provided.

[0034] Input stage 302 may include clock input circuitry 312 and frequency divider 314. In some embodiments, clock input circuitry 312 may be... Figure 1The clock input circuit 105. A frequency divider 314 receives from the clock input circuit 312 an internal clock signal ICLK and its complementary signal ICLKB based on external clock signals CK and CKB. The frequency divider 314 can provide clock signals Ref0(1 / 2F) and Ref180(1 / 2F) with frequencies half that of the internal clock signal ICLK. Clock signal Ref180(1 / 2F) is delayed by approximately 180° phase difference from clock signal Ref0(1 / 2F), the phase difference being one cycle of the internal clock signal ICLK.

[0035] Delay stage 304 can receive a clock signal Ref0(1 / 2F) from divider 314. Delay stage 304 may include clock enable circuit 316 and delay lines, the delay lines including a coarse delay 318 and a fine delay 320 coupled in series. In some embodiments, clock enable circuit 316 is similar to clock enable circuit 212, coarse delay 318 is similar to coarse delay 214a, and fine delay 320 is similar to... Figure 2 Similar to the fine delay 216a. Clock enable circuit 316 can receive clock signals Ref0(1 / 2F) and Ref180(1 / 2F) from divider 314. Clock enable circuit 316 can provide clock signal Ref0(1 / 4F) to activate coarse delay 318 by dividing clock signal Ref0(1 / 2F). The frequency of clock signal Ref0(1 / 4F) is one-quarter of the frequency of internal clock signal ICLK. Coarse delay 318 has a coarse (e.g., relatively large) step size for delay adjustment, while fine delay 320 has a fine (e.g., relatively small) step size for delay adjustment. Output clock signal CK_Out0 from fine delay 320 can be provided to output stage 306. Coarse delay 318 can be coupled to shift register (coarse) 322 and fine delay 320 can be coupled to shift register (fine) 324. At the end of the initialization operation, shift register (coarse) 322 and shift register (fine) 324 can store the delay amounts of coarse delay 318 and fine delay 320, respectively. A measurement initialization procedure is performed to initialize coarse delay 318.

[0036] DLL circuit 300 may further include a model delay 310 between the output node and the input node of delay stage 304. An output clock signal CK_Out 0 from delay stage 304 may be supplied to model delay 310. Model delay 310 may represent a delay equal to the sum of delays along the clock path, such as the sum of delays in input stage 302 and delays in output stage 306. In some embodiments, model delay 310 may represent... Figure 1 The delay of the clock input circuit 105 is the sum of the delay of the IO circuit 17. The feedback signal Fb of the model delay 310 can be provided to the clock enable circuit 316.

[0037] Clock enable circuit 316 can further provide clock signals Ref0(1 / 4F) and Ref180(1 / 4F) to measurement initialization circuit 308 by dividing clock signals Ref0(1 / 2F) and Ref180(1 / 2F) from frequency divider 314. The frequency of clock signal Ref180(1 / 4F) is also one-quarter of the frequency of internal clock signal ICLK. Clock signal Ref180(1 / 4F) is delayed from clock signal Ref0(1 / 4F) by approximately 180° phase difference, which is one cycle of internal clock signal ICLK. Clock enable circuit 316 can also provide feedback signal Fb from model delay 310 to measurement initialization circuit 308. Measurement initialization circuit 308 may include measurement delay clock enable control circuit 326, buffer model 328, stop control circuit 330, and multi-cycle (N) detection circuit 332. The measurement delay clock enable control circuit 326, buffer model 328, and stop control circuit 330, together with the coarse delay 318, can perform DLL measurement initialization. While DLL measurement initialization is being performed, the multi-cycle (N) detection circuit 332 can perform multi-cycle (N) detection.

[0038] Figure 4 This is a timing diagram of various signals during the measurement initialization operation according to an embodiment. (Refer to...) Figure 3 The DLL circuit 300 describes the measurement initialization operation. However, Figure 4 The measurement initialization operation is not limited to the DLL circuit 300, and in some embodiments of this disclosure, Figure 4 The measurement initialization operation is used in conjunction with other timing circuits.

[0039] The following will follow Figure 4The timing diagram describes the time sequence of the measurement initialization operation and the functionality of each circuit and / or component in the measurement initialization circuit 308. The measurement initialization operation begins at time T1. As previously described, the coarse delay 318 does not provide effective delay at time T1. The clock enable circuit 316 receives the clock signal Ref0(1 / 2F) from the divider 314. After dividing the clock signal Ref0(1 / 2F), the clock signal Ref0(1 / 4F) can be provided from the clock enable circuit 316 to the coarse delay 318 and further to the fine delay 320. The coarse delay 318 and the fine delay 320 at time T1 may not have any delay. The output clock signal from the fine delay 320 can be provided as the output clock signal CK_Out 0 to the model delay 310. The model delay 310 can provide a feedback signal Fb in response to the output clock signal CK_Out 0. The feedback signal Fb contains the inherent delay of the delay stage 306 and the delay of the model delay 310 relative to the Ref0(1 / 4F) clock signal.

[0040] Simultaneously, the clock enable circuit 316, in response to the clock signals Ref0(1 / 2F) and Ref180(1 / 2F) from the frequency divider 314, provides clock signals Ref0(1 / 4F) and Ref180(1 / 4F) to the measurement initialization circuit 308 to initiate multi-cycle (N) detection. The clock signals Ref0(1 / 4F) and Ref180(1 / 4F) are provided to the multi-cycle (N) detection circuit 332. In response to the clock signals Ref0(1 / 4F) and Ref180(1 / 4F), the start signal Start in the multi-cycle (N) detection circuit 332 is activated at time T1, and the measurement initialization operation is performed. The start signal Start is responsive to the clock signal Ref0(1 / 4F). In response to the start signal, at time T1', following a synchronization delay from T1 (e.g., two cycles of Ref0(1 / 4F)), multi-cycle (N) detection is initiated.

[0041] At time T2, the feedback signal Fb can be provided to the measurement delay clock enable control circuit 326 via the clock enable circuit 316. At time T3, the measurement delay clock enable control circuit 326 can provide the measurement delay clock enable signal MeasDlyClkEnFast to the buffer model 328 in response to the feedback signal Fb. In some embodiments, time T3 immediately follows time T2. Figure 4 In the process, time T2 and T3 are basically the same.

[0042] In response to the measurement delay clock enable signal MeasDlyClkEnFast, buffer model 328 can be activated at T4 to provide a default delay amount of coarse delay 318 to stop control circuit 330. If coarse delay 318 decreases during delay adjustment during measurement initialization, the default delay amount can be used to prevent underflow of coarse delay 318. In some embodiments, the default delay amount may be approximately several steps of coarse delay 318. Therefore, the signal (Buf->Stop) from buffer model 328 to stop control circuit 330 may be delayed by the default delay amount from the measurement delay clock enable signal MeasDlyClkEn.

[0043] The stop control circuit 330 can receive a signal (Buf->Stop) from the buffer model 328 and clock signals Ref0(1 / 4F) and Ref180(1 / 4F) from the clock enable circuit 316. In response to the rising or falling edge of either the signal (Buf->Stop) from the buffer model 328 or the clock signals Ref0(1 / 4F) and Ref180(1 / 4F), the stop control circuit 330 can provide valid stop signals Stop0 and Stop180, and at T5', after a synchronization delay of T5 (e.g., two cycles of Ref180F(1 / 4F)), in response to Stop signals Stop0 and Stop180, further provide a stop signal MeasStop to the slightly delayed 318 and the shift register (coarse) 322. Figure 4 In this example, the stop control circuit 330 responds immediately to the first rising edge of the clock signal Ref180F (1 / 4F) at T5' after the rising edge of the signal (Buf->Stop) with synchronous delay from the buffer model 328. The delay of the coarse delay 318 can be measured from T2' / T3' after the synchronous delay from T2 / T3 when another measurement delay clock enable signal MeasDlyClkEn, provided to the coarse delay 318, is activated only at T5'. Figure 5A It means in Figure 3 This diagram illustrates the activated delay steps of the coarse delay 318 at time T1 prior to the initialization operation and the corresponding registers contained in the shift register (coarse) 322. Before measurement initialization, the coarse delay 318 may not have an additional delay, where all steps C1 to C63 are deactivated. The shift register (coarse) 322 causes all registers Q1 to Q63 to store values ​​indicating an inactive state. In this example, there are 63 steps; however, the number of steps is not limited to 63. Any number of steps suitable for controlling the coarse delay 318 can be used to implement the shift register (coarse) 322.

[0044] Figure 5BIt means in Figure 4 A schematic diagram of the activated delay step of the coarse delay 318 at T5 after the initialization operation and the corresponding register contained in the shift register (coarse) 322. After measurement initialization, the stop control circuit 330 may further provide another stop signal MeasStop, which may signal the earliest activation of stop signals Stop0 and Stop180 to the coarse delay 318. The coarse delay 318 may stop adjusting its delay to have the initial delay amount in response to the stop signal MeasStop. Figure 5B In an example, the coarse delay 318 may have an initial delay amount, wherein delay steps C1 to C8 are activated and C9 to C63 are deactivated. The shift register (coarse) 322 may store the initial delay amount of the coarse delay 318 in corresponding registers. For example, the shift register (coarse) 322 may include registers Q1 to Q8 storing values ​​reflecting the active state of the initial delay amount of the coarse delay 318 and registers Q9 to Q63 storing values ​​indicating the inactive state. The initial delay amount of the coarse delay 318 may include the difference between a period of time N (number of cycles) and the delay represented by the model delay 310. Therefore, the initial delay amount may be set in the shift register (coarse) 322.

[0045] Furthermore, stop signals Stop0 and Stop180 are provided to the multi-cycle (N) detection circuit 332. In response to the activation of stop signals Stop0 and Stop180, the multi-cycle (N) detection circuit 332 can stop counting the number of cycles N of the internal clock signal ICLK at T5'. Figure 4 In this example, the stop signal can be a Stop180 signal responding to the rising edge of the clock signal Ref180F(1 / 4F), and the number of cycles N from T1' to T5' is 3. The number of cycles N of the internal clock signal ICLK can be provided to several circuits for delay control.

[0046] Figure 6 This is a schematic diagram of a measurement initialization circuit 608 according to an embodiment of the present disclosure.

[0047] In some embodiments of this disclosure, the measurement initialization circuit 608 may be included in a DLL circuit that serves as an internal clock generator 107. Figure 6 This diagram illustrates a series-coupled clock input circuit 602, a frequency divider 604, and a clock enable circuit 606, along with a measurement initialization circuit 608 coupled to the clock enable circuit 606. The clock input circuit 602, frequency divider 604, and clock enable circuit 606 together are available as previously referenced. Figure 3The clock signals Ref0(1 / 4F) and Ref180(1 / 4F) are described in the clock input circuit 312, frequency divider 314, and clock enable circuit 316. Therefore, the description of the clock input circuit 602, frequency divider 604, and clock enable circuit 606 will not be repeated. The clock enable circuit 606 can also provide a feedback signal Fb from the model delay (e.g., model delay 310) to the measurement initialization circuit 608.

[0048] The measurement initialization circuit 608 may include a measurement delay clock enable control circuit 610, a buffer model 612, a stop control circuit 614, and a multi-cycle (N) detection circuit 616. The measurement delay clock enable control circuit 610 and the buffer model 612 may be based on earlier references. Figure 3 The measurement delay clock enable control circuit 326 and buffer model 328 are described. Therefore, the description of the measurement delay clock enable control circuit 610 and buffer model 612 will not be repeated. The stop control circuit 614 can receive the signal (Buf->Stop) from the buffer model 612 and the clock signals Ref0(1 / 4F) and Ref180(1 / 4F) from the clock enable circuit 606. The stop control circuit 614 can also receive complementary clock signals Ref0F(1 / 4F) and Ref180F(1 / 4F) of the clock signals Ref0(1 / 4F) and Ref180F(1 / 4F). The measurement initialization circuit 608 may include an inverter that can invert the clock signals Ref0(1 / 4F) and Ref180(1 / 4F) to generate complementary clock signals Ref0F(1 / 4F) and Ref180F(1 / 4F). In some embodiments, the inverter may be included between the clock enable circuit 606 and the stop control circuit 614. In some embodiments, the inverter may be included in the stop control circuit 614.

[0049] In response to any of the signal (Buf->Stop) from buffer model 612 and clock signals Ref0(1 / 4F), Ref0F(1 / 4F), Ref180(1 / 4F), and Ref180F(1 / 4F), stop control circuit 614 may provide a stop signal MeasStop with a coarse delay (e.g., coarse delay 318). Stop control circuit 614 may further provide a stop signal Stop0 in response to any of the signal (Buf->Stop) from buffer model 612 and clock signals Ref0(1 / 4F) and Ref0F(1 / 4F). Stop control circuit 614 may also provide a stop signal Stop180 in response to any of the signal (Buf->Stop) from buffer model 612 and clock signals Ref180(1 / 4F) and Ref180F(1 / 4F). Stop signals Stop0 and Stop180 may be provided to multi-cycle (N) detection circuit 616. In response to the activation of stop signals Stop0 and Stop180, the multi-cycle (N) detection circuit 616 can stop counting the number of cycles N of the internal clock signal ICLK, as shown in the reference. Figure 4 As described. The number of cycles N of the internal clock signal ICLK can be provided to several circuits for delay control.

[0050] In some embodiments, the stop control circuit 614 may include synchronizers 618, 620, 622, and 624. Synchronizers 618, 620, 622, and 624 may receive clock signals Ref0(1 / 4F), Ref0F(1 / 4F), Ref180(1 / 4F), and Ref180F(1 / 4F), respectively. The stop control circuit 614 may further include a synchronization detector circuit 636, which includes logic circuits 626, 628, and 634, as well as inverters 630 and 632. Synchronizers 618, 620, 622, and 624 may also receive a signal (Buf->Stop). Furthermore, when the multi-cycle N is odd, synchronizers 618 and 620 may receive a valid stop signal, and when the multi-cycle N is even, synchronizers 622 and 624 may receive a valid stop signal. When the multi-cycle N is even, synchronizer 618 can provide a first stop signal in response to the signal (Buf->Stop) and the clock signal Ref0(1 / 4F). When the multi-cycle N is even, synchronizer 620 can provide a second stop signal in response to the signal (Buf->Stop) and the clock signal Ref0F(1 / 4F). Logic circuit 626 (e.g., NAND logic) can receive the first and second stop signals and provide a complementary signal to the stop signal Stop0, which is inverted by inverter 630 and further inverted by another inverter coupled to the output node of inverter 630, and provided as the stop signal Stop0 to the multi-cycle (N) detection circuit 616. Similarly, when the multi-cycle N is odd, synchronizer 622 can provide a third stop signal in response to the signal (Buf->Stop) and the clock signal Ref180(1 / 4F). When the multi-cycle N is odd, synchronizer 624 can provide a fourth stop signal in response to the signal (Buf->Stop) and the clock signal Ref180F(1 / 4F). Logic circuit 628 (e.g., NAND logic) can receive the third and fourth stop signals and provide a complementary signal to the stop signal Stop180, which is inverted by inverter 632 and further inverted by another inverter coupled to the output node of inverter 632, and provided as the stop signal Stop180 to the multi-cycle (N) detection circuit 616. Logic circuit 634 (e.g., NOR logic) receives the complementary signals of stop signals Stop0 and Stop180 and provides an output signal. The output signal is further inverted by another inverter coupled to the output node of logic circuit 634 and provided as the stop signal MeasStop.

[0051] Figure 7This is a circuit diagram of a synchronizer 700 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, synchronizer 700 may be included in synchronizers 618, 620, 622, and 624. However, synchronizers 618, 620, 622, and 624 are not limited to synchronizer 700 and may be implemented in different ways. Synchronizer 700 may include a plurality of flip-flops 702a, 702b, and 702c coupled in series. In this example, the number of flip-flops may be three; however, the number of multiple flip-flops used in each synchronizer is not limited to three. The plurality of flip-flops 702a to 702c may receive a common reference clock signal RefX at their clock nodes. For example, the reference clock signal RefX may be any one of clock signals Ref0(1 / 4F), Ref0F(1 / 4F), Ref180(1 / 4F), and Ref180F(1 / 4F). Flip-flop 702a can receive a signal (Buf->Stop) at input node D from a buffer model (e.g., buffer model 328 or buffer model 612). Flip-flop 702a can provide the signal received at input node D as an output signal to output node Q in response to a common reference clock signal RefX. Flip-flop 702b can receive the output signal of flip-flop 702a at input node D and provide the received signal as an output signal to output node Q in response to the common reference clock signal RefX. Flip-flop 702c can receive the output signal of flip-flop 702b at input node D and provide the received signal as an output signal to output node Q in response to the common reference clock signal RefX. Therefore, synchronizer 700 can provide a signal (Buf->Stop) timed by the RefX signal.

[0052] Figure 8 This is a block diagram of a multi-cycle (N) detection circuit 800 according to embodiments of the present disclosure. In some embodiments of the present disclosure, the multi-cycle (N) detection circuit 800 may be included... Figure 3 Multi-cycle (N) detection circuit 332 or Figure 6The multi-cycle (N) detection circuit 616 is used. However, the multi-cycle (N) detection circuit 332 and the multi-cycle (N) detection circuit 616 are not limited to the multi-cycle (N) detection circuit 800 and can be implemented in different ways. The multi-cycle (N) detection circuit 800 may include a plurality of counters 802, 804, 806 and 808. Counters 802, 804, 806 and 808 may be implemented as binary counters. Alternatively, the counters may be implemented as shift registers. Counter 802 may receive a clock signal Ref0 (e.g., clock signal Ref0(1 / 4F)) and a stop signal (Stop0). Counter 802 may also receive a start signal that can be generated from the clock signal Ref0. Similarly, counter 804 may receive a clock signal Ref0F (e.g., clock signal Ref0F(1 / 4F)), a stop signal (Stop0) and another start signal that can be generated from the clock signal Ref0F. Counter 806 may receive a clock signal Ref180 (e.g., clock signal Ref180(1 / 4F)), another stop signal (Stop180), and another start signal that may be generated from the clock signal Ref180. Counter 808 may receive a clock signal Ref180F (e.g., clock signal Ref180F(1 / 4F)), another stop signal (Stop180), and another start signal that may be generated from the clock signal Ref180F. Each of counters 802, 804, 806, and 808 may begin counting the number of cycles in response to a corresponding start signal having a period timed by the corresponding clock signal (e.g., Ref0, Ref0F, Ref180, Ref180F), and stop counting the number of cycles in response to a corresponding stop signal.

[0053] The multi-cycle (N) detection circuit 800 may include an adder circuit 810. The adder circuit 810 may include sub-adders 812 and 814 and an adder 816. Sub-adder 812 may receive cycle numbers from counters 802 and 804 and provide an addition result. Sub-adder 814 may receive cycle numbers from counters 806 and 808 and provide an addition result. Adder 816 may receive the addition result from sub-adders 812 and 814 and provide the received addition result as the cycle number N, for example, the cycle number N used for delay control.

[0054] Figure 9 This is a circuit diagram of a binary counter 900 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the binary counter 900 may be included... Figure 8The counters 802, 804, 806, and 808 are used. A binary counter 900 includes logic circuitry 902, an enable circuit 904, a ripple counter 906, and a synchronizer delay copy 908. The binary counter 900 can receive a clock signal RefX. The clock signal RefX can be one of clock signals Ref0 and Ref180. In some embodiments, the synchronizer delay copy 908 can include a delay equal to the delays on synchronizers 618, 620, 622, and 624 and the latch. In some embodiments, the delay of the synchronizer delay copy 908 can be implemented by including a synchronizer 700 and a latch. The synchronizer delay copy 908 can receive the clock signal RefX, such that the clock signal RefX is delayed, and the latch can provide a start signal StartX in response to the delayed clock signal RefX. The enable circuit 904 can receive an inverted start signal StartX and a stop signal StopX. The stop signal StopX can be one of stop signals Stop0 and Stop180. The enable circuit 904 can provide an enable signal En in response to a start signal StartX and a stop signal StopX. For example, the enable signal En can have a rising edge in response to the rising edge of the start signal StartX and a falling edge in response to the falling edge of the inverted signal StopX. Therefore, the enable signal En can have an active state from the rising edge of the start signal StartX to the rising edge of the stop signal StopX.

[0055] Logic circuit 902 can also receive a clock signal RefX. Logic circuit 902 can further receive an enable signal En. In response to the clock signal RefX and the enable signal En, logic circuit 902 can provide a clock signal RefXD during the active state of the enable signal En.

[0056] The ripple counter 906 may include multiple flip-flops connected in series, wherein the flip-flops are represented in binary form as a binary code N<3-0> representing the number of cycles N. For example, the ripple counter 906 may contain a stored value N. <0> The first flip-flop that can receive the clock signal RefXD, and the storage N <1> A second flip-flop that can receive the output signal from the first flip-flop, and a storage N <2> A third flip-flop that can receive the output signal from the second flip-flop and store N <3> The third flip-flop can receive the output signal from the third flip-flop. Compared with the counter implemented as a shift register, except for the stored value N <0> Apart from the flip-flops, most flip-flops can change their values ​​over a period longer than the clock period of the clock signal RefXD, so the signal in the ripple counter 906 can be relatively stable.

[0057] Because it includes a synchronizer with a clock cycle longer than the internal clock signal, metastability in each synchronizer is prevented. Furthermore, metastability in the multi-cycle (N) detection circuit is prevented when it is designed to operate at a clock cycle longer than the internal clock signal. Additionally, the ripple counter in the multi-cycle (N) detection circuit also stabilizes the signal representing the number of cycles N. Therefore, despite the relatively high clock speed of the external clock signal, measurement initiation and / or multi-cycle (N) detection can be performed stably.

[0058] Although various embodiments of this disclosure have been disclosed, those skilled in the art will understand that the embodiments extend beyond the specific disclosed embodiments, extending to other alternative embodiments and / or uses, as well as their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. It has also been considered that various combinations or sub-combinations of certain features and aspects of the embodiments may be made and still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed embodiments. Therefore, the scope of at least some of this disclosure is not intended to be limited to the specific disclosed embodiments described above.

[0059] Based on the foregoing, it will be understood that although specific embodiments of this disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to any of the specific embodiments described herein.

Claims

1. An apparatus comprising: The delay stage includes: A clock enable circuit is configured to receive first and second clock signals having a first frequency, and configured to provide third and fourth clock signals having a second frequency, the second frequency being half of the first frequency. A delay, which is coupled to the clock enable circuit and configured to receive the third clock signal and provide the third clock signal with an adjustable delay as an output clock signal; A model delay circuit configured to receive the output clock signal and provide the output clock signal with a model delay as a feedback signal; as well as Measurement initialization circuit, which includes: A stop control circuit configured to provide a first stop signal to stop measurement initialization in response to the third and fourth clock signals and further in response to the feedback signal, the stop control circuit comprising: Multiple synchronizers are configured to receive the third and fourth clock signals and a complementary clock signal of the third and fourth clock signals, respectively, and are further configured to provide multiple second stop signals. The stop control circuit is configured to provide the first stop signal in response to the plurality of second stop signals.

2. The device of claim 1, wherein the second clock signal is delayed by one period of the internal clock signal from the first clock signal; and The fourth clock signal is delayed by one cycle from the third clock signal by the internal clock signal.

3. The device of claim 1, wherein each of the plurality of synchronizers comprises a series of triggers.

4. The device according to claim 1, wherein the plurality of synchronizers comprises: A first synchronizer is configured to receive the third clock signal; A second synchronizer is configured to receive a complementary signal to the third clock signal; A third synchronizer is configured to receive the fourth clock signal; A fourth synchronizer, configured to receive a complementary signal to the fourth clock signal.

5. The device of claim 4, wherein the measurement initialization circuit further includes a buffer model configured to enable the first and second synchronizers in response to the feedback signal and the third clock signal, and further configured to enable the third and fourth synchronizers in response to the feedback signal and the fourth clock signal.

6. The device of claim 5, wherein the buffer model is further configured to provide a default delay in response to the feedback signal.

7. The device of claim 6, wherein the measurement initialization circuit further comprises: A delayed clock measurement enable control circuit is configured to receive the feedback signal and further configured to provide a delayed clock measurement enable control signal to the buffer model in response to the feedback signal. The buffer model is further configured to provide a default delay amount in response to the delay clock measurement enable control signal.

8. The device of claim 7, wherein the delay clock measurement enable control circuitry is further configured to provide the delay clock measurement enable control signal to a coarse delay, and The coarse delay is configured to initiate the measurement initialization in response to the delay clock measurement enable control signal and is further configured to stop the measurement initialization in response to the first stop signal.

9. The device of claim 8, further comprising shift register circuitry configured to provide a variable delay amount during normal operation. The coarse delay is configured to store a first variable delay amount on the shift register circuit in response to the first stop signal during the measurement initialization.

10. An apparatus comprising: An input stage includes a frequency divider configured to receive an internal clock signal having a first frequency and further configured to provide first and second clock signals having a second frequency, the second frequency being half of the first frequency. The delay stage includes: A clock enable circuit is configured to receive the first and second clock signals from the frequency divider, configured to provide the first clock signal, and further configured to provide third and fourth clock signals having a third frequency, the third frequency being half of the second frequency. A coarse delay, coupled to the clock enable circuit and configured to receive the third clock signal and provide the third clock signal with an adjustable coarse delay as the first delayed clock signal; as well as A fine delay, coupled to the coarse delay, and configured to receive the first delayed clock signal and provide the first delayed clock signal with an adjustable fine delay as an output clock signal; A model delay circuit coupled to the delay stage and configured to receive the output clock signal and provide the output clock signal with the model delay as a feedback signal; as well as A measurement initialization circuit configured to perform measurement initialization using the coarse delay, the measurement initialization circuit comprising: A stop control circuit configured to provide first and second stop signals in response to the third and fourth clock signals and further in response to the feedback signal; as well as A detection circuit configured to receive the third and fourth clock signals and the first and second stop signals, configured to start detecting the number of cycles of the third frequency in response to the third and fourth clock signals, and further configured to stop detecting the number of cycles of the third frequency in response to the first stop signal or the second stop signal.

11. The device of claim 10, wherein the measurement initialization circuit further comprises a buffer model configured to provide a default delay amount in response to the feedback signal, and The stop control circuit includes: First and second synchronizers are configured to provide a first output signal in response to the feedback signal and the third clock signal; The third and fourth synchronizers are configured to provide a second output signal in response to the feedback signal and the fourth clock signal; and An adder circuit configured to receive the first output signal and provide the first stop signal in response to the first output signal, and further configured to receive the second output signal and provide the second stop signal in response to the second output signal.

12. The device of claim 10, wherein the detection circuit comprises a plurality of counters. Each of these counters is configured to receive: One of the third and fourth clock signals and the complementary signal of the third and fourth clock signals; A start signal in response to the received clock signal; and The first stop signal or the second stop signal is in response to the received clock signal.

13. The device of claim 12, wherein each of the plurality of counters is a binary counter.

14. The device of claim 12, wherein each of the plurality of counters is a shift register circuit.

15. A method comprising: Provide a first clock signal having a first frequency; The delay stage delays at least a portion of the clock signal based on the first clock signal to provide an output clock signal; The output clock signal is delayed by the model delay to provide a feedback signal; Provide third and fourth clock signals with a second frequency, the second frequency being half of the first frequency; and The feedback signal is received by the first, second, third, and fourth synchronizers; The first, second, third, and fourth synchronizers respectively receive the third and fourth clock signals and the complementary clock signal of the third and fourth clock signals; A plurality of first stop signals are provided by the first, second, third and fourth synchronizers in response to the feedback signal, the third and fourth clock signals and the complementary clock signal of the third and fourth clock signals; as well as In response to the plurality of first stop signals, a second stop signal is provided to the delay stage, the second stop signal indicating a halt to measurement initialization.

16. The method of claim 15, wherein providing the third and fourth clock signals comprises: The second clock signal is delayed by one cycle from the first clock signal; and The fourth clock signal is generated by dividing the second clock signal so that the fourth clock signal is delayed by one cycle from the third clock signal by the input clock signal.

17. The method of claim 15, further comprising providing a default delay in response to the feedback signal.

18. The method of claim 17, wherein providing the default delay comprises: The first and second synchronizers are activated in response to the feedback signal and the third clock signal; and The third and fourth synchronizers are activated in response to the feedback signal and the fourth clock signal.

19. The method of claim 18, further comprising: Receive the feedback signal; A delayed clock measurement enable control signal is provided in response to the feedback signal; and The default delay is provided in response to the delay clock measurement enable control signal.

20. The method of claim 19, further comprising: The delay clock measurement enable control signal is provided to the coarse delay; The measurement initialization is initiated by the coarse delay response to the delayed clock measurement enable control signal; and The measurement initialization is stopped in response to the second stop signal by the coarse delay.

21. The method of claim 15, further comprising: Receive the third and fourth clock signals and the plurality of first stop signals; The number of cycles of the second frequency is detected in response to the third and fourth clock signals; and The detection of the number of cycles of the second frequency is stopped in response to one of the plurality of first stop signals.

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