Semiconductor structure and method for forming the same

The dielectric fins and gate structures are formed through a self-aligned multiple patterning process, which solves the problems of semiconductor structure integration and spacing caused by the gate cut-off process in the existing technology, achieves smaller isolation openings and larger conductive structure design windows, and improves semiconductor performance.

CN116230636BActive Publication Date: 2025-09-19SEMICON MFG INT (SHANGHAI) CORP +1
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Patent Information

Application Number
CN202111470775.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-12-03
Publication Date
2025-09-19
Estimated Expiration
2041-12-03

AI Technical Summary

Technical Problem

In the prior art, semiconductor structures formed by gate cut-off processes have many problems, making it difficult to effectively improve integration and reduce gate spacing, resulting in a reduction in the design window of the conductive structure.

Method used

A self-aligned multi-patterning process is used to form sacrificial fins and device fins. An isolation opening is formed by removing the sacrificial fins, and a dielectric fin is formed in the isolation opening. The top surface of the dielectric fin is higher than the surface of the device fin. Subsequently, a gate structure is formed to cover the sidewalls of the dielectric fin.

Benefits of technology

It effectively reduces the width of the isolation opening, increases the spacing between gate structures, expands the conductive structure design window, and improves the integration and performance of the semiconductor structure.

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Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a base, a sacrificial fin, and a plurality of device fins, the substrate comprising an isolation region and a plurality of device regions, the plurality of device fins being located in the device region, and the sacrificial fin being located in the isolation region; forming an initial isolation layer on the substrate, the initial isolation layer covering the sidewalls of the device fins and the sacrificial fin; removing the sacrificial fins to form an isolation opening within the initial isolation layer; forming a dielectric fin within the isolation opening; and forming a gate structure, the gate structure spanning the plurality of device fins located on the device region, the gate structure exposing the top surface of the dielectric fin. Forming the isolation opening by removing the sacrificial fins reduces the spacing between the gate structures located on either side of the dielectric fin. When the spacing between the gate structures located on either side of the dielectric fin is reduced, the volume of the corresponding gate structure increases, thereby increasing the design window for subsequently forming a conductive structure on the gate structure.
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