Gate drive circuit and method
By automatically finding the critical voltage of the transistor and increasing the gate drive voltage, the problem of the inability to share drive circuits between gallium nitride devices and silicon devices is solved, simplifying the design and improving the versatility and efficiency of the drive circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2022-12-30
- Publication Date
- 2026-08-04
AI Technical Summary
In fast charging or switching power device scenarios, the drive circuits of gallium nitride devices and silicon devices cannot be shared, which requires the design of separate gate drive circuits, increasing design complexity.
A gate drive circuit and method are provided, which automatically finds the critical voltage of the transistor through a comparator, a counter and a driver, and increases the gate drive voltage based on this voltage to achieve the output of saturation voltage, thus avoiding the need for different drive circuits for different transistors.
It achieves automatic finding of critical voltage and output saturation voltage, simplifies drive circuit design, is applicable to enhancement-mode gallium nitride and silicon transistors, and improves the versatility and efficiency of drive circuits.
Smart Images
Figure CN116248098B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device technology, and in particular to a gate driving circuit and method. Background Technology
[0002] Compared with traditional silicon (Si) power electronic devices, gallium nitride (GaN) power electronic devices have superior characteristics such as higher switching frequency, high efficiency, high power, high voltage resistance, high temperature resistance and strong radiation resistance, so they can be quickly penetrated into 5G, radio frequency and fast charging scenarios.
[0003] Because gallium nitride (GaN) is a depletion-mode (D-mode) device, it requires a negative bias voltage to conduct. This poses no significant problem in 5G and radio frequency (RF) applications because second-generation semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), which are also depletion-mode devices, are commonly used in the design of power amplifiers (PAs) and low-noise amplifiers (LNAs). Therefore, GaN can be seamlessly integrated into 5G and RF applications. However, in scenarios such as fast charging or switching power devices, depletion-mode devices pose considerable challenges. This is because most fast charging or switching power devices are silicon devices, which are enhancement-mode devices and conduct using a positive bias voltage. Therefore, the widespread adoption of GaN devices in fast charging or switching power device scenarios faces certain difficulties.
[0004] Two solutions are presented in the relevant technologies:
[0005] 1. P-type gallium nitride layer (P-GaN layer). Enhancement-mode gallium nitride devices are achieved by combining physical structure with dry etching.
[0006] 2. Cascode. This method utilizes a circuit architecture combined with a low-voltage silicon device to achieve an enhanced structure.
[0007] When using enhancement-mode gallium nitride (GaN) devices, a gate driver circuit is used. This gate driver circuit can protect the device, enhance the signal, and reduce losses. However, this creates a problem: the driver circuits for the two types of GaN devices cannot be shared. The gate driver circuits for the P-type GaN layer and the device formed by stacking must be designed separately. Summary of the Invention
[0008] This disclosure provides a gate driving circuit and method that can automatically find the critical voltage and apply a corresponding gate driving voltage, avoiding the problem of designing different driving circuits for different transistors. The technical solution is as follows:
[0009] This disclosure provides a gate driving circuit, the gate driving circuit comprising:
[0010] A comparator is used to compare the drain current of a transistor with a reference current.
[0011] A counter is used to periodically acquire the result of the comparator, the result of which indicates whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, the counter is incremented by one; when the drain current exceeds the reference current, the counting stops.
[0012] A driver is used to provide a gate drive voltage to the transistor and periodically increase the gate drive voltage until the counter stops counting; a critical voltage corresponding to the count value of the counter when counting stops is determined, and the voltage value is increased based on the critical voltage to obtain a saturation voltage; the saturation voltage is used as the gate drive voltage.
[0013] Optionally, the period during which the driver controls the gate drive voltage to increase is the same as the period during which the counter counts.
[0014] Optionally, the counter is a 6-bit or 8-bit counter, and the driver controls the gate drive voltage to increase by 0.05V to 0.5V in each cycle.
[0015] Optionally, the transistor is an enhancement-grade gallium nitride transistor;
[0016] The driver is used to increase the critical voltage by 1V to 10V as the saturation voltage.
[0017] Optionally, the transistor is an enhancement-mode silicon transistor;
[0018] The driver is used to increase the critical voltage by 1V to 10V as the saturation voltage.
[0019] Optionally, the driver is configured to connect to a power supply voltage provider terminal, and to start outputting a gate drive voltage when the power supply voltage provided at the power supply voltage provider terminal reaches 80% of a predetermined value.
[0020] Optionally, the driver is configured to connect to a clock signal provider and periodically increase the gate drive voltage based on the clock signal.
[0021] Optionally, the reference current is 0.1 to 1 mA.
[0022] Optionally, the gate drive circuit further includes a current mirror connected between the transistor and the comparator;
[0023] The current mirror includes a first transistor and a second transistor. The source and drain of the first transistor are connected. The drain of the first transistor and the drain of the second transistor are connected to a device that was originally connected to the drain of the second transistor. The gate of the first transistor and the gate of the second transistor are connected. The source and the gate of the second transistor are connected. The drain of the second transistor is connected to one input terminal of the comparator.
[0024] This disclosure provides a gate driving method, the gate driving method comprising:
[0025] Compare the magnitudes of the transistor's drain current and reference current;
[0026] The comparison results are acquired periodically, and the comparison results are used to indicate whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, the count is incremented by one; when the drain current exceeds the reference current, the counting is stopped.
[0027] A gate drive voltage is provided to the transistor, and the gate drive voltage is periodically increased until the counter stops counting; a critical voltage corresponding to the count value of the counter when counting stops is determined, and the voltage value is increased based on the critical voltage to obtain a saturation voltage; the saturation voltage is used as the gate drive voltage.
[0028] Optionally, the period during which the driver controls the gate drive voltage to increase is the same as the period during which the counter counts.
[0029] Optionally, increasing the voltage value based on the critical voltage to obtain the saturation voltage includes:
[0030] The critical voltage is increased by 1V to 10V to be used as the saturation voltage.
[0031] The beneficial effects of the technical solutions provided in this disclosure include:
[0032] In the technical solution provided in this disclosure, a driver provides a gate drive voltage to the transistor and periodically increases the gate drive voltage. During this process, a comparator compares the drain current and a reference current, and the magnitude of the reference current is provided to a counter. The counter counts when the drain current does not exceed the reference current and stops counting when the drain current exceeds the reference current. The shift from the drain current exceeding the reference current indicates that the drive voltage has reached a critical voltage. The corresponding critical voltage is determined based on the count value at this point. Then, the voltage value is increased based on the critical voltage to obtain a saturation voltage, which is used as the gate drive voltage. This solution can automatically find the critical voltage and output the gate drive voltage, avoiding the problem of designing different drive circuits for different transistors. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure;
[0035] Figure 2 This is a connection diagram of a gate driving circuit provided in an embodiment of the present disclosure;
[0036] Figure 3 This is a schematic diagram of the structure of a comparator provided in an embodiment of this disclosure;
[0037] Figure 4 This is a waveform diagram of an 8-bit counter provided in an embodiment of this disclosure;
[0038] Figure 5 This is a timing diagram provided in an embodiment of the present disclosure;
[0039] Figure 6 This is a flowchart of a gate driving method provided in an embodiment of this disclosure. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0041] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the components or objects preceding “comprising” or “including” encompass the components or objects listed following “comprising” or “including” and their equivalents, and do not exclude other components or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0042] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure. The gate driving circuit includes a comparator 101, a counter 102, and a driver 103. The comparator 101 is electrically connected to the drain of the transistor to be driven and the counter 102, and the driver 103 is electrically connected to the gate of the transistor to be driven and the counter 102.
[0043] Comparator 101 is used to compare the magnitude of the transistor's drain current and the reference current;
[0044] Counter 102 is used to periodically acquire the result of the comparator, the result of which indicates whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, the count is incremented by one; when the drain current exceeds the reference current, the counting stops.
[0045] Driver 103 is used to provide a gate drive voltage to the transistor and periodically increase the gate drive voltage until the counter stops counting; determine the critical voltage corresponding to the count value of the counter when counting stops, and increase the voltage value based on the critical voltage to obtain a saturation voltage; use the saturation voltage as the gate drive voltage.
[0046] In the technical solution provided in this disclosure, a driver provides a gate drive voltage to the transistor and periodically increases the gate drive voltage. During this process, a comparator compares the drain current and a reference current, and the magnitude of the reference current is provided to a counter. The counter counts when the drain current does not exceed the reference current and stops counting when the drain current exceeds the reference current. The shift from the drain current exceeding the reference current indicates that the drive voltage has reached a critical voltage. The corresponding critical voltage is determined based on the count value at this point. Then, the voltage value is increased based on the critical voltage to obtain a saturation voltage, which is used as the gate drive voltage. This solution can automatically find the critical voltage and output the gate drive voltage, avoiding the problem of designing different drive circuits for different transistors.
[0047] Figure 2 This is a schematic diagram of the connection of a gate driving circuit provided in an embodiment of this disclosure. See also... Figure 2 In this embodiment of the disclosure, in order to obtain the drain current Ids output by the transistor without affecting the normal operation of the transistor, a current mirror needs to be set between the transistor and the comparator 101 to obtain the mirror current of the drain current Ids, and then use the mirror current for comparison.
[0048] See Figure 2 The current mirror consists of two transistors. The source and drain of the first transistor 104 are connected, the drain of the first transistor 104 is connected to the device that was originally connected to the drain of the second transistor 105, the gate of the first transistor 104 is connected to the gate of the second transistor 105, the source and gate of the second transistor 105 are connected, and the drain of the second transistor 105 is connected to one input terminal of the comparator 101.
[0049] In one possible implementation of this disclosure, the transistor is an enhancement-mode gallium nitride (GNU) transistor. For a P-type gallium nitride layer and an enhancement-mode gallium nitride device formed by stacking, their critical voltages (Vth) are not similar, thus requiring separate design of drive circuits in related technologies. This disclosure, however, achieves the driving of the enhancement-mode gallium nitride transistor by automatically finding the critical voltage and adding a saturation voltage based on it.
[0050] In other possible implementations of this disclosure, the transistor can also be an enhancement-mode silicon transistor. Since the solution of this disclosure automatically finds a critical voltage and then increases it to obtain a saturation voltage, it can naturally also drive the enhancement-mode silicon transistor.
[0051] It should be noted that for transistors made of different materials, the increase in voltage to obtain the saturation voltage from the critical voltage can be different.
[0052] Figure 3 This is a schematic diagram of a comparator provided in an embodiment of this disclosure. See also... Figure 3 (a) Comparator 101 is a current comparator. One input of comparator 101 is a self-defined reference current Iref, and the other input is connected to the drain of the transistor, and the input is the drain current Ids.
[0053] In one possible implementation of this disclosure, the reference current is 0.1 to 1 mA.
[0054] For example, the reference current is 0.1mA.
[0055] In one possible implementation of this disclosure, such as Figure 3 As shown in (b), when the drain current Ids does not exceed the reference current Iref, the comparator output is 0 (0V).
[0056] When the drain current Ids gradually increases and exceeds the reference current Iref, the comparator output output changes from 0 to 1 (greater than 0V); at this time, the gate drive voltage provided to the transistor represents the transistor's critical voltage.
[0057] Accordingly, counter 102 continues counting when it receives a comparator output of 0, and stops counting when it receives a comparator output of 1.
[0058] In another possible implementation of this disclosure, such as Figure 3 As shown in (c), when the drain current Ids does not exceed the reference current Iref, the comparator output is 1 (greater than 0V).
[0059] When the drain current Ids gradually increases and exceeds the reference current Iref, the comparator output output changes from 1 to 0 (0V); at this time, the gate drive voltage provided to the transistor represents the transistor's critical voltage.
[0060] Accordingly, counter 102 continues counting when it receives a comparator output of 1, and stops counting when it receives a comparator output of 0.
[0061] In one possible implementation of this disclosure, the counter 102 is a 6-bit or 8-bit counter, and the driver 103 increases the gate drive voltage by 0.05V to 0.5V in each cycle.
[0062] For example, the gate drive voltage is increased by 0.1V in each cycle.
[0063] For a 6-bit counter, the maximum value is 111111, which is 63 in decimal, and the maximum gate drive voltage that the driver can output is 6.3V.
[0064] For an 8-bit counter, the maximum value is 11111111, which is 255 in decimal, and the maximum gate drive voltage that the driver can output is 25.5V.
[0065] Figure 4 This is a waveform diagram of an 8-bit counter provided in an embodiment of this disclosure. See also... Figure 4 When all 8 bits of the 8-bit counter are low, the corresponding count value is 00000000, and the corresponding gate drive voltage is 0V.
[0066] When only the first bit of the 8 bits of the 8-bit counter is high, the corresponding count value is 00000001, and the corresponding gate drive voltage is 0.1V.
[0067] When only the second bit of the 8 bits of the 8-bit counter is high, the corresponding count value is 00000010, and the corresponding gate drive voltage is 0.2V.
[0068] When only the first and second bits of the 8-bit counter are high, the corresponding count value is 00000011, and the corresponding gate drive voltage is 0.3V.
[0069] Similarly, when all 8 bits of the 8-bit counter are high, the corresponding count value is 11111111, and the corresponding gate drive voltage is 25.5V.
[0070] The above implementation method can meet both the voltage driving requirements and the accuracy requirements for determining the critical voltage.
[0071] In other possible implementations of this disclosure, counter 102 may also have fewer or more bits, such as 4 bits or 10 bits. When using a 4-bit counter, the driver 103 increases the gate drive voltage by a larger amount each cycle, such as 0.3V.
[0072] In this embodiment of the disclosure, the driver 103 may be implemented using an integrated circuit or a chip.
[0073] For example, driver 103 determines whether to stop counting based on the waveform output by the counter. For instance, if the counter outputs the same waveform for N consecutive cycles, then it determines to stop counting. N can be 3 or other integers greater than 1.
[0074] For example, when the transistor is an enhancement-mode gallium nitride transistor, the driver 103 is used to increase the threshold voltage by 1V to 10V as the saturation voltage.
[0075] For example, when the transistor is an enhancement-mode gallium nitride transistor, the driver 103 is used to increase the threshold voltage by 5V as the saturation voltage.
[0076] For example, if driver 103 determines the critical voltage to be 5V, then the gate drive voltage output to the transistor will be 10V. This additional voltage is also adjustable, but generally, gallium nitride devices reach saturation operation at a voltage approximately 5V below the critical voltage.
[0077] For example, when the transistor is an enhancement-mode silicon transistor, the driver 103 is used to increase the threshold voltage by 1V to 10V as the saturation voltage.
[0078] Optionally, the driver 103 is configured to connect to a power supply voltage provider terminal, and to start outputting a gate drive voltage when the power supply voltage provided at the power supply voltage provider terminal reaches 80% of a predetermined value.
[0079] The predetermined value is the maximum power supply voltage.
[0080] Optionally, the driver 103 is configured to connect to a clock signal provider and periodically increase the gate drive voltage based on the clock signal.
[0081] Figure 5 This is a timing diagram provided in an embodiment of this disclosure. See also... Figure 5 The clock signal CLK serves as the clock for all devices in this circuit. When CLK rises, the power supply voltage VDD begins to increase. When VDD reaches 80%, the enable signal EN enables the circuit. The comparator compares Ids and Iref. While the comparator output is low, the counter continues counting. As the counter count increases, the gate drive voltage Vgate gradually increases from 0.1V to 5V. When Vgate reaches 5V, the comparator output goes high, and the counter stops counting. The driver adds 5V to Vgate, outputting a 10V Vgate, which is used to drive the transistors subsequently.
[0082] Figure 6 This is a flowchart illustrating a gate driving method provided in an embodiment of this disclosure. See also... Figure 6 The gate driving method includes:
[0083] 201: Compare the magnitude of the transistor's drain current and the reference current.
[0084] In one possible implementation of this disclosure, the transistor is an enhancement-mode gallium nitride (GNU) transistor. For a P-type gallium nitride layer and an enhancement-mode gallium nitride device formed by stacking, their critical voltages (Vth) are not similar, thus requiring separate design of drive circuits in related technologies. This disclosure, however, achieves the driving of the enhancement-mode gallium nitride transistor by automatically finding the critical voltage and adding a saturation voltage based on it.
[0085] In other possible implementations of this disclosure, the transistor can also be an enhancement-mode silicon transistor. Since the solution of this disclosure automatically finds a critical voltage and then increases it to obtain a saturation voltage, it can naturally also drive the enhancement-mode silicon transistor.
[0086] It should be noted that for transistors made of different materials, the increase in voltage to obtain the saturation voltage from the critical voltage can be different.
[0087] This step 201 is implemented using a comparator. The comparator is a current comparator, with one input being a user-defined reference current Iref, and the other input being connected to the drain of the transistor, where the drain current Ids is input.
[0088] For example, the reference current is 0.1 to 1 mA.
[0089] In one possible implementation of this disclosure, such as Figure 3 As shown in (b), when the drain current Ids does not exceed the reference current Iref, the comparator output is 0 (0V).
[0090] When the drain current Ids gradually increases and exceeds the reference current Iref, the comparator output output changes from 0 to 1 (greater than 0V); at this time, the gate drive voltage provided to the transistor represents the transistor's critical voltage.
[0091] Accordingly, counter 102 continues counting when it receives a comparator output of 0, and stops counting when it receives a comparator output of 1.
[0092] In another possible implementation of this disclosure, such as Figure 3 As shown in (c), when the drain current Ids does not exceed the reference current Iref, the comparator output is 1 (greater than 0V).
[0093] When the drain current Ids gradually increases and exceeds the reference current Iref, the comparator output output changes from 1 to 0 (0V); at this time, the gate drive voltage provided to the transistor represents the transistor's critical voltage.
[0094] Accordingly, counter 102 continues counting when it receives a comparator output of 1, and stops counting when it receives a comparator output of 0.
[0095] 202: Periodically acquire the comparison results, the comparison results being used to indicate whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, increment the count by one; when the drain current exceeds the reference current, stop counting.
[0096] Step 202 is implemented using a counter.
[0097] 203: Provide a gate drive voltage to the transistor and periodically increase the gate drive voltage until the counter stops counting; determine the critical voltage corresponding to the count value of the counter when counting stops, and increase the voltage value based on the critical voltage to obtain a saturation voltage; use the saturation voltage as the gate drive voltage.
[0098] Step 203 is implemented using a driver. The period during which the driver controls the gate drive voltage to increase is the same as the period during which the counter counts.
[0099] The counter is a 6-bit or 8-bit counter, and the driver controls the gate drive voltage to increase by 0.05V to 0.5V per cycle.
[0100] For a 6-bit counter, the maximum value is 111111, which is 63 in decimal, and the maximum gate drive voltage that the driver can output is 6.3V.
[0101] For an 8-bit counter, the maximum value is 11111111, which is 255 in decimal, and the maximum gate drive voltage that the driver can output is 25.5V.
[0102] Optionally, the driver is connected to a power supply voltage provider, and starts outputting a gate drive voltage when the power supply voltage provided at the power supply voltage provider reaches 80% of a predetermined value.
[0103] The predetermined value is the maximum power supply voltage.
[0104] Optionally, the driver is connected to a clock signal provider, and the gate drive voltage is periodically increased based on the clock signal.
[0105] In the technical solution provided in this disclosure, a driver provides a gate drive voltage to the transistor and periodically increases the gate drive voltage. During this process, a comparator compares the drain current and a reference current, and the magnitude of the reference current is provided to a counter. The counter counts when the drain current does not exceed the reference current and stops counting when the drain current exceeds the reference current. The shift from the drain current exceeding the reference current indicates that the drive voltage has reached a critical voltage. The corresponding critical voltage is determined based on the count value at this point. Then, the voltage value is increased based on the critical voltage to obtain a saturation voltage, which is used as the gate drive voltage. This solution can automatically find the critical voltage and output the gate drive voltage, avoiding the problem of designing different drive circuits for different transistors.
[0106] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A gate driving circuit, characterized in that, The gate driving circuit includes: A comparator is used to compare the magnitude of the drain current of the driving transistor with the reference current. A counter is used to periodically acquire the result of the comparator, the result of which indicates whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, the counter is incremented by one; when the drain current exceeds the reference current, the counting stops. A driver is used to provide a gate drive voltage to the driving transistor and periodically increase the gate drive voltage until the counter stops counting; a critical voltage corresponding to the count value of the counter when counting stops is determined, and the voltage value is increased based on the critical voltage to obtain a saturation voltage; the saturation voltage is used as the gate drive voltage.
2. The gate driving circuit according to claim 1, characterized in that, The period during which the driver controls the gate drive voltage to increase is the same as the period during which the counter counts.
3. The gate driving circuit according to claim 2, characterized in that, The counter is a 6-bit or 8-bit counter, and the driver controls the gate drive voltage to increase by 0.05V to 0.5V per cycle.
4. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The driving transistor is an enhancement-mode gallium nitride transistor or an enhancement-mode silicon transistor; The driver is used to increase the critical voltage by 1V to 10V as the saturation voltage.
5. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The driver is used to connect to the power supply voltage provider terminal, and starts to output the gate drive voltage when the power supply voltage provided by the power supply voltage provider terminal reaches 80% of a predetermined value.
6. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The driver is used to connect to a clock signal provider and periodically increase the gate drive voltage based on the clock signal.
7. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The reference current is 0.1~1mA.
8. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The gate drive circuit further includes a current mirror connected between the drive transistor and the comparator; The current mirror includes a first transistor and a second transistor. The source of the first transistor is connected to the drain of the driving transistor. The drain of the first transistor and the drain of the driving transistor are connected to a device that was originally connected. The gate of the first transistor is connected to the gate of the second transistor. The source of the second transistor is connected to the gate of the second transistor. The drain of the second transistor is connected to one input terminal of the comparator.
9. A gate driving method, characterized in that, The gate driving method includes: Compare the magnitudes of the drain current of the driving transistor and the reference current; The comparison results are acquired periodically, and the comparison results are used to indicate whether the drain current exceeds the reference current; when the drain current does not exceed the reference current, the count is incremented by one; when the drain current exceeds the reference current, the counting is stopped. A gate drive voltage is provided to the driving transistor, and the gate drive voltage is periodically increased until the counter stops counting; a critical voltage corresponding to the count value of the counter when counting stops is determined, and the voltage value is increased based on the critical voltage to obtain a saturation voltage; the saturation voltage is used as the gate drive voltage.
10. The gate driving method according to claim 9, characterized in that, The step of increasing the voltage value based on the critical voltage to obtain the saturation voltage includes: The critical voltage is increased by 1V to 10V to be used as the saturation voltage.