Transparent display device with touch sensor

Abstract

A transparent display device having a touch sensor that can minimize loss of light transmittance due to the touch sensor and the touch lines and can improve uniformity of parasitic capacitance between the touch lines is provided. The transparent display device includes a substrate provided with a transmissive area and a non-transmissive area, a touch sensor disposed in the transmissive area above the substrate and including a touch sensor electrode, pixels disposed in the non-transmissive area above the substrate and including a plurality of light emitting elements composed of an anode electrode, a light emitting layer, and a cathode electrode, a first signal line extending in a first direction from the non-transmissive area, a first touch line disposed between the first signal line and the transmissive area, and a second touch line disposed between the first touch line and the transmissive area. The first touch line has a first interval distance from the first signal line, the second touch line has a second interval distance from the first touch line, and the first interval distance can be greater than the second interval distance.

Description

Technical Field

[0001] This disclosure relates to a transparent display device having a touch sensor. Background Technology

[0002] Recently, research has been actively conducted on transparent display devices, in which users can view objects or images located on opposite sides of the display device. A transparent display device includes a display area on which an image is displayed, wherein the display area may include a transmissive region and a non-transmissive region capable of transmitting external light, and may have a high light transmittance through the transmissive region.

[0003] Transparent display devices can have multiple touch sensors and multiple touch lines to achieve touch functionality. However, the problem with transparent display devices is that the light transmittance may be reduced due to the multiple touch sensors and multiple touch lines, and the parasitic capacitance may increase due to the short spacing between the signal lines and touch lines. Summary of the Invention

[0004] This disclosure is made in view of the above-mentioned problems, and the purpose of this disclosure is to provide a transparent display device that can reduce or minimize light transmittance loss due to touch sensors and touch lines.

[0005] Another object of this disclosure is to provide a transparent display device that can improve the uniformity of parasitic capacitance between touch lines.

[0006] In addition to the purposes of this disclosure as stated above, other purposes and features of this disclosure will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a transparent display device with a touch sensor, the transparent display device comprising: a substrate having a transmissive region and a non-transmissive region; a touch sensor disposed in the transmissive region above the substrate and including touch sensor electrodes; a pixel disposed in the non-transmissive region on the substrate and including a plurality of light-emitting elements composed of an anode electrode, a light-emitting layer, and a cathode electrode; a first signal line extending from the non-transmissive region in a first direction; a first touch line disposed between the first signal line and the transmissive region; and a second touch line disposed between the first touch line and the transmissive region. The first touch line is configured to have a first spacing distance from the first signal line, the second touch line is configured to have a second spacing distance from the first touch line, and the first spacing distance is greater than the second spacing distance.

[0008] According to another aspect of this disclosure, the above and other objectives can be achieved by providing a transparent display device with a touch sensor, the transparent display device comprising: a substrate having a transmissive region and a non-transmissive region; a touch sensor disposed above the substrate in the transmissive region; a pixel disposed above the substrate in the non-transmissive region, the pixel comprising a plurality of light-emitting elements consisting of an anode electrode, a light-emitting layer, and a cathode electrode; a pixel power line extending from the non-transmissive region in a first direction to provide a first power supply to the anode electrode of each of the plurality of light-emitting elements; a first touch line and a second touch line disposed between the pixel power line and the transmissive region and extending in the first direction; and a scan line extending from the non-transmissive region in a second direction to provide a scan signal to each of the plurality of light-emitting elements. The first touch line and the second touch line have respective regions different from each other, the regions overlapping with at least a portion of the scan line. Attached Figure Description

[0009] The above and other objects, features and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic plan view showing a transparent display panel;

[0011] Figure 2 It shows the setting Figure 1 A schematic diagram illustrating an example of pixels in region A;

[0012] Figure 3 It shows the setting Figure 2 A diagram showing examples of signal lines, touch lines, and touch sensors in region B;

[0013] Figure 4 It is a diagram showing the connection relationships between multiple touch blocks and multiple touch lines;

[0014] Figure 5 This is a diagram showing the connection relationships between multiple touch lines and multiple touch sensors in a touch block;

[0015] Figure 6 It means Figure 3 A cross-sectional view of an example of the I-I' line;

[0016] Figure 7 This is a diagram illustrating an example of setting up a cathode electrode and a touch sensor electrode;

[0017] Figure 8 This is a diagram illustrating an example of recognizing a touch through one of multiple touch blocks;

[0018] Figure 9 This is a diagram showing the touch signal in the absence of parasitic capacitance and in the presence of touch signal and parasitic capacitance;

[0019] Figure 10 This is a graph showing the touch recognition rate based on the deviation of parasitic capacitance;

[0020] Figure 11 It is shown Figure 3 A magnified view of an example in region C;

[0021] Figure 12 yes Figure 11 A cross-sectional view of line II-II' (example);

[0022] Figure 13 It is shown Figure 11 A diagram of a variant example;

[0023] Figure 14 It is shown Figure 11 A cross-sectional view of another example of line II-II'; and

[0024] Figure 15 It means Figure 11 Cross-sectional views of other examples of line II-II'. Detailed Implementation

[0025] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0026] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals denote the same elements. In the following description, detailed descriptions that determine relevant known functions or configurations will be omitted where such descriptions unnecessarily obscure the essential points of this disclosure. Where the terms “comprising,” “having,” and “including” are used in this specification, another component may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0027] When interpreting an element, even without an explicit description, the element is interpreted as including a range of error.

[0028] When describing positional relationships, such as "on ~", "above ~", "below ~", and "adjacent to ~", one or more parts may be arranged between two other parts unless "only" or "directly" is used.

[0029] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] In describing the elements of this disclosure, the terms “first,” “second,” etc., may be used. These terms are intended to identify the corresponding element from other elements, and the basis, order, or number of the corresponding elements is not limited by these terms. The expression that an element is “connected” or “linked” to another element should be understood to mean that the element can be directly connected to or linked to another element, or, unless specifically mentioned, that a third element can be inserted between the corresponding elements.

[0031] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable and technically driven differently from each other. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0032] Figure 1 This is a schematic plan view showing a transparent display panel.

[0033] In the following text, the X-axis represents the line parallel to the scan line, the Y-axis represents the line parallel to the data line, and the Z-axis represents the height direction of the transparent display device 100.

[0034] Although the transparent display device 100 according to one embodiment of the present disclosure has been described as an organic light-emitting display device, the transparent display device 100 may be implemented as a liquid crystal display device, a plasma display panel (PDP), a quantum dot light-emitting display (QLED) or an electrophoretic display device.

[0035] Reference Figure 1 According to one embodiment of the present disclosure, a transparent display device includes a transparent display panel 110. The transparent display panel 110 may include a display area DA provided with pixels for displaying images, and a non-display area NDA for not displaying images.

[0036] The display area DA may have a first signal line SL1, a second signal line SL2, and pixels. The non-display area NDA may be provided with a pad area PA and at least one gate driver 205, wherein pads are provided in the pad area PA.

[0037] The first signal line SL1 may extend in a first direction (e.g., the Y-axis direction). The first signal line SL1 may intersect with the second signal line SL2 in the display area DA. The second signal line SL2 may extend in the display area DA in a second direction (e.g., the X-axis direction). Pixels may be disposed in the area where the first signal line SL1 is disposed or in the area where the first signal line SL1 and the second signal line SL2 intersect each other, and emit predetermined light or selected light to display an image.

[0038] Gate driver 205 is connected to scan lines and provides scan signals to scan lines. Gate driver 205 can be disposed in non-display area NDA on one or both sides of display area DA of transparent display panel 110 by means of in-panel gate driver (GIP) method or tape auto-bonding (TAB) method.

[0039] To enable touch functionality, in addition to the first signal line SL1, the second signal line SL2, and pixels, the transparent display panel 110 may also include touch lines and a touch sensor. Detailed descriptions of the touch lines and touch sensor will follow, along with a detailed description of the touch sensor.

[0040] Figure 2 It shows the setting Figure 1 A schematic diagram of an example of pixels in region A, and Figure 3 It shows the setting Figure 2 A diagram showing examples of signal lines, touch lines, and touch sensors in region B.

[0041] Reference Figure 2 and Figure 3 The display area DA includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA is the area through which most of the external incident light passes, and the non-transmissive area NTA is the area through which most of the external incident light cannot pass. For example, the transmissive area TA can be an area with a transmittance greater than α% (e.g., about 90%), and the non-transmissive area NTA can be an area with a transmittance less than β% (e.g., about 50%). In this case, α is greater than β. Due to the transmissive area TA, the user can view objects or backgrounds arranged on the rear surface of the transparent display panel 110.

[0042] The non-transmissive region NTA may include a first non-transmissive region NTA1, a second non-transmissive region NTA2, and a plurality of pixels P. Pixel P may be located in the first non-transmissive region NTA1, or in the overlapping area of ​​the first non-transmissive region NTA1 and the second non-transmissive region NTA2, and emits predetermined light or selected light to display an image. The emitting region EA may correspond to the area in pixel P from which light is emitted.

[0043] like Figure 2 As shown, each pixel P may include at least one of a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. The first sub-pixel SP1 may include a first emitting region EA1 that emits light of a first color. The second sub-pixel SP2 may include a second emitting region EA2 that emits light of a second color. The third sub-pixel SP3 may include a third emitting region EA3 that emits light of a third color. The fourth sub-pixel SP4 may include a fourth emitting region EA4 that emits light of a fourth color.

[0044] The first to fourth emitting regions EA1, EA2, EA3, and EA4 can emit different colors of light. For example, the first emitting region EA1 can emit green light. The second emitting region EA2 can emit red light. The third emitting region EA3 can emit blue light. The fourth emitting region EA4 can emit white light. However, the emitting regions are not limited to this example. Each pixel P can also include subpixels that emit light of colors other than red, green, blue, and white. Furthermore, the arrangement order of subpixels SP1, SP2, SP3, and SP4 can be changed in various ways.

[0045] The first non-transmissive region NTA1 can extend in the display region DA in the first direction (Y-axis direction) and can be configured to at least partially overlap the light-emitting regions EA1, EA2, EA3, and EA4. Multiple first non-transmissive regions NTA1 can be provided in the transparent display panel 110, and a transmissive region TA can be provided between two adjacent first non-transmissive regions NTA1. In the first non-transmissive region NTA1, the first signal line SL1 extending in the first direction (Y-axis direction) and the touch line TL extending in the first direction (Y-axis direction) can be configured to be spaced apart from each other.

[0046] For example, the first signal line SL1 may include at least one of the following: pixel power line VDDL, common power line VSSL, reference line REFL, and data lines DL1, DL2, DL3, and DL4.

[0047] The pixel power line VDDL can provide a first power supply to the driving transistor DTR in each of the sub-pixels SP1, SP2, SP3, and SP4 located in the display area DA. The first power supply can be an anode power supply.

[0048] The common power line VSSL can provide a second power supply to the cathode electrodes of sub-pixels SP1, SP2, SP3, and SP4 located in the display area DA. In this case, the second power supply can be a cathode power supply. The cathode power supply can be a common power supply provided to sub-pixels SP1, SP2, SP3, and SP4.

[0049] The common power line VSSL can supply cathode power to the cathode electrode through the cathode contact portion CCT. The cathode contact portion CCT can be disposed between the transmission region TA and the common power line VSSL. The power connection line VCL can be disposed between the common power line VSSL and the cathode contact portion CCT. One end of the power connection line VCL can be connected to the common power line VSSL through the first contact hole CH1, and the other end can be connected to the cathode contact portion CCT. The cathode electrode can be connected to the cathode contact portion CCT. As a result, the cathode electrode can be electrically connected to the common power line VSSL through the power connection line VCL and the cathode contact portion CCT.

[0050] The reference line REFL can provide an initialization voltage (or reference voltage) to the driving transistors DTR of each sub-pixel SP1, SP2, SP3, and SP4 located in the display area DA. The reference line REFL can be positioned between multiple data lines DL1, DL2, DL3, and DL4. For example, the reference line REFL can be positioned in the center of the multiple data lines DL1, DL2, DL3, and DL4, that is, between the second data line DL2 and the third data line DL3.

[0051] The reference line REFL can branch and connect to multiple sub-pixels SP1, SP2, SP3, and SP4. Specifically, the reference line REFL can be connected to the circuit elements of multiple sub-pixels SP1, SP2, SP3, and SP4 to provide an initialization voltage (or reference voltage) to each sub-pixel SP1, SP2, SP3, and SP4.

[0052] When the reference line REFL is positioned near the edge of the first non-transmissive region NTA1, the deviation between the connection lengths from the bifurcation point to the circuit elements of the plurality of sub-pixels SP1, SP2, SP3, and SP4 increases. In a transparent display panel 110 according to one embodiment of the present disclosure, the reference line REFL is positioned in the middle region of the first non-transmissive region NTA1, thereby reducing or minimizing the deviation between the connection lengths of each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 to the circuit elements. Therefore, the reference line REFL can uniformly provide signals to the circuit elements of the plurality of sub-pixels SP1, SP2, SP3, and SP4.

[0053] Each of the data lines DL1, DL2, DL3, and DL4 can provide a data voltage to sub-pixels SP1, SP2, SP3, and SP4. For example, the first data line DL1 can provide a first data voltage to the first driving transistor of the first sub-pixel SP1, the second data line DL2 can provide a second data voltage to the second driving transistor of the second sub-pixel SP2, the third data line DL3 can provide a third data voltage to the third driving transistor of the third sub-pixel SP3, and the fourth data line DL4 can provide a fourth data voltage to the fourth driving transistor of the fourth sub-pixel SP4.

[0054] In a transparent display panel 110 according to one embodiment of the present disclosure, touch lines TL may also be provided in a first non-transmissive region NTA1. At least two touch lines TL may be provided in a first non-transmissive region NTA1. When multiple touch lines TL are provided in the transmissive region TA of the transparent display panel 110, the light transmittance may be degraded due to the multiple touch lines TL.

[0055] Furthermore, slits (specifically, elongated linear or rectangular shapes) can be provided between multiple touch lines TL. When external light passes through the slits, diffraction may occur. According to diffraction, when light passes through the slits, light corresponding to a plane wave may become a spherical wave, and interference may occur in the spherical wave. Therefore, constructive and destructive interferences occur in the spherical wave, thus the external light passing through the slits may have irregular light intensities. As a result, in the transparent display panel 110, the sharpness of objects or images located on opposite sides may be reduced.

[0056] Therefore, multiple touch lines TL are preferably arranged in the first non-transmissive region NTA1, rather than in the transmissive region TA. However, in the transparent display panel 110, the size of the non-transmissive region NTA is much smaller than that of a typical display panel, and multiple signal lines, circuit elements, and light-emitting elements are formed in such a small area. Therefore, there are space constraints in the arrangement of the multiple touch lines TL in the non-transmissive region NTA, and problems may arise due to increased parasitic capacitance caused by the close proximity of the multiple touch lines and other signal lines.

[0057] According to one embodiment of the present disclosure, a transparent display panel 110 provides an arrangement structure that can reduce the average value of parasitic capacitance and improve the uniformity of parasitic capacitance when multiple touch lines TL are arranged in a non-transmissive region NTA. Reference will be made later. Figures 8 to 15 A detailed description of the arrangement structure of the touch line TL.

[0058] like Figure 3 As shown, multiple touch lines TL can be arranged between the first signal line SL1 in the first non-transmissive region NTA1 and the transmissive region TA. For example, six touch lines TL1, TL2, TL3, TL4, TL5, and TL6 can be arranged in one first non-transmissive region NTA1. Three of the six touch lines TL1, TL2, and TL3 can be arranged between the pixel power line VDDL and the transmissive region TA, and the other three touch lines TL4, TL5, and TL6 can be arranged between the common power line VSSL and the transmissive region TA, but are not limited to this arrangement. It is necessary to advantageously arrange the multiple touch lines TL so as not to overlap with the circuit regions CA1, CA2, CA3, and CA4 where circuit elements are arranged, and various modifications can be made to the arrangement order of the multiple touch lines TL and the first signal line SL1.

[0059] According to one embodiment of the present disclosure, a transparent display panel 110 includes pixels P between adjacent transmissive regions TA, and each pixel P may include light-emitting regions EA1, EA2, EA3, and EA4 in which light-emitting elements are disposed to emit light. Since the size of the non-transmissive region NTA in the transparent display panel 110 is small, the circuit elements can be configured to at least partially overlap with the light-emitting regions EA1, EA2, EA3, and EA4. That is, the light-emitting regions EA1, EA2, EA3, and EA4 may include circuit regions CA1, CA2, CA3, and CA4 in which circuit elements are disposed.

[0060] For example, the circuit region may include: a first circuit region CA1, wherein a circuit element connected to a first sub-pixel SP1 is provided; a second circuit region CA2, wherein a circuit element connected to a second sub-pixel SP2 is provided; a third circuit region CA3, wherein a circuit element connected to a third sub-pixel SP3 is provided; and a fourth circuit region CA4, wherein a circuit element connected to a fourth sub-pixel SP4 is provided.

[0061] In a transparent display panel 110 according to one embodiment of the present disclosure, multiple touch lines TL do not overlap with circuit regions CA1, CA2, CA3 and CA4, thereby reducing or minimizing the parasitic capacitance of the touch lines TL caused by circuit elements.

[0062] Furthermore, the transparent display panel 110 according to one embodiment of this disclosure can reduce the horizontal distance difference between touch lines TL. Since at least two transistors and one capacitor are disposed in circuit regions CA1, CA2, CA3, and CA4, it may be difficult for the touch lines TL to be formed as a straight line in the circuit regions CA1, CA2, CA3, and CA4, and it may be difficult to have a constant horizontal distance. Therefore, the horizontal distance difference between touch lines TL increases, thereby potentially resulting in very low uniformity of parasitic capacitance.

[0063] In a transparent display panel 110 according to one embodiment of the present disclosure, the touch line TL can be configured not to overlap with the circuit regions CA1, CA2, CA3 and CA4, thereby reducing the influence of circuit elements and simultaneously reducing the horizontal distance difference between the touch lines TL to improve the uniformity of parasitic capacitance.

[0064] The second non-transmissive region NTA2 may extend in the display region DA in a second direction (X-axis direction) and may be configured to at least partially overlap with the light-emitting regions EA1, EA2, EA3, and EA4. A plurality of second non-transmissive regions NTA2 may be provided in the transparent display panel 110, and a transmissive region TA may be provided between two adjacent second non-transmissive regions NTA2. The second signal line SL2 and the touch bridge line TBL may be configured to be spaced apart from each other in the second non-transmissive regions NTA2.

[0065] The second signal line SL2 may extend in a second direction (X-axis direction) and may include, for example, a scan line SCANL. The scan line SCANL may provide scan signals to the sub-pixels SP1, SP2, SP3, and SP4 of pixel P.

[0066] The touch bridge cable TBL can connect any one of multiple touch lines TL to a touch sensor TS. The touch bridge cable TBL can be connected to any one of the multiple touch lines TL via the second contact hole CH2. Furthermore, the touch bridge cable TBL can extend in the second direction (X-axis direction) and connect to at least two touch sensors TS extending in the second direction (X-axis direction).

[0067] In one embodiment, the touch bridge line TBL may include multiple layers (e.g., two layers). The touch bridge line TBL may include a first touch bridge line disposed in a first layer in a region overlapping with the first non-transmissive region NTA1, and a second touch bridge line disposed in a second layer in a region not overlapping with the first non-transmissive region NTA1. A first touch bridge line may be connected at one end to a second touch bridge line through a third contact hole CH3, and at the other end to another second touch bridge line through a fourth contact hole CH4. For example, the first layer may be the same layer as the gate electrode of the driving transistor, and the second layer may be the same layer as the source and drain electrodes of the driving transistor.

[0068] In a transparent display panel 110 according to one embodiment of the present disclosure, multiple touch lines TL can be provided in a first non-transmissive region NTA1 that is not a second non-transmissive region NTA2, thereby preventing the light transmittance from deteriorating due to the multiple touch lines TL. Figure 3 As shown, the second non-transmissive region NTA2, extending in the second direction (X-axis direction), intersects with adjacent transmissive regions TA. When the width of the second non-transmissive region NTA2, which intersects with the transmissive region TA, increases, the size of the transmissive region TA must decrease.

[0069] When multiple touch lines TL are set in the second non-transmissive area NTA2, the width of the second non-transmissive area NTA2 increases to accommodate a large number of lines, and the size of the transmissive area TA decreases. In other words, the light transmittance of the transparent display panel 110 may decrease due to the multiple touch lines TL.

[0070] In a transparent display panel 110 according to one embodiment of the present disclosure, multiple touch lines TL are disposed in a first non-transmissive region NTA1, and a single touch bridge line TBL for connecting multiple touch sensors TS is disposed in a second non-transmissive region NTA2. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can reduce or minimize the reduction in the size of the transmissive region TA or the reduction in light transmittance caused by the multiple touch lines TL and the touch bridge line TBL.

[0071] A touch sensor TS can be disposed in a transmission area TA. The touch sensor TS can be disposed in each of multiple transmission areas TA and its capacitance can change during user contact. A touch driver (not shown) can be connected to multiple touch sensors TS via multiple touch lines TL to detect changes in capacitance of the multiple touch sensors TS.

[0072] Each of a plurality of touch sensors TS can be connected to a touch bridge line TBL via a touch connection portion TC. The touch connection portion TC may overlap at least partially with the touch sensor TS at one end and at least partially with the touch bridge line TBL at the other end to facilitate connection between the touch sensor TS and the touch bridge line TBL. The touch connection portion TC may include a touch connection line TCL and a touch contact electrode TCT.

[0073] The touch connection cable (TCL) can connect the touch bridge cable (TBL) and the touch sensor (TS). Specifically, the touch connection cable (TCL) can be connected to the touch bridge cable (TBL) at one end and to the touch contact electrode (TCT) at the other end via a contact hole. The touch contact electrode (TCT) can be located in the transmissive area (TA) and can be connected to the touch sensor (TS). Therefore, the touch connection cable (TCL) can be connected to the touch sensor (TS) via the touch contact electrode (TCT).

[0074] In the following text, reference will be made to Figure 4 and Figure 5 This describes in more detail the connection relationships between multiple touch sensors (TS), multiple touch lines (TL), and multiple touch bridge lines (TBL).

[0075] Figure 4 It is a diagram showing the connection relationships between multiple touch blocks and multiple touch lines, and Figure 5 This is a diagram showing the connection relationships between multiple touch lines and multiple touch sensors in a touch block.

[0076] Reference Figures 4 to 5 According to one embodiment of this disclosure, the transparent display panel 110 may include a plurality of touch blocks TB. Each of the plurality of touch blocks TB may include a plurality of pixels P and a plurality of transmissive regions TA, wherein the plurality of transmissive regions TA, as basic units for determining the user's touch position, are configured to correspond one-to-one with the plurality of pixels P. For example, each of the plurality of touch blocks TB may include 12×15 pixels P and 12×15 touch sensors TS. In this case, when the image resolution is 1920×1080, the touch resolution may be 160×72.

[0077] In this case, the touch sensor TS may include a touch sensor electrode TSE. The touch sensor electrode TSE may comprise the same material in the same layer as the cathode electrode CE of the pixel P. In this configuration, the touch sensor electrode TSE and the cathode electrode CE may be spaced apart from each other.

[0078] In a transparent display panel 110 according to one embodiment of the present disclosure, when each of the plurality of touch lines TL is connected to one of the plurality of touch blocks TB, a change in capacitance of the touch sensor TS disposed in the connected touch block TB can be sensed. That is, the plurality of touch lines TL disposed in the transparent display panel 110 can correspond one-to-one with the plurality of touch blocks TB. Therefore, the number of touch lines TL can be the same as the number of touch blocks TB in the transparent display panel 110. For example, when the number of touch blocks TB is 160×72, the touch lines TL can also be 160×72, and can be connected to the touch driver TIC.

[0079] As described above, in order to form as many touch lines TL as there are touch blocks TB, at least two touch lines TL should be provided in a first non-transmissive area NTA1. For example, when the image resolution is 1920×1080 and the touch resolution is 160×72, such as Figure 3 As shown, six touch lines TL1, TL2, TL3, TL4, TL5 and TL6 can be provided in a first non-transparent area NTA1 to form 160×72 touch lines TL in the transparent display panel 110.

[0080] like Figure 5 As shown, multiple touch sensors TS disposed in a touch block TB can be connected to one of multiple touch lines TL disposed in the touch block TB. For example, twelve first non-transmissive regions NTA1 can be disposed in a touch block TB, and six touch lines TL1, TL2, TL3, TL4, TL5, and TL6 can be disposed in each of the twelve first non-transmissive regions NTA1. As a result, a touch block TB can have 72 touch lines TL1...TL72. In this case, the multiple touch sensors TS disposed in a touch block TB can be connected to a specific touch line TL among the 72 touch lines TL1...TL72. At this time, the specific touch line TL can be connected to the multiple touch sensors TS arranged in the second direction (X-axis direction) through a touch bridge line TBL extending in the second direction (X-axis direction). As a result, the multiple touch sensors TS disposed in a touch block TB can be electrically connected through the specific touch line TL and the touch bridge line TBL.

[0081] Each of the multiple touch lines TL can correspond one-to-one with a touch block TB. Therefore, multiple touch blocks TB are connected to different touch lines and are thus electrically isolated from each other. Each touch line TL can connect multiple touch sensors TS disposed in the corresponding touch block TB to the touch driver TIC. Specifically, each touch line TL can transmit a modified capacitance provided by the touch sensors TS disposed in the touch block TB to the touch driver TIC. The touch driver TIC can sense the modified capacitance and determine the user's touch position. Furthermore, each touch line TL can provide a sensing voltage generated from the touch driver TIC to the touch sensors TS disposed in the touch block TB.

[0082] In the following text, reference will be made to Figures 6 to 7 More specifically, the light-emitting element in the light-emitting area EA and the touch sensor TS in the transmission area TA are described.

[0083] Figure 6 It is shown Figure 3 A cross-sectional view of line I-I' as an example, and Figure 7 This is a diagram showing an example of setting up a cathode electrode and a touch sensor electrode.

[0084] Reference Figure 3 and Figures 6 to 7 The first non-transmissive region NTA1 includes circuit regions CA1, CA2, CA3, and CA4, in which at least one transistor and a capacitor are disposed, and power lines VSSL, reference lines REFL, data lines DL, and touch lines TL extending in a first direction (Y-axis direction) and configured not to overlap with circuit regions CA1, CA2, CA3, and CA4. The second non-transmissive region NTA2 may include scan lines SCANL and touch bridge lines TBL extending in a second direction (X-axis direction).

[0085] At least one transistor may include a drive transistor DTR and a switching transistor. The switching transistor may be switched according to a scan signal provided to the scan line SCANL to charge a capacitor with a data voltage provided from the data line DL, or to provide a reference voltage to the drive transistor DTR.

[0086] The driving transistor DTR is switched according to the data voltage charged in the capacitor to generate a data current from the power supplied by the pixel power line VDDL, and the data current is supplied to the first electrode 120 of sub-pixels SP1, SP2, SP3, and SP4. The driving transistor DTR may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0087] like Figure 6As shown, a light-shielding layer LS can be disposed above the first substrate 111. The light-shielding layer LS can be used to shield external light incident on the active layer ACT in the region where the driving transistor DTR is disposed. The light-shielding layer LS may comprise a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0088] According to one embodiment of the present disclosure, a transparent display panel 110 may form at least one of pixel power lines VDDL, common power lines VSSL, reference lines REFL, data lines DL, touch lines TL, scan lines SCANL, and touch bridge lines TBL in the same layer as the light shielding layer LS. For example, the scan line SCANL may include the same material as the light shielding layer LS and may be disposed in the same layer as the light shielding layer LS, but is not limited thereto.

[0089] A buffer layer BF can be disposed on the light shielding layer LS. The buffer layer BF is used to protect the transistor DTR from water penetration through the first substrate 111, and may include inorganic layers (e.g., silicon oxide layer (SiOx), silicon nitride layer (SiNx), or a multilayer of silicon oxide layer and silicon nitride layer).

[0090] An active layer ACT for driving the transistor DTR can be set on the buffer layer BF. The active layer ACT can include silicon-based semiconductor materials or oxide-based semiconductor materials.

[0091] A gate insulating layer GI can be disposed on the active layer ACT of the driving transistor DTR. The gate insulating layer G1 can be disposed in the non-transmissive region NTA and the transmissive region TA. However, in order to form a first undercut structure UC1 in the transmissive region TA, the gate insulating layer GI can be provided with a first opening region OA1, which is configured to expose the buffer layer BF without being disposed in at least a portion of the transmissive region TA. The gate insulating layer G1 may include inorganic layers (e.g., a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer of silicon oxide and silicon nitride layers).

[0092] The gate electrode GE of the driving transistor DTR can be disposed on the gate insulating layer GI. The gate electrode GE may comprise a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0093] An interlayer dielectric layer (ILD) can be provided on the gate electrode GE of the driving transistor DTR. The ILD can be disposed in the non-transmissive region NTA and the transmissive region TA. However, the ILD can have a first opening region OA1 that exposes the buffer layer BF and is not disposed in at least a portion of the transmissive region TA, to form a first undercut structure UC1 in the transmissive region TA. The ILD may include inorganic layers (e.g., a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer of silicon oxide and silicon nitride layers).

[0094] The source electrode SE and drain electrode DE of the driving transistor DTR can be formed on the interlayer dielectric layer ILD. The source electrode SE and drain electrode DE of the driving transistor DTR can be connected to the active layer ACT of the driving transistor DTR through the fifth contact hole CH5 passing through the gate insulating layer GI and the interlayer dielectric layer ILD. The source electrode SE and drain electrode DE of the driving transistor DTR can be made of a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0095] In a transparent display panel 110 according to one embodiment of the present disclosure, at least one of the pixel power line VDDL, common power line VSSL, reference line REFL, data line DL, touch line TL, scan line SCANL, and touch bridge line TBL can be disposed in the same layer as the source electrode SE and drain electrode DE of the driving transistor DTR. For example, the pixel power line VDDL, common power line VSSL, and data line DL can be disposed in the same layer as the source electrode SE and drain electrode DE, but are not limited thereto.

[0096] A first passivation layer PAS1 for insulating the driving transistor DTR can be disposed on the source electrode SE and drain electrode DE of the driving transistor DTR. A second passivation layer PAS2 can be disposed on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 can be disposed in the non-transmitting region NTA and the transmitting region TA. However, the first passivation layer PAS1 and the second passivation layer PAS2 can be provided with a first opening region OA1, which exposes the buffer layer BF without being disposed in at least a portion of the transmitting region TA, so as to form a first undercut structure UC1 in the transmitting region TA. The first opening region OA1 of the first passivation layer PAS1 and the second passivation layer PAS2 can overlap at least partially with the first opening region OA1 of the interlayer dielectric layer ILD and the first opening region OA1 of the gate insulating layer G1. The first passivation layer PAS1 and the second passivation layer PAS2 can include inorganic layers (e.g., silicon oxide layer (SiOx), silicon nitride layer (SiNx), or a multilayer of silicon oxide layer and silicon nitride layer).

[0097] A planarization layer PLN can be disposed on the second passivation layer PAS2 to flatten the step difference caused by the driving transistor DTR and multiple signal lines. The planarization layer PLN can be disposed in the non-transmissive region NTA, and may not be disposed in at least a portion of the transmissive region TA to form a first undercut structure UC1 in the transmissive region TA. The planarization layer PLN may include an organic layer (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin).

[0098] In a transparent display panel 110 according to one embodiment of the present disclosure, a first undercut structure UC1 can be formed using a planarization layer PLN and a plurality of inorganic insulating layers (e.g., a first passivation layer PAS1 and a second passivation layer PAS2, an interlayer dielectric layer ILD, and a gate insulating layer GI). Specifically, the first undercut structure UC1 can be formed such that the planarization layer PLN protrudes more than the plurality of inorganic insulating layers (e.g., the first passivation layer PAS1 and the second passivation layer PAS2, the interlayer dielectric layer ILD, and the gate insulating layer GI) in the direction of the transmission region TA. Therefore, the first undercut structure UC1 can expose at least a portion of the lower surface of the planarization layer PLN, and the plurality of inorganic insulating layers may not be disposed below the exposed lower surface, thereby providing a gap space with the buffer layer BF.

[0099] The first undercut structure UC1 can be formed by a wet etching process. Considering the characteristics, the wet etching process used to form the first undercut structure UC1 can be isotropic etching. Therefore, in the first undercut structure UC1, the first spacing distance d1 from the end of the planarization layer PLN to the ends of the plurality of inorganic insulating layers can be formed in the same manner as the second spacing distance d2 from the lower surface of the planarization layer PLN to the upper surface of the buffer layer BF. In this case, the first spacing distance d1 of the first undercut structure UC1 should have a minimum distance value or a selected distance value (e.g., 2 μm or greater) to ensure isolation between the cathode electrode CE and the touch sensor electrode TSE. Therefore, since the second spacing distance d2 of the first undercut structure UC1 should be greater than or equal to 2 μm, the sum of the thicknesses of the passivation layer PAS, the interlayer dielectric layer ILD, and the gate insulating layer GI can be 2 μm or greater.

[0100] The first undercut structure UC1 is disposed in the transmission region TA and may have a planar closed shape. For example, the first undercut structure UC1 may be disposed along the edge of the transmission region TA. In this case, the first undercut structure UC1 may be configured to surround the touch sensor TS.

[0101] In a transparent display panel 110 according to one embodiment of the present disclosure, a first undercut structure UC1 can be formed using a planarization layer PLN and a plurality of inorganic insulating layers, thereby preventing a reduction in light transmittance due to the first undercut structure UC1.

[0102] A light-emitting element comprising a first electrode 120, an organic light-emitting layer 130, a second electrode 140, and a dam 125 can be disposed on the planarization layer PLN.

[0103] A first electrode 120 can be provided on the planarization layer PLN for each sub-pixel SP1, SP2, SP3, and SP4. The first electrode 120 is not disposed in the transmission region TA. The first electrode 120 can be connected to the driving transistor DTR. Specifically, the first electrode 120 can be connected to one of the source electrode SE and drain electrode DE of the driving transistor DTR through contact holes (not shown) passing through the planarization layer PLN and the first passivation layer PAS1 and the second passivation layer PAS2.

[0104] The first electrode 120 may include a metallic material with high reflectivity (e.g., a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a laminated structure of Ag alloy and ITO (ITO / Ag alloy / ITO), a MOTi alloy, and a laminated structure of MOTi alloy and ITO (ITO / MOTi alloy / ITO)). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MOTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be the anode of the light-emitting element.

[0105] A dam 125 can be provided on the planarization layer PLN. The dam 125 can be provided to at least partially cover the edge of the first electrode 120 and expose a portion of the first electrode 120. Therefore, the dam 125 can prevent the luminous efficiency from deteriorating due to current concentration at the end of the first electrode 120.

[0106] The dam 125 can define the light-emitting regions EA1, EA2, EA3, and EA4 of sub-pixels SP1, SP2, SP3, and SP4. The light-emitting regions EA1, EA2, EA3, and EA4 of each sub-pixel SP1, SP2, SP3, and SP4 represent areas where the first electrode 120, the organic light-emitting layer 130, and the cathode electrode CE are sequentially stacked, and holes from the first electrode 120 and electrons from the cathode electrode CE combine with each other in the organic light-emitting layer 130 to emit light. In this case, the area where the dam 125 is provided can become a non-light-emitting region NEA because light is not emitted from it, and the area where the dam 125 is not provided and the first electrode is exposed can become a light-emitting region EA.

[0107] The embankment 125 may include an organic layer (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin).

[0108] An organic light-emitting layer 130 may be disposed on the first electrode 120. The organic light-emitting layer 130 may include a hole transport layer, a light-emitting layer, and an electron transport layer. In this case, when a voltage is applied to the first electrode 120 and the cathode electrode CE, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light.

[0109] In one embodiment, the organic light-emitting layer 130 may be a common layer disposed in sub-pixels SP1, SP2, SP3, and SP4. In this case, the light-emitting layer may be a white light-emitting layer for emitting white light.

[0110] In another embodiment, the light-emitting layer of the organic light-emitting layer 130 can be provided for each sub-pixel SP1, SP2, SP3, and SP4. For example, a green light-emitting layer for emitting green light can be provided in the first sub-pixel SP1, a red light-emitting layer for emitting red light can be provided in the second sub-pixel SP2, a blue light-emitting layer for emitting blue light can be provided in the third sub-pixel SP3, and a white light-emitting layer for emitting white light can be provided in the fourth sub-pixel SP4. In this case, the light-emitting layer of the organic light-emitting layer 130 is not provided in the transmission region TA.

[0111] The organic light-emitting layer 130 can be separated between the non-transmissive region NTA and the transmissive region TA via the first undercut structure UC1. Specifically, the organic light-emitting layer 130 can be separated by the first undercut structure UC1 into an organic light-emitting layer 131 disposed in the non-transmissive region NTA and an organic light-emitting layer 132 disposed in the transmissive region TA. That is, the organic light-emitting layer 131 disposed in the non-transmissive region NTA and the organic light-emitting layer 132 disposed in the transmissive region TA can be spaced apart from each other by the first undercut structure UC1.

[0112] The second electrode 140 can be disposed on the organic light-emitting layer 130 and the embankment 125. When the second electrode 140 is deposited on the entire surface, the second electrode 140 can be separated discontinuously between the non-transmissive region NTA and the transmissive region TA by the first undercut structure UC1. Specifically, the second electrode 140 can be separated by the first undercut structure UC1 into a second electrode CE disposed in the non-transmissive region NTA and a second electrode TSE disposed in the transmissive region TA.

[0113] In this configuration, the second electrode CE disposed in the non-transmissive region NTA can be a cathode electrode CE and is a component constituting the light-emitting element. The cathode electrode CE can be connected to the cathode contact portion CCT to receive power from the common power line VSSL. The cathode electrode CE can be a common layer disposed in sub-pixels SP1, SP2, SP3, and SP4 to apply the same voltage.

[0114] Furthermore, the second electrode TSE disposed in the transmission region TA is the touch sensor electrode TSE, and can be a component constituting the touch sensor TS. The touch sensor electrode TSE can be connected to the second touch contact electrode TCT2 to provide a change in capacitance to the touch line TL.

[0115] The second electrode 140, which includes the cathode electrode CE and the touch sensor electrode TSE, may include a transparent conductive material (TCO) such as ITO and IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 140 includes a semi-transmissive conductive material, the luminous efficiency can be improved through a microcavity.

[0116] An encapsulation layer 150 can be disposed on the light-emitting element and the touch sensor TS. The encapsulation layer 150 can be disposed on the cathode electrode CE and the touch sensor electrode TSE to at least partially cover the cathode electrode CE and the touch sensor electrode TSE. The encapsulation layer 150 is used to prevent oxygen or water from penetrating into the organic light-emitting layer 130, the cathode electrode CE, and the touch sensor electrode TSE. For this purpose, the encapsulation layer 150 may include at least one inorganic layer and at least one organic layer.

[0117] A color filter CF can be disposed on the encapsulation layer 150. The color filter CF can be disposed on a surface of the second substrate 112 facing the first substrate 111. In this case, the first substrate 111 with the encapsulation layer 150 and the second substrate 112 with the color filter CF can be bonded to each other by an adhesive layer 160. Here, the adhesive layer 160 can be an optically clear resin (OCR) layer or an optically clear adhesive (OCA) film.

[0118] Patterned color filters (CFs) can be set for each sub-pixel SP1, SP2, SP3, and SP4. Black matrices (BMs) can be positioned between the color filters (CFs). The black matrices (BMs) can be positioned between sub-pixels SP1, SP2, SP3, and SP4 to prevent color mixing between adjacent sub-pixels SP1, SP2, SP3, and SP4. Additionally, the black matrices (BMs) can prevent externally incident light from being reflected by multiple lines positioned between sub-pixels SP1, SP2, SP3, and SP4, such as scan lines (SCANL), pixel power lines (VDDL), common power lines (VSSL), reference lines (REFL), and data lines (DL).

[0119] In a transparent display panel 110 according to one embodiment of the present disclosure, the touch sensor electrode TSE of the touch sensor TS and the cathode electrode CE of the light-emitting element can be formed in the same layer using a first undercut structure UC1. In the transparent display panel 110 according to one embodiment of the present disclosure, the touch process is simplified, and a separate mask for the touch sensor electrode TSE is not required.

[0120] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, a first undercut structure UC1 can be formed using a planarization layer PLN and a plurality of inorganic insulating layers, thereby forming the first undercut structure UC1 without sacrificing light transmittance.

[0121] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, a touch line TL can be disposed below the light-emitting element, thereby preventing the light-emitting efficiency of pixel P from being degraded due to the touch line TL.

[0122] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the touch line TL can be configured not to overlap with the circuit regions CA1, CA2, CA3 and CA4, thereby minimizing or reducing the influence caused by circuit elements and improving the uniformity of parasitic capacitance.

[0123] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, multiple touch lines TL can be provided in a first non-transmissive region NTA1, and only one touch bridge line TBL for connecting multiple touch sensors TS can be provided in a second non-transmissive region NTA2, thereby minimizing or reducing the reduction in the size of the transmissive region TA or the reduction in light transmittance caused by the multiple touch lines TL and the touch bridge line TBL.

[0124] Furthermore, in a transparent display panel 110 according to one embodiment of this disclosure, in addition to the touch line TL, multiple first signal lines SL1 and second signal lines SL2 can be disposed in the non-transmissive region NTA. In this case, the first signal lines SL1 and second signal lines SL2 may affect the parasitic capacitance of the touch line TL. The parasitic capacitance between the touch line TL and the other signal lines SL1 and SL2 may affect the touch recognition rate. In the following, reference will be made to... Figures 8 to 10 The touch recognition rate is described by the deviation of the parasitic capacitance of multiple touch lines TL.

[0125] Figure 8 This is a diagram illustrating an example of recognizing a touch through one of multiple touch blocks. Figure 9 The diagram illustrates the touch signal in the absence of parasitic capacitance and the case with both touch signal and parasitic capacitance. Figure 10 This is a graph showing the touch recognition rate based on the deviation of parasitic capacitance.

[0126] like Figure 8 As shown, a transparent display panel 110 according to one embodiment of the present disclosure may include a plurality of touch blocks TB as basic units for determining the user's touch position. Each of the plurality of touch blocks TB may include a plurality of touch sensors TS and may be connected to one of a plurality of touch lines TL.

[0127] The touch line TL can provide touch sensing signals to the touch sensor TS located in the touch block TB. The touch sensing signal can be provided to the touch sensor TS via the touch line TL. At this time, when the touch sensing signal Touch signal_Cp input to the touch sensor TS passes through the touch line TL, such as... Figure 9 As shown, signal delay may occur due to the parasitic capacitance of the touch line TL.

[0128] The parasitic capacitance can vary depending on the location of the touch line TL. Since each of the multiple touch blocks TB is different from the connected touch line TL, the touch sensors TS, which are respectively located in the multiple touch blocks TB, can receive touch sensing signals with different signal delays.

[0129] For example, the touch line TL connected to each of the first to third touch blocks TB1, TB2, and TB3 can have a parasitic capacitance of a first value. The touch line TL connected to each of the fourth to sixth touch blocks TB4, TB5, and TB6 can have a parasitic capacitance of a second value greater than the first value. In this case, such as Figure 10 The touch sensing signal shown, Touch signal_Cp1, is input to the touch sensor TS located in each of the first to third touch blocks TB1, TB2, and TB3. This can be achieved by using, for example... Figure 10 The touch sensing signal shown, Touch signal_Cp2, is input to the touch sensor TS located in each of the fourth to sixth touch blocks TB4, TB5 and TB6.

[0130] Furthermore, the touch line TL transmits the capacitance of the touch sensor TS to the touch driver. The touch driver can sense changes in the capacitance of the touch sensor TS and determine the user's touch position. Specifically, the touch driver can sense changes in the capacitance of the touch sensor TS caused by the signal difference between the touch block TB2 where the touch occurred and the surrounding touch blocks TB1, TB3, TB4, TB5, and TB6.

[0131] The touch driver identifies a touch by comparing the capacitance signal of touch block TB2 with the capacitance signals of peripheral touch blocks TB4, TB5, and TB6. However, if there is a significant difference in parasitic capacitance between the touch line TL connected to touch block TB2 (where the touch occurred) and the touch lines TL connected to the peripheral touch blocks TB4, TB5, and TB6, the touch driver may have difficulty detecting or fail to detect the change in capacitance of touch block TB2, thus failing to recognize the touch. This can reduce the touch recognition rate.

[0132] For example, such as Figure 10 The touch sensing signal shown, Touch signal_Cp1, is input to the first to third touch blocks TB1, TB2, and TB3. When a user touches one of the first to third touch blocks TB1, TB2, and TB3, the current is reduced in the corresponding touch block TB2, thereby providing a current supply to the touch driver, such as... Figure 10 The image shows a capacitive touch signal related to touch.

[0133] Furthermore, due to the large parasitic capacitance of the touch line TL, signal delays may occur in touch blocks TB4, TB5, and TB6 located near touch block TB2 where touches occur, and so on. Figure 10 The touch sensing signal shown as Touch signal_Cp2 can be input to touch blocks TB4, TB5, and TB6. When no user touch occurs in the peripheral touch blocks TB4, TB5, and TB6, the peripheral touch blocks TB4, TB5, and TB6 may provide the touch driver with signals such as... Figure 10 The capacitance signal shown is Touch signal_Cp2.

[0134] Because the capacitance signal Touch signal on Touch of touch block TB2, where a touch occurs, is similar to the capacitance signal Touch Signal_Cp2 of the peripheral touch blocks TB4, TB5, and TB6, the touch driver cannot sense the change in capacitance of touch block TB2, where a touch occurs.

[0135] As described above, when the deviation of the parasitic capacitance of the touch line TL increases, the touch recognition rate may decrease, and the touch performance may also decrease. According to one embodiment of the present disclosure, the transparent display panel 110 adjusts the parasitic capacitance of the touch line TL to improve the uniformity of the parasitic capacitance.

[0136] Figure 11 This is an example Figure 3 An enlarged view of an example of region C. Figure 12 This is an example Figure 11 A cross-sectional view of line II-II'. Figure 13 This is an example Figure 11 Cross-sectional view of the deformed example, Figure 14 This is an example Figure 11 A cross-sectional view of another example of line II-II'. Figure 15 This is an example Figure 11 Cross-sectional views of other examples of line II-II'.

[0137] Reference Figure 3 and Figures 11 to 15Multiple touch lines TL can be positioned between the pixel power line VDDL and the transmissive area TA, or between the common power line VSSL and the transmissive area TA. For example, a portion of the multiple touch lines TL can be positioned between the pixel power line VDDL and the transmissive area TA, and another portion of the multiple touch lines TL can be positioned between the common power line VSSL and the transmissive area TA.

[0138] Multiple touch lines TL can be disposed between the first passivation layer PAS1 and the second passivation layer PAS2. In a transparent display panel 110 according to one embodiment of the present disclosure, multiple touch lines TL can be disposed between the first passivation layer PAS1 and the second passivation layer PAS2, thereby increasing the vertical distance from other signal lines.

[0139] Specifically, parasitic capacitance Cp can appear between multiple touch lines TL and other signal lines. For example, as Figure 12 As shown, multiple touch lines TL can generate a first parasitic capacitance Cp1 with signal lines (e.g., scan lines SCANL) disposed below and at least partially overlapping touch lines TL. Furthermore, multiple touch lines TL can generate a second parasitic capacitance Cp2 with signal lines (e.g., first electrode 120) disposed above and at least partially overlapping touch lines TL. Additionally, multiple touch lines TL can generate a third parasitic capacitance Cp3 with signal lines (e.g., pixel power lines VDDL or common power lines VSSL) configured to be adjacent to touch lines TL in the horizontal direction but not overlapping touch lines TL.

[0140] Multiple touch lines TL can be positioned between the first passivation layer PAS1 and the second passivation layer PAS2, thereby increasing the vertical distance to the scan line SCANL compared to the case where the touch lines are positioned below the first passivation layer PAS1. Therefore, the first parasitic capacitance Cp1 of the multiple touch lines TL can be reduced.

[0141] Additionally, when multiple touch lines TL are placed on the same layer as the pixel power line VDDL or the common power line VSSL, the vertical distance between them can be increased. This increases the spacing between the pixel power line VDDL and the common power line VSSL, thereby reducing the third parasitic capacitance Cp3 of the multiple touch lines TL.

[0142] Furthermore, the first parasitic capacitance Cp1 to the third parasitic capacitance Cp3 can vary depending on the location of the multiple touch lines TL, resulting in different parasitic capacitances Cp. More specifically, at least two touch lines TL1, TL2, and TL3 can be positioned between the pixel power line VDDL and the transmissive region TA. For example, the first touch line to the third touch line TL1, TL2, and TL3 can be positioned between the pixel power line VDDL and the transmissive region TA, but this is not a limitation. Two touch lines or four or more touch lines can be positioned between the pixel power line VDDL and the transmissive region TA.

[0143] Furthermore, at least two touch lines TL4, TL5, and TL6 may be positioned between the common power line VSSL and the transmission area TA. For example, the fourth to sixth touch lines TL4, TL5, and TL6 may be positioned between the common power line VSSL and the transmission area TA, but are not limited thereto. Two touch lines or four or more touch lines may be positioned between the common power line VSSL and the transmission area TA.

[0144] For ease of description, it is assumed that the first to third touch lines TL1, TL2, and TL3 are positioned between the pixel power line VDDL and the transmission region TA. Furthermore, although the description primarily focuses on the first to third touch lines TL1, TL2, and TL3 positioned between the pixel power line VDDL and the transmission region TA, this description can also be applied to the fourth to sixth touch lines TL4, TL5, and TL6. In this case, the description of the first touch line TL1 can be applied to the fourth touch line TL4, the description of the second touch line TL2 can be applied to the fifth touch line TL5, and the description of the third touch line TL3 can be applied to the sixth touch line TL6. In this case, the common power line VSSL can be used instead of the pixel power line VDDL.

[0145] The first to third touch lines TL1, TL2, and TL3 can differ from each other in the third parasitic capacitance Cp3. The first touch line TL1 can be positioned between the pixel power line VDDL and the transmission region TA, the second touch line TL2 can be positioned between the first touch line TL1 and the transmission region TA, and the third touch line TL3 can be positioned between the second touch line TL2 and the transmission region TA. That is, the first touch line TL1 can be positioned closest to the pixel power line VDDL, and the third touch line TL3 can be positioned furthest from the pixel power line VDDL. Therefore, the first touch line TL1 can generate a third parasitic capacitance Cp3 larger than each of the second touch lines TL2 and the third touch line TL3. On the other hand, the third touch line TL3 can generate a third parasitic capacitance Cp3 smaller than the parasitic capacitances of each of the first touch line TL1 and the second touch line TL2.

[0146] Furthermore, the first to third touch lines TL1, TL2, and TL3 can differ from each other in the second parasitic capacitance Cp2. The first touch line TL1 can be configured to be furthest from the transmission region TA and closest to the middle region of the first electrode 120. Since the parasitic capacitance Cp can also include both horizontal and vertical components, the first electrode 120 and the first touch line TL1 can have a wide region in which the second parasitic capacitance Cp2 is formed. On the other hand, the third touch line TL3 can be configured to be closest to the transmission region TA and closest to the end of the first electrode 120. Therefore, the first electrode 120 and the third touch line TL3 can have a small region in which the second parasitic capacitance Cp2 is formed. That is, the first touch line TL1 can generate a second parasitic capacitance Cp2 larger than each of the second touch lines TL2 and the third touch line TL3. On the other hand, the third touch line TL3 can generate a second parasitic capacitance Cp2 smaller than the parasitic capacitances of each of the first touch line TL1 and the second touch line TL2.

[0147] As a result, the first touch line TL1 has the largest parasitic capacitance Cp, while the third touch line TL3 can have the smallest parasitic capacitance Cp. Because the signal lines are positioned in a narrower space than typical display panels, the spacing between the signal lines and touch lines TL can be reduced, and their overlap area can be increased. Consequently, the parasitic capacitance Cp of the touch lines TL may increase, and its deviation may also increase.

[0148] To meet the touch performance requirements of the transparent display panel 110, the deviation of the parasitic capacitance Cp is preferably less than 7pF. However, when the first touch line to the third touch line TL1, TL2 and TL3 are set at the same distance between the pixel power line VDDL and the transmissive region TA, the first touch line to the third touch line TL1, TL2 and TL3 may have a deviation of nearly 20pF in parasitic capacitance Cp.

[0149] In a transparent display panel 110 according to one embodiment of the present disclosure, the spacing between the first touch line and the third touch lines TL1, TL2, and TL3 can be adjusted to reduce the deviation of the parasitic capacitance Cp. Specifically, the first touch line TL1 can be configured to have a first spacing distance d1 with the pixel power line VDDL, the second touch line TL2 can be configured to have a second spacing distance d2 with the first touch line TL1, and the third touch line TL3 can be configured to have a third spacing distance d3 with the second touch line TL2. In this case, the first spacing distance d1 can be greater than the second spacing distance d2. The third spacing distance d3 can be less than the second spacing distance d2 and the first spacing distance d1.

[0150] In a transparent display panel 110 according to one embodiment of the present disclosure, the first spacing distance d1 can be increased to reduce the second parasitic capacitance Cp2 and the third parasitic capacitance Cp3 of the first touch line TL1. Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the first spacing distance d1 can be increased, while the second spacing distance d2 and the third spacing distance d3 can be decreased, so that the distance between the pixel power line VDDL and the transmissive region TA does not need to be increased. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can reduce the parasitic capacitance Cp of the first touch line TL1 without reducing the transmittance.

[0151] Furthermore, the transparent display panel 110 according to one embodiment of this disclosure can reduce the deviation of parasitic capacitance Cp in the first touch line to the third touch lines TL1, TL2, and TL3. The first touch line TL1 can have its first spacing distance d1 from the pixel power line VDDL increased, thereby reducing the parasitic capacitance Cp. However, since the distance between the third touch line TL3 and the pixel power line VDDL is maintained, the parasitic capacitance Cp may remain unchanged. As a result, the deviation of parasitic capacitance Cp in the first touch line to the third touch lines TL1, TL2, and TL3 can be reduced, and the touch recognition rate of the transparent display panel 110 can be increased.

[0152] According to one embodiment of the present disclosure, the transparent display panel 110 can reduce the deviation of parasitic capacitance Cp by controlling the size of the area of ​​overlap between the first touch line to the third touch line TL1, TL2, and TL3 and the scan line. Specifically, the first touch line to the third touch line TL1, TL2, and TL3 can have different sizes of areas overlapping with the scan line SCANL. The first touch line TL1 can have a first area overlapping at least a portion of the scan line SCANL, the second touch line TL2 can have a second area overlapping at least a portion of the scan line SCANL, and the third touch line TL3 can have a third area overlapping at least a portion of the scan line SCANL. In this case, the second area and the third area can be smaller than the first area.

[0153] The second area of ​​the second touch line TL2 and the third area of ​​the third touch line TL3, which overlap with at least a portion of the scan line SCANL, can be increased, thereby increasing the first parasitic capacitance Cp1. Conversely, the first area of ​​the first touch line TL1, which overlaps with at least a portion of the scan line SCANL, can be maintained so that the first parasitic capacitance Cp1 remains unchanged. As a result, the deviation of the parasitic capacitance Cp from the first touch line to the third touch lines TL1, TL2, and TL3 can be reduced, and the touch recognition rate of the transparent display panel 110 can be increased.

[0154] In one implementation, such as Figure 11 As shown, the scan line SCANL may include a signal pattern SP having a first width W1 and a parasitic capacitance compensation pattern PCP having a second width W2. The second width W2 may be greater than the first width W1. The signal pattern SP may overlap with at least a portion of the first touch line TL1, and the parasitic capacitance compensation pattern PCP may overlap with at least a portion of the second touch line TL2 and the third touch line TL3. Therefore, the area of ​​the second touch line TL2 and the third touch line TL3 that overlap with at least a portion of the scan line SCANL may be larger than that of the first touch line TL1.

[0155] exist Figure 11 In this embodiment, the second touch line TL2 and the third touch line TL3 have areas of the same size that overlap with at least a portion of the scan line SCANL, but are not limited thereto. The second area of ​​the second touch line TL2 and the third area of ​​the third touch line TL3 overlapping at least a portion of the scan line SCANL can be different from each other, such as... Figure 13 As shown.

[0156] Specifically, such as Figure 13As shown, the scan line SCANL may include a signal pattern SP with a first width W1, a first parasitic capacitance compensation pattern PCP1 with a second width W2, and a second parasitic capacitance compensation pattern PCP2 with a third width W3. The third width W3 may be greater than the second width W2, and the second width W2 may be greater than the first width W1. The signal pattern SP may overlap with at least a portion of the first touch line TL1, and the first parasitic capacitance compensation pattern PCP1 may overlap with at least a portion of the second touch line TL2. The second parasitic capacitance compensation pattern PCP2 may overlap with at least a portion of the third touch line TL3. The area of ​​the third touch line TL3, which overlaps with at least a portion of the scan line SCANL, may be greater than that of the second touch line TL2 and the first touch line TL1. The second touch line TL2 may be greater than that of the first touch line TL1. Therefore, the third touch line TL3 may increase the first parasitic capacitance Cp1 to be greater than that of the second touch line TL2. The third touch line TL3 may have a second parasitic capacitance Cp2 and a third parasitic capacitance Cp3 smaller than those of the second touch line TL2 and the first touch line TL1. The area of ​​the second touch line TL2, which overlaps with at least a portion of the scan line SCANL, can be larger than that of the first touch line TL1. Therefore, the first parasitic capacitance Cp1 of the third touch line TL3 can be significantly increased compared to the first parasitic capacitance Cp1 of the second touch line TL2. In terms of the second parasitic capacitance Cp2 and the third parasitic capacitance Cp3, the third touch line TL3 can be smaller than both the second touch line TL2 and the first touch line TL1. Through the second parasitic capacitance compensation pattern PCP2, the first parasitic capacitance of the third touch line TL3 can be significantly increased compared to the first parasitic capacitance of the second touch line TL2, thereby reducing the variation in the parasitic capacitance Cp of the second touch line TL2 and the first touch line TL1.

[0157] In a transparent display panel 110 according to one embodiment of the present disclosure, the spacing between the first touch line and the third touch lines TL1, TL2, and TL3 can be adjusted, and the size of the area where the first touch line and the third touch lines TL1, TL2, and TL3 overlap with at least a portion of the scan line SCANL can be adjusted, thereby greatly reducing the deviation of the parasitic capacitance Cp. Regarding the second parasitic capacitance Cp2 and the third parasitic capacitance Cp3, the first touch line TL1 can be larger than the second touch line TL2 and the third touch line TL3. In a transparent display panel 110 according to one embodiment of the present disclosure, the first spacing distance d1 between the first touch line TL1 and the pixel power line VDDL can be increased, thereby increasing the second parasitic capacitance Cp2 and the third parasitic capacitance Cp3 of the first touch line TL1. As a result, the parasitic capacitance Cp of the first touch line TL1 can be reduced.

[0158] Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, the area of ​​overlap between the second touch line TL2 and the scan line SCANL can be increased, thereby increasing the first parasitic capacitance Cp1 of the second touch line TL2. Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, the area of ​​overlap between the third touch line TL3 and the scan line SCANL can be increased, thereby increasing the first parasitic capacitance Cp1 of the third touch line TL3.

[0159] Even if the spacing between the first touch line and the third touch lines TL1, TL2, and TL3 is adjusted, the first touch line TL1 can still have a second parasitic capacitance Cp2 and a third parasitic capacitance Cp3, which are greater than the parasitic capacitances of the second touch line TL2 and the third touch line TL3. In a transparent display panel 110 according to one embodiment of the present disclosure, the first parasitic capacitance Cp1 of the second touch line TL2 and the third touch line TL3 can be increased, thereby reducing the deviation of the parasitic capacitance Cp in the first touch line to the third touch line TL1, TL2, and TL3 to 7pF or less.

[0160] exist Figure 12 In this process, multiple touch lines TL are positioned between the first passivation layer PAS1 and the second passivation layer PAS2, but are not limited to this.

[0161] In another embodiment, multiple touch lines TL can be formed between the first substrate 111 and the passivation layer PAS. The multiple touch lines TL can be formed in the same layer as at least one other signal line. For example, the touch lines TL can be formed in the same layer as the source electrode SE and drain electrode DE of the driving transistor DTR, such as... Figure 14 As shown.

[0162] It is set Figure 14 The transparent display panel 110 with the touch line TL shown does not require a separate mask to form the touch line TL, and can eliminate the need for additional processes such as forming a second passivation layer PAS2. As a result, a transparent display panel 110 with the touch line TL shown does not require a separate mask to form the touch line TL, and can eliminate the need for additional processes such as forming a second passivation layer PAS2. Figure 14 The transparent display panel 110 of the touch line TL shown has a [feature / feature] that is consistent with [the previous one / the current]. Figure 12 Compared to the transparent display panel 110 with the touch line TL shown, mask costs can be reduced and the process can be simplified.

[0163] also, Figure 12 and Figure 14 This illustrates multiple touch lines (TL) set in the same layer, but is not limited to this.

[0164] In another implementation, the multiple touch lines TL can be arranged in different layers. A portion of the multiple touch lines TL can be arranged in a first layer, and another portion of the multiple touch lines TL can be arranged in a second layer. For example, as... Figure 15 As shown, a portion of the multiple touch lines TL can be disposed in the same layer as the source electrode SE and drain electrode DE of the driving transistor DTR, and another portion of the multiple touch lines TL can be disposed in the same layer as the light shielding layer LS. The first touch line TL1 and the third touch line TL3 can be disposed in the same layer as the source electrode SE and drain electrode DE of the driving transistor DTR, and the second touch line TL2 can be disposed in the same layer as the light shielding layer LS, but this disclosure is not limited thereto.

[0165] At this point, the touch lines TL set in the first layer and TL set in the second layer can be alternately set to increase the vertical distance vd between the touch lines TL. (Set with...) Figure 15 The transparent display panel 110 of the touch lines TL shown can reduce the horizontal distance hd between the touch lines TL as the vertical distance vd increases. Therefore, with the setting of Figure 12 and 14 Compared to the transparent display panel 110 of the touch line TL shown, it is provided with Figure 15 The transparent display panel 110 of the touch line TL shown can reduce the width of the first non-transmissive region NTA1 and increase the area of ​​the transmissive region TA, thereby improving the light transmittance.

[0166] The following advantages can be obtained according to this disclosure.

[0167] In this disclosure, an undercut structure can be used to simultaneously form the touch sensor electrode of the touch sensor and the cathode electrode of the light-emitting element, thereby simplifying the touch process and eliminating the need for a separate mask for the touch sensor electrode.

[0168] Furthermore, in this disclosure, the spacing between touch lines and between touch lines and other signal lines can be adjusted to reduce the deviation of parasitic capacitance between touch lines.

[0169] Furthermore, in this disclosure, the overlap area between the touch line and the signal line can be adjusted to reduce or minimize the deviation of parasitic capacitance between the touch lines, thereby further improving the uniformity of parasitic capacitance.

[0170] Furthermore, in this disclosure, the touch line can be configured to overlap with the pixel, thereby preventing the light transmittance from being degraded due to the touch line.

[0171] Furthermore, in this disclosure, the touch line can be configured not to overlap with the circuit area, thereby reducing or minimizing the influence of circuit elements on the touch line.

[0172] It will be apparent to those skilled in the art that this disclosure is not limited to the embodiments and drawings described above, and that various substitutions, modifications, and variations may be made in this disclosure without departing from its spirit or scope. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A transparent display device with a touch sensor, the transparent display device comprising: A substrate having a transmissive region and a non-transmissive region; A touch sensor, wherein the touch sensor is disposed in the transmissive region above the substrate, the touch sensor including touch sensor electrodes; A pixel is disposed in the non-transmissive region above the substrate, and the pixel includes a plurality of light-emitting elements, each of the plurality of light-emitting elements including an anode electrode, a light-emitting layer and a cathode electrode; A first signal line extends from the non-transmissive region in a first direction; A first touch line is disposed between the first signal line and the transmission area; A second touch line is disposed between the first touch line and the transmissive area; as well as A third touch line is disposed between the transmissive area and the second touch line. Wherein, the first touch line is configured to have a first interval distance from the first signal line, the second touch line is configured to have a second interval distance from the first touch line, and the first interval distance is greater than the second interval distance. The first touch line and the third touch line are disposed in the same layer as the source and drain electrodes of the driving transistor, and The second touch line is disposed in the same layer as the light shielding layer disposed between the substrate and the driving transistor.

2. The transparent display device according to claim 1, further comprising a plurality of driving transistors disposed in the non-transmissive region and respectively connected to the plurality of light-emitting elements. in, The first touch line and the second touch line do not overlap with the plurality of driving transistors.

3. The transparent display device according to claim 2, wherein, The first touch line and the second touch line are disposed in a layer between the plurality of driving transistors and the anode electrode.

4. The transparent display device according to claim 2, wherein, The first touch line and the second touch line are disposed in the same layer as the source electrode and drain electrode of the driving transistor.

5. The transparent display device according to claim 1, in, The third touch line is configured to have a third interval distance from the second touch line, and the third interval distance is smaller than the second interval distance.

6. The transparent display device according to claim 5, wherein, The first touch line and the third touch line are disposed in different layers from the second touch line.

7. The transparent display device according to claim 1, wherein, The first signal line includes a pixel power line that provides a first power supply to the anode electrode of each of the plurality of light-emitting elements.

8. The transparent display device according to claim 1, wherein, The first signal line includes a common power line that provides a second power supply to the cathode electrodes of the plurality of light-emitting elements.

9. The transparent display device of claim 1, further comprising a second signal line extending from the non-transparent region in a second direction to at least partially overlap with the first touch line and the second touch line. in, The second area where the second touch line and the second signal line overlap is larger than the first area where the first touch line and the second signal line overlap.

10. The transparent display device according to claim 9, wherein, The second signal line includes a signal pattern that overlaps with at least a portion of the first touch line and has a first width, and a parasitic capacitance compensation pattern that overlaps with at least a portion of the second touch line and has a second width greater than the first width.

11. The transparent display device according to claim 9, wherein, The second signal line is a scan line that provides a scan signal to each of the plurality of light-emitting elements.

12. The transparent display device according to claim 1, wherein, The cathode electrode and the touch sensor electrode are disposed in the same layer.

13. The transparent display device according to claim 12, further comprising a first undercut structure disposed in the transmissive region, the first undercut structure having a planar closed shape. in, The cathode electrode and the touch sensor electrode are separated from each other by the first undercut structure.

14. The transparent display device according to claim 1, wherein, It is equipped with multiple touch sensors and multiple pixels, and The plurality of touch sensors are configured to correspond one-to-one with the plurality of pixels.

15. A transparent display device having a touch sensor, the transparent display device comprising: A substrate having a transmissive region and a non-transmissive region; A touch sensor, wherein the touch sensor is disposed in the transmissive region above the substrate; A pixel is disposed in the non-transmissive region above the substrate, and the pixel includes a plurality of light-emitting elements, each of the plurality of light-emitting elements including an anode electrode, a light-emitting layer and a cathode electrode; A pixel power line extends from the non-transmissive region in a first direction and provides a first power supply to the anode electrode of each of the plurality of light-emitting elements. A first touch line and a second touch line are disposed between the pixel power line and the transmissive region and extend in the first direction; as well as A scan line, extending from the non-transmissive region in a second direction, provides a scan signal to each of the plurality of light-emitting elements. The area where the first touch line and the scan line overlap each other is different from the area where the second touch line and the scan line overlap each other.

16. The transparent display device according to claim 15, wherein, The scan line includes a signal pattern that overlaps with at least a portion of the first touch line and has a first width, and a parasitic capacitance compensation pattern that overlaps with at least a portion of the second touch line and has a second width greater than the first width.

17. The transparent display device according to claim 15, wherein, The first touch line is disposed between the second touch line and the pixel power line, and The first spacing between the first touch line and the pixel power line is different from the second spacing between the first touch line and the second touch line.

18. The transparent display device according to claim 17, wherein, The first interval distance is greater than the second interval distance.

19. The transparent display device according to claim 17, further comprising a third touch line disposed between the transmissive region and the second touch line. in, The third interval distance between the third touch line and the second touch line is different from the first interval distance.

20. The transparent display device according to claim 15, further comprising: A common power line extends from the non-transmissive region in the first direction, and the common power line provides a second power supply to the cathode electrode of the plurality of light-emitting elements; as well as A fourth touch line and a fifth touch line are disposed between the common power line and the transmission area. The area where the fourth touch line and the scan line overlap each other is different from the area where the fifth touch line and the scan line overlap each other.

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