Display panel, driving method thereof, and display device

Abstract

The application discloses a display panel, a driving method thereof and a display device. The display panel comprises a pixel circuit and a light emitting element. A driving module in the pixel circuit provides a driving current for the light emitting element in a light emitting stage. A bias adjustment module provides a bias adjustment signal for a driving transistor of the driving module in a bias adjustment stage. At least part of a non-light emitting stage of the display panel is a first non-light emitting stage. The first non-light emitting stage comprises the bias adjustment stage. In the same first non-light emitting stage, a time between a termination time of the bias adjustment stage and a termination time of the first non-light emitting stage is a bias maintenance stage. The brightness of the display panel in a first mode is different from the brightness in a second mode. At least one of the time length of the bias adjustment stage and the time length of the bias maintenance stage in the first mode and the second mode is different. According to the technical scheme of the application, the bias of the driving transistor can be adjusted according to different brightness modes, and the display uniformity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] A display panel usually has pixel circuits and light emitting elements, and a driving transistor in a pixel circuit can provide a driving current for a light emitting element according to a data signal received by the driving transistor, so as to drive the light emitting element to emit light, so that the display panel presents a corresponding display picture.

[0003] However, over time, the internal characteristics of the driving transistor in the pixel circuit change slowly, causing the threshold voltage of the driving transistor to drift, and the threshold drift of the driving transistor is different under different display brightness, thereby affecting the display uniformity of the display panel. SUMMARY

[0004] The present application provides a display panel, a driving method thereof and a display device, which adjusts the bias of the driving transistor in different degrees for different brightness modes, so as to improve the display uniformity of the display panel under different brightness modes.

[0005] According to an aspect of the present application, a display panel is provided, comprising:

[0006] a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a bias adjustment module;

[0007] the driving module is configured to provide a driving current for the light emitting element in a light emitting stage; the driving module comprises a driving transistor;

[0008] the bias adjustment module is configured to provide a bias adjustment signal for the source and / or drain of the driving transistor in a bias adjustment stage;

[0009] a frame time of the display panel comprises at least one light emitting stage and at least one non-light emitting stage; at least part of the non-light emitting stage is a first non-light emitting stage;

[0010] the first non-light emitting stage comprises the bias adjustment stage; in the same first non-light emitting stage, the time between the end time of the bias adjustment stage and the end time of the first non-light emitting stage is a bias maintenance stage;

[0011] the working module of the display panel comprises a first mode and a second mode; the brightness of the display panel in the first mode is different from the brightness of the display panel in the second mode;

[0012] At least one of a time length of the bias adjustment phase and a time length of the bias maintaining phase in the first mode is different from that in the second mode.

[0013] According to another aspect of the present application, a driving method of a display panel is provided, the display panel comprising a pixel circuit and a light emitting element; the pixel circuit comprising a driving module and a bias adjustment module; the driving module being configured to provide a driving current for the light emitting element in a light emitting phase; the driving module comprising a driving transistor; the bias adjustment module being configured to provide a bias adjustment signal for a source and / or a drain of the driving transistor in a bias adjustment phase; a frame time of the display panel comprising at least one light emitting phase and at least one non-light emitting phase; at least part of the non-light emitting phase being a first non-light emitting phase; the first non-light emitting phase comprising the bias adjustment phase; in the same first non-light emitting phase, a time between a termination time of the bias adjustment phase and a termination time of the first non-light emitting phase being a bias maintaining phase; the driving method of the display panel comprising:

[0014] acquiring a display mode of the display panel; the display mode comprising at least a first mode and a second mode with different brightnesses;

[0015] determining a time length of the bias adjustment phase and a time length of the bias maintaining phase according to the display mode; wherein at least one of the time length of the bias adjustment phase and the time length of the bias maintaining phase is different when the display mode of the display panel is the first mode and when the display mode of the display panel is the second mode;

[0016] controlling a time when the bias adjustment module provides the bias adjustment signal to the source and / or the drain of the driving transistor according to the time length of the bias adjustment phase and the time length of the bias maintaining phase.

[0017] According to still another aspect of the present application, a display device is provided, comprising the above display panel.

[0018] The technical scheme of the embodiment of the present application is characterized in that the first non-light-emitting stage of the non-light-emitting stage comprises a bias adjustment stage and a bias maintaining stage, and in the bias adjustment stage and the bias maintaining stage, the voltage difference between the source and / or the drain of the driving transistor and the gate thereof is the voltage difference between the bias adjustment signal and the gate thereof, which is different from the voltage difference between the source and / or the drain of the driving transistor and the gate thereof in the light-emitting stage, so that the bias adjustment of the driving transistor is realized in the bias adjustment stage and the bias maintaining stage, and the situation that the threshold voltage drifts due to the long-time unchanged voltage difference between the source and / or the drain of the driving transistor and the gate thereof is improved. Meanwhile, when the display panel is in different modes, the display panel presents different display brightness, and when the display panel presents different display brightness, the gate voltage of the driving transistor is different, at this time, by controlling at least one of the bias adjustment stage and the bias position stage in different brightness modes to be different, the source and / or the drain of the driving transistor can be kept for different time of the bias adjustment signal, so as to adjust the bias state of the driving transistor in each brightness mode, thereby ensuring the display uniformity in different brightness modes. In addition, by controlling at least one of the bias adjustment stage and / or the bias maintaining stage in different brightness modes to be different, under the premise of adjusting the bias state of the driving transistor in each brightness mode, the bias adjustment signal provided by the driving chip does not need to be changed, so that the additional power consumption caused by the repeated charging and discharging of the circuit, signal line and the like due to the change of the bias adjustment signal can be reduced, thereby ensuring the display effect of the display panel under the premise of improving the display uniformity of the display panel.

[0019] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 2 is a structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0023] Figure 3is another structural schematic view of a pixel circuit in a display panel provided by an embodiment of the present application;

[0024] Figure 4 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0025] Figure 5 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0026] Figure 6 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0027] Figure 7 is a top view structural schematic view of another display panel provided by an embodiment of the present application;

[0028] Figure 8 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0029] Figure 9 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0030] Figure 10 is another structural schematic view of a pixel circuit in a display panel provided by an embodiment of the present application;

[0031] Figure 11 is another structural schematic view of a pixel circuit in a display panel provided by an embodiment of the present application;

[0032] Figure 12 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0033] Figure 13 is another structural schematic view of a pixel circuit in a display panel provided by an embodiment of the present application;

[0034] Figure 14 is another structural schematic view of a pixel circuit in a display panel provided by an embodiment of the present application;

[0035] Figure 15 is a working timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0036] Figure 16 is a relationship curve schematic view of a display panel's brightness and bias maintaining stage provided by an embodiment of the present application;

[0037] Figure 17 is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0038] Figure 18 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0039] Figure 19 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0040] Figure 20 is a flowchart of a driving method of a display panel provided by an embodiment of the present application;

[0041] Figure 21 is a flowchart of a method for determining the length of a bias maintaining stage provided by an embodiment of the present application;

[0042] Figure 22 is a flowchart of another method for determining the length of a bias maintaining stage provided by an embodiment of the present application;

[0043] Figure 23 is a structural diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative work should fall within the scope of protection of the present application.

[0045] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0046] The self-luminous display panel includes a pixel circuit and a light emitting element, the pixel circuit includes a driving transistor, by providing a data signal to the gate of the driving transistor, so that the driving transistor converts the data signal into a driving current to drive the light emitting element to emit light. However, when the driving transistor is turned on, for PMOS type transistor, there may be a case that the gate potential is higher than the drain potential, for NMOS type transistor, there may be a case that the gate potential is lower than the drain potential, if the state is kept for a long time, the ion polarization in the driving transistor, and then the built-in electric field is formed in the driving transistor, which causes the threshold voltage of the driving transistor to drift, so that the driving transistor is biased, thereby affecting the stability of the driving current provided by the driving transistor, and then affecting the light emitting stability of the light emitting element.

[0047] In addition, when the display panel presents different display brightness, the data signal provided to the driving transistor is different, or the light emitting duration of the light emitting element is different, which causes the biasing of the driving transistor to be different, that is, the threshold voltage drift of the driving transistor is different, thereby affecting the display uniformity of the display panel under different display brightness, and further affecting the display effect of the display panel.

[0048] To solve the above technical problems, the first non-light emitting stage of the embodiment includes a bias adjustment stage and a bias maintaining stage, and in the bias adjustment stage and the bias maintaining stage, the voltage difference between the source and / or drain of the driving transistor and the gate thereof is the voltage difference between the bias adjustment signal and the gate thereof, which is different from the voltage difference between the source and / or drain of the driving transistor and the gate thereof in the light emitting stage, so that in the bias adjustment stage and the bias maintaining stage, the bias adjustment of the driving transistor is realized, and the case that the threshold voltage drifts due to the long-time unchanged voltage difference between the source and / or drain of the driving transistor and the gate thereof is improved. At the same time, when the display panel is in different modes, the display panel presents different display brightness, and when the display panel presents different display brightness, the gate voltage of the driving transistor is different. At this time, by controlling at least one of the bias adjustment stage and the bias maintaining stage in different brightness modes to be different, the time for keeping the source and / or drain of the driving transistor as the bias adjustment signal is different, so as to adjust the bias state of the driving transistor in each brightness mode, thereby ensuring the display uniformity in different brightness modes. In addition, by controlling at least one of the bias adjustment stage and / or the bias maintaining stage in different brightness modes to be different, under the premise of adjusting the bias state of the driving transistor in each brightness mode, the bias adjustment signal provided by the driving chip does not need to be changed, thereby reducing the additional power consumption caused by the repeated charging and discharging of the circuit, signal line, etc. due to the change of the bias adjustment signal, and further ensuring the display effect of the display panel under the premise of improving the display uniformity of the display panel.

[0049] The above is the core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application.

[0050] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 is a structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application, in combination with reference Figure 1 and Figure 2 The display panel 10 includes a pixel circuit 100 and a light emitting element 200, the pixel circuit 100 includes a driving module 11 and a bias adjustment module 12; the driving module 11 is configured to provide a driving current for the light emitting element 200 in a light emitting stage, and the driving module includes a driving transistor M1; the bias adjustment module 12 is configured to provide a bias adjustment signal for the source and / or drain of the driving transistor M1 in a bias adjustment stage; wherein one frame time of the display panel 10 includes at least one light emitting stage and at least one non-light emitting stage; at least part of the non-light emitting stage is a first non-light emitting stage; the first non-light emitting stage includes the bias adjustment stage; in the same first non-light emitting stage, the time between the end time of the bias adjustment stage and the end time of the first non-light emitting stage is a bias maintenance stage; the working module of the display panel 10 includes a first mode and a second mode; the brightness of the display panel 10 in the first mode is different from the brightness of the display panel in the second mode; at least one of the time length of the bias adjustment stage and the time length of the bias maintenance stage in the first mode is different from that in the second mode.

[0051] In the display panel 10, the pixel circuits 100 can be arranged in an array, and the light emitting elements 200 corresponding to the pixel circuits 100 are electrically connected, respectively. By providing data signals to each pixel circuit 100, the driving module 11 in the pixel circuit 100 can provide a driving current for the light emitting element 200 in a light emitting stage to drive the display light emitting of the light emitting element 200, so that the display panel 10 can present a corresponding display picture.

[0052] Since the light emitting element 200 is generally a current-driven element, and the data signal received by the pixel circuit 100 is generally a voltage signal, the data signal received by the pixel circuit 100 is written to the gate of the driving transistor M1 by providing the driving transistor M1 in the driving module 11, and in the light emitting stage, the driving transistor M1 generates a corresponding driving current according to the voltage difference between the gate potential and the positive power signal PVDD, and the threshold voltage of the driving transistor M1, and provides the driving current to the light emitting element 200, and drives the light emitting element 200 to emit light with a corresponding brightness. At this time, one of the source and drain of the driving transistor M1 can be coupled to the positive power signal end, and the other can be coupled to the anode of the light emitting element 200, and the cathode of the light emitting element 200 can be electrically connected to the negative power signal end, so that in the light emitting stage, a current path is formed between the positive power signal PVDD of the positive power signal end and the negative power signal PVEE of the negative power signal end, so that the driving transistor M1 can generate a driving current and provide the driving current to the light emitting element 200 to drive the light emitting element 200 to emit light.

[0053] It can be understood that the active layer material of the driving transistor M1 in the driving module 11 can include low-temperature polysilicon material, so that it has a higher carrier mobility, thereby meeting the requirements of high response speed and low power consumption, and the like. At this time, the driving transistor M1 can be a PMOS transistor. In other alternative embodiments, the active layer material of the driving transistor M1 can also include oxide semiconductor material, and at this time, the driving transistor M1 can be an NMOS transistor. The material and type of the driving transistor M1 are not specifically limited in the embodiments of the present application as long as the core inventive point of the embodiments of the present application can be achieved.

[0054] It should be noted that the source and drain of the transistor are not constant, but will change with the state of the transistor. Figure 2 The driving transistor M1 is only exemplarily shown as a PMOS transistor, and at this time, the drain of the driving transistor M1 is coupled to the light emitting element 200, and for the PMOS driving transistor M1, the driving current I generated by the driving transistor M1 is positively correlated with k(PVDD-Vdata) 2 The positive correlation, and the positive power signal PVDD is generally a constant value, when PVDD is constant greater than Vdata, the smaller Vdata is, the greater the driving current I is, and the greater the display light emitting brightness of the light emitting element 200 is.

[0055] In other alternative embodiments, Figure 3 is another structure diagram of a pixel circuit in a display panel provided by the embodiments of the present application, as Figure 3As shown, when the driving transistor M1 is an NMOS transistor, the source of the driving transistor M1 is coupled with the light emitting element 200. For the driving transistor M1 of the NMOS type, when PVDD is always less than Vdata, the greater Vdata is, the greater driving current I is, and the greater display light emitting brightness of the light emitting element 200 is.

[0056] For the convenience of description, without special limitation, the embodiments of the present application are exemplarily described by taking the driving transistor as a PMOS transistor.

[0057] In addition, the embodiments of the present application are exemplarily described by taking the driving transistor as a PMOS transistor. Figure 1 Figure 2 When there is a voltage deviation between the gate of the driving transistor M1 and its source and / or drain, the driving transistor M1 is in a bias state. For example, in the light emitting stage, the voltage of the source or drain of the driving transistor M1 is a positive power signal PVDD, and the gate voltage of the driving transistor M1 includes a data signal, so that the voltage difference between the gate of the driving transistor M1 and its source or drain in the light emitting stage is consistent with the voltage difference between the data signal and the positive power signal. When the voltage difference between the gate of the driving transistor M1 and its source and / or drain is kept constant for a long time, the internal characteristics of the driving transistor M1 change, the threshold voltage of the driving transistor M1 drifts, and the size of the driving current provided by the driving transistor M1 to the light emitting element 200 in the light emitting stage is affected, and then the light emitting brightness of the light emitting element 200 is affected.

[0058] The bias adjustment module 12 in the pixel circuit 100 can provide a bias adjustment signal for the source and / or drain of the driving transistor M1 in the bias adjustment stage of the first non-light emitting stage, so that the voltage of the source and / or drain of the driving transistor M1 is consistent with the bias adjustment signal, the voltage difference between the gate of the driving transistor M1 and its source and / or drain becomes consistent with the difference between the data signal and the bias adjustment signal, the bias state of the driving transistor M1 is adjusted, and the phenomenon that the threshold voltage of the driving transistor M1 drifts due to the voltage difference between the gate of the driving transistor M1 and its source and / or drain being kept constant for a long time is improved or eliminated, so that the display uniformity of the display panel 10 can be improved, and the display effect of the display panel 10 can be ensured.

[0059] ​It can be understood that the bias adjustment module 12 provides the bias adjustment signal for the source and / or drain of the drive transistor M1 in the bias adjustment stage, that is, the bias adjustment module 12 only provides the bias adjustment signal for the source of the drive transistor M1 in the bias adjustment stage, at this time the bias adjustment module 12 can be electrically connected to the source of the drive transistor M1; or, the bias adjustment module 12 only provides the bias adjustment signal for the drain of the drive transistor M1 in the bias adjustment stage, at this time the bias adjustment module 12 can be electrically connected to the drain of the drive transistor M1; or, the bias adjustment module 12 provides the bias adjustment signal for the source and drain of the drive transistor M1 in the bias adjustment stage, at this time the bias adjustment module 12 can be electrically connected to the source and drain of the drive transistor M1 respectively; or, when the bias adjustment module 12 provides the bias adjustment signal for the source and drain of the drive transistor M1 in the bias adjustment stage, the bias adjustment module 12 can also be electrically connected to only one of the source and drain of the drive transistor M1, at this time the bias adjustment module 12 provides the bias adjustment signal for one of the source and drain of the drive transistor M1, and then controls the drive transistor M1 to be in the on state, so that the bias adjustment signal is transmitted from one of the source and drain to the other.

[0060] For the convenience of description, the embodiment of the present application is described by taking that the bias adjustment module is electrically connected to one of the source and drain of the drive transistor M1, for example Figure 2 and Figure 3 It is shown that the bias adjustment module 12 is electrically connected to the drain of the drive transistor M1 and can provide the bias adjustment signal for the source and drain of the drive transistor M1 in the bias adjustment stage, which is taken as an example to exemplarily describe the technical scheme of the embodiment of the present application.

[0061] In an optional embodiment, the bias adjustment module 12 is turned on or turned off under the control of the bias adjustment control signal S-P*, and the bias adjustment module 12 is capable of providing the bias adjustment signal Vpark to the source and the drain of the driving transistor M1 when the bias adjustment control signal S-P* controls the bias adjustment module 12 to be turned on. At this time, the bias adjustment module 12 can include a bias adjustment transistor M2, the gate of the bias adjustment transistor M2 receives the bias adjustment control signal S-P*, the first pole of the bias adjustment transistor M2 receives the bias adjustment signal Vpark, and the second pole of the bias adjustment transistor M2 is electrically connected to the drain of the driving transistor M1 at the node N3. The bias adjustment control signal S-P* is usually a pulse signal, and the high and low levels of the pulse signal can control the transistor to be turned on or turned off. In the embodiment of the present application, the bias adjustment transistor M2 can be an NMOS transistor or a PMOS transistor. When the bias adjustment transistor M2 is an NMOS transistor, the bias adjustment transistor M2 is turned on when the bias adjustment control signal S-P* is at a high level, and the bias adjustment transistor M2 is turned off when the bias adjustment control signal S-P* is at a low level; on the contrary, when the bias adjustment transistor M2 is a PMOS transistor, the bias adjustment transistor M2 is turned on when the bias adjustment control signal S-P* is at a low level, and the bias adjustment transistor M2 is turned off when the bias adjustment control signal S-P* is at a high level. The type of the bias adjustment transistor M2 is not limited in the embodiment of the present application.

[0062] The bias adjustment control signal S-P* can control the bias adjustment module 12 to be turned on in the bias adjustment phase, so that the voltage difference between the gate of the driving transistor M1 and the source and the drain of the driving transistor M1 is consistent with the voltage difference between the data signal Vdata and the bias adjustment signal Vpark; in other phases except the bias adjustment phase, the bias adjustment control signal S-P* controls the bias adjustment module 12 to be turned off, so that the bias adjustment module 12 stops providing the bias adjustment signal Vpark to the source and the drain of the driving transistor M1. At this time, if the source and the drain of the driving transistor M1 are not written with other signals, the source and the drain of the driving transistor M1 will continue to maintain the bias adjustment signal Vpark, for example, in the bias maintenance phase between the end time of the bias adjustment phase and the end time of the first non-emitting phase to which the bias adjustment phase belongs, the voltage difference between the gate of the driving transistor M1 and the source and the drain of the driving transistor M1 will continue to be consistent with the voltage difference between the data signal Vdata and the bias adjustment signal Vpark.

[0063] For example, the driving transistor M1 and the bias adjustment transistor M2 are both PMOS transistors, Figure 4 is a driving timing diagram of a pixel circuit in a display panel provided by the embodiment of the present application, which is combined with reference to Figure 2 and Figure 4After the end of the previous frame, the first non-emitting stage Tb1 of the next frame is entered. In the first non-emitting stage Tb1 of the frame, the data signal of the previous frame displayed on the gate of the driving transistor is cleared, and the data signal of the current frame is provided to the gate of the driving transistor M1; after the end of the first non-emitting stage Tb1, the first emitting stage Ta1 is entered, in which a positive power signal PVDD is provided to the source or drain of the driving transistor M1, so that the voltage difference between the gate and the source of the driving transistor M1 is less than its threshold voltage, the driving transistor M1 generates a driving current and provides it to the light emitting element 200 to drive the light emitting element 200 to emit light; after the end of the first emitting stage Ta1, the second non-emitting stage Tb2 is entered, in which the gate voltage of the driving transistor M1 remains unchanged, at this time, a bias adjustment signal can be provided to the source and / or drain of the driving transistor M1 to alleviate or offset the situation that the threshold voltage of the driving transistor M1 drifts due to the voltage difference between the gate and the source and / or drain of the driving transistor in the previous emitting stage Ta1, so that after entering the next emitting stage Ta2, the driving transistor M1 can recover to the state before the first emitting stage Ta1 as much as possible to ensure that the driving transistor M1 can accurately emit light in the next emitting stage Ta2; similarly, when a frame time includes more non-emitting stages Tb and emitting stages Ta, the non-emitting stages Tb and the emitting stages Ta are alternately performed until the next frame is entered.

[0064] It should be noted that, Figure 4In the embodiment of the present application, the number of non-emitting phase Tb and emitting phase Ta included in a frame picture time is generally set according to the multiple relationship between the refresh frequency of the current frame picture and the basic refresh frequency of the display panel. For example, when the basic refresh frequency of the display panel is 120 Hz, if the refresh frequency of the current frame picture is 120 Hz, the current frame picture can include J non-emitting phase Tb and J emitting phase Ta; or, when the refresh frequency of the current frame picture is 60 Hz, the current frame picture can include 2J non-emitting phase Tb and 2J emitting phase Ta; or, when the refresh frequency of the current frame picture is 30 Hz, the current frame picture can include 4J non-emitting phase Tb and 4J emitting phase Ta, and so on. The number of non-emitting phase Tb and emitting phase Ta included in a frame picture time of the display panel 10 at different refresh frequencies can be determined in this way. In the embodiment of the present application, the basic refresh frequency of the display panel 10 and the refresh frequency of the current frame picture are not specifically limited. J can be equal to any positive integer. For the convenience of description, the embodiment of the present application is exemplarily described by taking J equal to 1.

[0065] For example, if the current display frequency of the display panel is 1 / 2 of the basic frequency, each frame display picture time can include two non-emitting phase Tb and two emitting phase Ta. At this time, the second non-emitting phase Tb2 can be the first non-emitting phase Tb10, which can include a bias adjustment phase Tc. In the bias adjustment phase Tc, the bias adjustment control signal S-P* is a low level for controlling the bias adjustment transistor M2 in the bias adjustment module 12 to be turned on. At this time, the bias adjustment signal Vpark at the bias adjustment signal end can be transmitted to the drain of the driving transistor M1 through the turned-on bias adjustment transistor M2, and then transmitted from the drain of the driving transistor M1 to the source of the driving transistor M1, so that the source and the drain of the driving transistor M1 are both the bias adjustment signal. After the bias adjustment phase Tc ends, a bias maintenance phase Td is entered, in which the gate, source and drain of the driving transistor M1 remain consistent with the signals written in the bias adjustment phase Tc.

[0066] It can be understood that the display panel 10 can have different working modes in different application scenarios, and the display panel 10 can present different display brightness in different working modes. For example, in a brighter environment, in order to enable the picture presented by the display panel 10 to be recognized by the human eye, the picture displayed by the display panel 10 is usually controlled to have a higher display brightness; in a darker environment, in order to prevent the display brightness of the picture presented by the display panel 10 from being too high to cause damage to the human eye, the picture displayed by the display panel 10 is usually controlled to have a lower display brightness. Among them, by adjusting the proportion of the light emitting stage Ta and the non-light emitting stage Tb of the light emitting element 200 in a frame of picture, the display panel 10 can have different display brightness in different working modes; or by adjusting the relationship between the gray scale (i.e. the light emitting brightness level of the light emitting element) and the data signal, the display panel 10 can also have different display brightness in different working modes.

[0067] Among them, when the working mode of the display panel 10 includes the first mode and the second mode, and the brightness of the display panel 10 in the first mode is different from the brightness of the display panel 10 in the second mode, the data signals received by the gate of the driving transistor M1 in each pixel circuit 100 are different, or the time that the voltage difference between the gate and the source and / or drain of the driving transistor M1 in each pixel circuit 100 remains the same as the difference between the data signal and the positive power signal PVDD is different, so that the biasing condition of the driving transistor M1 in each pixel circuit 100 in the first mode is different from the biasing condition of the driving transistor M1 in the second mode.

[0068] For example, to make the display panel 10 have different display brightness in different operation modes by adjusting the relationship between the gray scale (i.e. the light emitting luminance level of the light emitting element) and the data signal, when the brightness of the display panel 10 in the first mode is less than the brightness of the display panel 10 in the second mode, in the first mode, the data signal needed to be provided to the driving transistor M1 in the pixel circuit 100 is Vdata1 when the light emitting element 200 presents the level n of brightness (i.e. the gray scale); while in the second mode, the data signal needed to be provided to the driving transistor M1 in the pixel circuit 100 is Vdata2 when the light emitting element 200 presents the level n of brightness; if the driving transistor M1 is a PMOS transistor, Vdata1 will be greater than Vdata2; thus, when the signal received by the source of the driving transistor M1 is the positive power signal PVDD in the first mode and the second mode, the voltage difference between the gate and the source of the driving transistor M1 in the first mode will be less than the voltage difference between the gate and the source of the driving transistor M1 in the second mode, so that the biasing conditions of the driving transistor M1 in the first mode and the second mode are different, at this time, the biasing adjustment of the driving transistor M1 needs to be made for different operation modes of the display panel 10.

[0069] In an exemplary embodiment, continue to combine reference Figure 1 , Figure 2 and Figure 4, in the first mode, the bias adjustment control signal S-P*(1) provided to the bias adjustment transistor M2 is such that in the bias adjustment stage Tc1 of the first non-emitting stage Tb10 of the first mode, the bias adjustment control signal S-P*(1) is an enable level capable of controlling the bias adjustment transistor M2 to be turned on, to provide the bias adjustment signal Vpark1 to the source and the drain of the driving transistor M1 respectively, and after the bias adjustment stage Tc1 of the first non-emitting stage Tb10 ends, the bias maintenance stage Td1 of the first non-emitting stage Tb10 is entered; in the second mode, the bias adjustment control signal S-P*(2) provided to the bias adjustment transistor M2 is such that in the bias adjustment stage Tc2 of the first non-emitting stage Tb10 of the second mode, the bias adjustment control signal S-P*(2) is an enable level capable of controlling the bias adjustment transistor M2 to be turned on, to provide the bias adjustment signal Vpark2 to the source and the drain of the driving transistor M1 respectively, and after the bias adjustment stage Tc2 of the first non-emitting stage Tb10 ends, the bias maintenance stage Td2 of the first non-emitting stage Tb10 is entered; wherein the bias maintenance stage Td1 in the first mode is greater than the bias maintenance stage Td2 in the second mode, which can make the voltage difference between the gate of the driving transistor M1 and the source and the drain thereof in the first mode remain consistent with Vdata1-Vpark1 for a time length greater than that in the second mode, so that at the termination time of the first non-emitting stage Tb10, the bias degree of the driving transistor M1 in the first mode can remain consistent with that in the second mode, to balance the different bias conditions caused by different data signals in the two modes, to realize the targeted adjustment of the bias state of the driving transistor M1 in different working modes, thereby being beneficial to the display uniformity of the display panel 10 in different working modes.

[0070] In another exemplary embodiment, Figure 5 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, Figure 5 is the same as the description of Figure 4 above, which will not be repeated here. Refer to Figure 4 , Figure 1 , Figure 2 and Figure 5In the first mode, the bias adjustment control signal S-P*(1) provided to the bias adjustment module 12 is kept at the enable level in the bias adjustment stage Tc1 of the first non-light-emitting stage Tb10; in the second mode, the bias adjustment control signal S-P*(2) provided to the bias adjustment module 12 is kept at the enable level in the bias adjustment stage Tc2 of the first non-light-emitting stage Tb10; at this time, by making the length of the bias adjustment stage Tc1 in the first mode different from the length of the bias adjustment stage Tc2 in the second mode, the length of time for which the bias adjustment signal Vpark1 is written to the source and drain of the driving transistor M1 in the first mode is made different from the length of time for which the bias adjustment signal Vpark2 is written to the source and drain of the driving transistor M1 in the second mode, so that at the end of the bias adjustment stage Tc, the bias of the driving transistor M1 in the first mode can be consistent with the bias of the driving transistor M1 in the second mode, thereby enabling targeted adjustment of the bias state of the driving transistor M1 in different working modes, and thus facilitating display uniformity of the display panel 10 in different working modes

[0071] In yet another exemplary embodiment, Figure 6 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, which is described in combination with Figure 1 、 Figure 2 and Figure 6 , the length of the bias adjustment stage Tc1 in the first mode is different from the length of the bias adjustment stage Tc2 in the second mode, and at the same time, the length of the bias maintenance stage Td1 in the first mode is different from the length of the bias maintenance stage Td2 in the second mode, at this time, targeted adjustment of the bias state of the driving transistor M1 in different working modes can also be achieved, thereby improving display uniformity of the display panel 10 in different working modes.

[0072] In an optional embodiment, the voltage of the bias adjustment signal Vpark1 in the first mode can be the same as the voltage of the bias adjustment signal Vpark2 in the second mode. In this way, by controlling at least one of the bias adjustment stage Tc and the bias maintenance stage Td in different working modes to be different, to enable targeted adjustment of the bias state of the driving transistor M1 in each brightness mode, without changing the bias adjustment signal Vpark provided by the driving chip, thereby reducing the additional power consumption caused by repeated charging and discharging of the circuit, signal lines, etc. due to changes in the bias adjustment signal Vpark, and thus ensuring the display effect of the display panel 10 while improving the display uniformity of the display panel 10.

[0073] It should be noted that the working modes of the display panel mentioned in the embodiments of the present application include the first mode and the second mode, and are not only two working modes of the display panel 10, but represent different working modes of the display panel 10 by using the first mode and the second mode, and the display panel 10 has different brightness in different working modes. In the embodiments of the present application, the working mode of the display panel 10 is different in different application scenarios, so that the display panel 10 has different brightness. For ease of description, without special instructions, the working mode of the display panel 10 includes two modes (the first mode and the second mode) as an example, and the technical solutions of the embodiments of the present application are exemplarily described.

[0074] The technical solutions of the embodiments of the present application ensure that the voltage difference between the source and / or drain of the driving transistor and the gate thereof in the bias adjustment stage and the bias maintenance stage is the voltage difference between the bias adjustment signal and the gate thereof, which is different from the voltage difference between the source and / or drain of the driving transistor and the gate thereof in the light-emitting stage, so that the bias adjustment of the driving transistor is realized in the bias adjustment stage and the bias maintenance stage, and the situation that the threshold voltage drifts due to the long-time unchanged voltage difference between the source and / or drain of the driving transistor and the gate thereof is improved. At the same time, the display panel presents different display brightness when the display panel is in different modes, and the gate voltage of the driving transistor is different when the display panel presents different display brightness. At this time, by controlling at least one of the bias adjustment stage and the bias position stage in different brightness modes to be different, the time for keeping the source and / or drain of the driving transistor as the bias adjustment signal is different, so as to adjust the bias state of the driving transistor in each brightness mode, thereby ensuring the display uniformity in different brightness modes. In addition, without changing the bias adjustment signal provided by the driving chip, the additional power consumption caused by the repeated charging and discharging of the circuit, signal line and the like due to the change of the bias adjustment signal is reduced, and the display effect of the display panel is ensured on the premise of improving the display uniformity of the display panel.

[0075] It can be understood that at least one of the bias adjustment stage Tc and the bias maintenance stage Td in the first mode and the second mode is different, wherein the way of setting at least one of the bias adjustment stage Tc and the bias maintenance stage Td in different working modes to be different can be realized by adjusting the starting time and the ending time of the bias adjustment control signal Vpark provided to the bias adjustment module 12.

[0076] In an optional embodiment, Figure 7 is another schematic top view of a display panel provided by an embodiment of the present application, which is described in combination with Figure 2 , Figure 4-6 and Figure 7 , the display panel 10 can include a display area 110 and a non-display area 120, wherein the display area 110 is provided with a plurality of pixel circuits 100 arranged in an array and a plurality of light emitting elements 200 electrically connected to the pixel circuits 100 in correspondence, and the non-display area 120 is provided with at least one shift register circuit 300, which can include a plurality of shift register units 310 connected in cascade; in a frame of picture, the signals provided by each shift register unit 310 of the shift register circuit 300 can perform line-by-line scanning on the pixel circuits 100, so that the pixel circuits 100 can work in sequence.

[0077] The shift register circuit 300 at least includes a shift register circuit 300 providing a bias adjustment control signal. At this time, the display area 110 is further provided with a plurality of control signal lines 410, the gate of the bias adjustment transistor M2 of at least part of the pixel circuits 100 in the same row is electrically connected to the same control signal line 410; the signal output end of each shift register unit 310 of the shift register circuit 300 is respectively electrically connected to each control signal line 410, so as to be able to sequentially provide the enable level of the bias adjustment control signal S-P* to each control signal line 410. The starting time and the ending time of the bias adjustment control signal S-P* provided by each shift register unit 310 of the shift register circuit 300 to each control signal line 410 are determined by the control signal received by the shift register unit 310, therefore, by adjusting the control signal provided to each shift register unit 310, the time length of the bias adjustment phase Tc and the bias maintenance phase Td in different working modes can be adjusted.

[0078] Optionally, in combination with Figure 2 and Figure 4 (or Figure 5-6 any of the accompanying drawings), the pixel circuit 100 further includes a data writing module 13, which is used for providing a data signal Vdata to the gate of the driving transistor M1 in a data writing phase, and the non-light emitting phase Tb of a frame of picture of the display panel 10 includes a data writing phase Te; in the same pixel circuit 100, the data writing phase Te and the bias adjustment phase Tc are not overlapped in time.

[0079] Specifically, the driving transistor M1 generates different driving current when receiving different data signal Vdata, so that the light emitting element 200 has different light emitting brightness. Usually, the first non-light emitting stage Tb1 of a frame picture includes a data writing stage Te, and in each data writing stage Te, the data writing module 13 can provide a corresponding data signal Vdata to the gate of the driving transistor M1, so that when entering the light emitting stage Ta of the frame picture, the driving transistor M1 can provide a corresponding driving current to the light emitting element 200 according to the data signal Vdata of its gate, so as to control the light emitting brightness of the light emitting element 200, so that the display panel 10 presents a display picture with corresponding content and brightness.

[0080] Wherein, the data writing stage Te and the bias adjusting stage Tc of the same pixel circuit 100 do not overlap in time, that is, when writing the data signal Vdata, the bias adjusting signal Vpark is not provided to any of the source and drain of the driving transistor M1, so as to prevent the bias adjusting signal Vpark from affecting the accuracy of the data signal Vdata writing; on the contrary, when at least one of the source and drain of the driving transistor M1 is provided with the bias adjusting signal Vpark, the gate of the driving transistor M1 is not provided with the data signal Vdata. At this time, the bias adjusting stage Tc can be located before or after the data writing stage Te.

[0081] It should be noted that, Figure 4-6 In the embodiment, only the first non-light emitting stage Tb1 includes the data writing stage Te, and the second non-light emitting stage Tb2 (i.e. the first non-light emitting stage Tb10) includes the bias adjusting stage Tc, that is, the data writing stage Te and the bias adjusting stage Tc are located in different non-light emitting stages, and the data writing stage Te is located before the bias adjusting stage Tc, but the present application is not limited to this setting mode.

[0082] In an exemplary embodiment, Figure 8 is another driving timing diagram of a pixel circuit in a display panel provided by the embodiment of the present application, which is combined with reference to Figure 2 and Figure 8As shown, the first non-light-emitting stage Tb1 of a frame of picture simultaneously includes the data writing stage Te and the bias adjustment stage Tc, and the bias adjustment stage Tc is located after the data writing stage Te, that is, after the writing of the data signal Vdata to the gate of the driving transistor M1 is completed, the bias adjustment stage Tc is entered, in which the bias adjustment signal Vpark can be written to the source and the drain of the driving transistor M1, so that the potentials of the source and the drain of the driving transistor M1 of each pixel circuit 100 in the display panel are kept consistent before the light-emitting stage Ta, that is, the bias states of each driving transistor M1 are kept consistent, thereby being beneficial to improving the display uniformity of the display panel 10.

[0083] In another exemplary embodiment, the bias maintenance stages in different working modes are different, Figure 9 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, which is combined with reference to Figure 2 and Figure 9 As shown, the first non-light-emitting stage Tb1 of a frame of picture simultaneously includes the data writing stage Te and the bias adjustment stage Tc, and the bias adjustment stage Tc is located before the data writing stage Te, that is, after the end of the previous frame of picture, because there is a voltage difference between the gate and the source and the drain of the driving transistor M1 in the light-emitting stage Ta of the previous frame of picture, the driving transistor M1 is in a bias state, which is not conducive to the writing of the data signal Vdata of the current frame of picture, by providing the bias adjustment signal Vpark to the source and the drain of the driving transistor M1 in the bias adjustment stage Tc, the bias state of the driving transistor M1 in the light-emitting stage of the previous frame of picture is alleviated or eliminated, so that after the bias adjustment stage T, when entering the data writing stage, the data signal Vdata can be accurately written to the gate of the driving transistor M1.

[0084] It can be understood that the data writing module 13 can be directly electrically connected with the gate of the driving transistor M1 to be able to provide the data signal directly to the gate of the driving transistor M1; the data writing module 13 can also be indirectly electrically connected with the gate of the driving transistor M1; under the premise that the data writing module 13 can provide the data signal for the driving transistor M1, the present embodiment does not make specific limitation thereto.

[0085] Exemplarily, the above description is combined with reference to Figure 2 and Figure 4 (or Figure 5-6 and Figure 8-9As shown in any one of the accompanying drawings, one end of the data writing module 13 can receive the data signal Vdata, and the other end of the data writing module 13 can be electrically connected to the node N2 with the source of the driving transistor M1, and the data writing module 13 can be turned on or off under the control of the scanning signal S-P. When the data writing module 13 is controlled to be turned on by the scanning signal S-P, the data writing module 13 can write the data signal Vdata to the source of the driving transistor M1, and transmit the data signal Vdata from the source of the driving transistor M1 to the gate of the driving transistor M1. At this time, the data writing module 13 can include a data writing transistor M3, the gate of the data writing transistor M3 can receive the scanning signal S-P, the first pole of the data writing transistor M3 receives the data signal Vdata, and the second pole of the data writing transistor M3 is electrically connected to the source of the driving transistor M1. The data writing transistor M3 can be an NMOS transistor or a PMOS transistor. When the data writing transistor M3 is an NMOS transistor, the data writing transistor M3 is turned on when the scanning signal S-P is at a high level, and the data writing transistor M3 is turned off when the scanning signal S-P is at a low level; on the contrary, when the data writing transistor M3 is a PMOS transistor, the data writing transistor M3 is turned on when the scanning signal S-P is at a low level, and the data writing transistor M3 is turned off when the scanning signal S-P is at a high level. The type of the data writing transistor M3 is not limited in the embodiment of the present application.

[0086] Optionally, continue to combine reference Figure 2 and Figure 4 (or Figure 5-6 and Figure 8-9 As shown in any one of the accompanying drawings, when the data writing module 13 is electrically connected to the source of the driving transistor M1, the pixel circuit 100 can further include a compensation module 14 electrically connected between the drain and the gate of the driving transistor M1, that is, one end of the compensation module 14 is electrically connected to the node N3 with the drain of the driving transistor M1, and the other end of the compensation module 14 is electrically connected to the node N1 with the gate of the driving transistor M1; the compensation module 14 can compensate the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1 at the same time when the data signal Vdata is written, so as to offset or alleviate the influence of the threshold voltage of the driving transistor M1 on the driving current provided by the driving transistor M1 in the light-emitting stage.

[0087] For example, the compensation module 14 can be turned on or off under the control of the scan signal S-N2, and when the compensation module 14 is turned on under the control of the scan signal S-N2, the compensation module 14 can adjust the voltage between the gate and the drain of the driving transistor M1 and compensate the threshold voltage of the driving transistor M1. At this time, the compensation module 14 can include a compensation transistor M4, a first electrode of the compensation transistor M4 is electrically connected to the drain of the driving transistor M1, a second electrode of the compensation transistor M4 is electrically connected to the gate of the driving transistor M1, and the gate of the compensation transistor M4 receives the scan signal S-N2.

[0088] It can be understood that the compensation transistor M4 can be an NMOS transistor, and the material of the active layer of the compensation transistor M4 can include an oxide semiconductor, which can be an indium gallium zinc oxide (IGZO) semiconductor. At this time, the compensation transistor M4 is turned on under the control of the high level of the scan signal S-N2 and is turned off under the control of the low level of the scan signal S-N2.

[0089] In other optional embodiments, the compensation transistor M4 can also be a PMOS transistor, and the material of the active layer of the compensation transistor M4 can include a silicon-based semiconductor, which can be a low-temperature polysilicon (LTPS) semiconductor. At this time, the compensation transistor M4 is turned on under the control of the low level of the scan signal received by the gate of the compensation transistor M4 and is turned off under the control of the high level of the scan signal received by the gate of the compensation transistor M4. The embodiments of the present application do not make specific limitations on the type of compensation transistor.

[0090] It can be understood that when the data writing module 13 is electrically connected to the source of the driving transistor M1 and the compensation module 14 is electrically connected between the drain and the gate of the driving transistor M1, the data signal Vdata needs to pass through the data writing module 13, the driving transistor M1 and the compensation module 14 in sequence to be written to the gate of the driving transistor M1. Therefore, before the data writing stage, the driving transistor M1 needs to be in the on state. At this time, the gate of the driving transistor M1 can be initialized by providing an initialization signal Vref1 to the gate of the driving transistor before the data writing stage, so that the driving transistor M1 can be in the on state at the beginning of the data writing stage.

[0091] Correspondingly, continuing to combine with reference to Figure 2 and Figure 4 (or Figure 5-6 and Figure 8-9 any of the accompanying drawings), the pixel circuit 100 can further include an initialization module 15, one end of the initialization module 15 receives an initialization signal Vref1, and the other end is electrically connected to the gate of the driving transistor M1. In the initialization stage Tf, the initialization module 15 can transmit the initialization signal Vref1 to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1.

[0092] The initialization module 15 can be turned on or turned off under the control of the scanning signal S-N1, and when the initialization module 15 is turned on under the control of the scanning signal S-N1, the initialization signal Vref1 is transmitted to the gate of the driving transistor M1. At this time, the initialization module 15 can include an initialization transistor M5, the gate of the initialization transistor M5 receives the scanning signal S-N1, the first electrode of the initialization transistor M5 receives the reset signal Vref, and the second electrode of the initialization transistor M5 is electrically connected to the node N1 with the gate of the driving transistor M1.

[0093] It can be understood that the initialization transistor M5 can be an NMOS transistor, and the material of the active layer of the initialization transistor M5 can include an oxide semiconductor, which can be an indium gallium zinc oxide (IGZO) semiconductor. At this time, the initialization transistor M5 is turned on under the control of the high level of the scanning signal S-N2, and is turned off under the control of the low level of the scanning signal S-N2.

[0094] In other optional embodiments, the initialization transistor M5 can also be a PMOS transistor, and the material of the active layer of the initialization transistor M5 can include a silicon-based semiconductor, which can be a low-temperature polysilicon (LTPS) semiconductor. At this time, the initialization transistor M5 is turned on under the control of the low level of the scanning signal received by the gate of the initialization transistor M5, and is turned off under the control of the high level of the scanning signal received by the gate of the initialization transistor M5. The embodiments of the present application do not make specific limitations on the type of the initialization transistor M5.

[0095] It can be understood that the above only exemplarily takes the data writing module 13 and the bias adjustment module 12 as examples of being respectively electrically connected to the source and the drain of the driving transistor M1 to exemplarily describe the technical solutions of the embodiments of the present application. In other embodiments of the present application, Figure 10 is another structure schematic diagram of a pixel circuit in a display panel provided by the embodiments of the present application, Figure 11 is another structure schematic diagram of a pixel circuit in a display panel provided by the embodiments of the present application, as Figure 10-11 In any of the above figures, the data writing module 13 and the bias adjustment module 12 can also be simultaneously electrically connected to the source of the driving transistor M1, and the working principle is similar to the case that the data writing module 13 and the bias adjustment module 12 are respectively electrically connected to the source and the drain of the driving transistor M1, which will not be described here.

[0096] It should be noted that the above only exemplarily takes the case that only one bias adjustment stage is included in the same non-emitting stage as an example for exemplarily description, and in other embodiments of the present application, the non-emitting stage can also include two bias adjustment stages or multiple bias adjustment stages.

[0097] Exemplarily,Figure 12 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, which is described in combination with reference to Figure 10 and Figure 12As shown, the first non-emitting stage Tb1 of each frame picture is taken as an example. After the emitting stage of the previous frame picture ends, the non-emitting stage Tb (i.e., the first non-emitting stage Tb10) of the next frame picture is entered. Since the driving transistor M1 needs to provide a driving current to the light-emitting element 200 to drive the light-emitting element 200 to emit light in the emitting stage of the previous frame picture, a voltage difference exists between the gate, source and drain of the driving transistor M1, so that the driving transistor M1 is in a bias state. Therefore, when the non-emitting stage Tb of the next frame picture is entered, the bias adjustment of the driving transistor M1 can be performed first, i.e., the first bias adjustment stage Tc11 / Tc21 is entered. At this time, the bias adjustment control signal S-P* controls the bias adjustment module 12 to be turned on, and the scan signal S-N2 controls the compensation module 14 to be turned on, so that the bias adjustment signal Vpark is written to the node N2, transmitted to the node N3 through the driving transistor M1, and transmitted to the node N1 through the compensation module 14. At this time, the potentials of the gate, source and drain of the driving transistor M1 are consistent with the voltage of the bias adjustment signal Vpark, so that the driving transistor M1 is transitioned from the bias state in the emitting stage of the previous frame picture to a non-bias state. After the bias adjustment of the driving transistor M1 is completed, the initialization stage Tf is entered. The scan signal S-N1 controls the initialization module 15 to be turned on, and the initialization signal Vref1 is written to the node N1 to initialize the gate of the driving transistor M1, so as to prepare for the subsequent writing of the data signal Vdata. After the initialization of the gate of the driving transistor M1 is completed, the next initialization stage Tf' is entered. At this time, the initialization module 15 continues to be in the turned-on state, and the compensation module 14 also continues to be in the turned-on state, so that the initialization signal Vref1 is transmitted to the node N3, i.e., the drain of the driving transistor M1. At this time, the drain and gate potentials of the driving transistor M1 are consistent and are the initialization signal Vref1, so as to further bias the driving transistor M1 and prepare for the writing of the data signal Vdata. After the initialization stage Tf' ends, the data writing stage Te is entered. At this time, the compensation module 14 continues to be in the turned-on state, and the scan signal S-P controls the data writing module 13 to be turned on. The data signal Vdata is sequentially written to the gate of the driving transistor M1 through the data writing module 13, the driving transistor M1 and the compensation module 14, and the threshold voltage Vth of the driving transistor M1 is compensated to the gate of the driving transistor M1, so that the gate potential of the driving transistor M1 is Vdata+Vth at the end of the data writing stage Te.After the writing of the data signal Vdata is completed, a second bias adjustment stage Tc12 / Tc22 is entered, so that the bias adjustment control signal S-P* controls the bias adjustment module 12 to be turned on again, and the bias adjustment signal Vpark is written to the source and drain of the driving transistor M1 again to perform bias adjustment on the driving transistor M1 again, so as to ensure that the source and drain potentials of the driving transistor M1 of each pixel circuit can be kept consistent in the subsequent light emitting stage Ta, and the display uniformity of the display panel is improved.

[0098] It can be understood that, in different working modes, the data signal Vdata written to the gate of the driving transistor M1 in the data writing stage is different, so that the driving transistor M1 has different states after the data writing stage, and therefore, the time length of the second bias adjustment stage Tc12 and / or the time length of the bias maintenance stage Td1 in the first mode can be set to be different from the time length of the second bias adjustment stage Tc22 and / or the time length of the bias maintenance stage Td1 in the second mode.

[0099] It should be noted that, Figure 12 Only part of the stages of a frame of display picture is shown, and in the embodiment of the present application, when a frame of picture includes multiple light emitting stages and multiple non-light emitting stages, the setting mode of other non-light emitting stages and light emitting stages can be referred to the description above, and will not be described here again.

[0100] Optionally, continuing to combine with reference to Figure 2 (or Figure 3 and Figure 10-11 any drawing) and Figure 4 (or Figure 5-6 and Figure 8-9 any drawing), the pixel circuit 100 can further include a light emitting control module 16, which can control the time when the driving transistor M1 provides driving current to the light emitting element 200. Wherein, the light emitting control module 16 can be connected in series with the light emitting element 200 and the driving transistor M1 between the positive power signal end and the negative power signal end.

[0101] In an exemplary embodiment, the light emitting control module 16 can include a first light emitting control transistor M6 and a second light emitting control transistor M7, the gate of the first light emitting control transistor M6 and the gate of the second light emitting control transistor M7 both receiving a light emitting control signal Emit, the first electrode of the first light emitting control transistor M6 receiving a positive power supply signal PVDD, the second electrode of the first light emitting control transistor M6 being electrically connected to the source of the driving transistor M1, the first electrode of the second light emitting control transistor M7 being electrically connected to the drain of the driving transistor M1, and the second electrode of the second light emitting control transistor M7 being electrically connected to the anode of the light emitting element 200. The light emitting control signal Emit can be a pulse signal. When the first light emitting control transistor M6 and the second light emitting control transistor M7 are both NMOS transistors, a high level of the light emitting control signal Emit controls the first light emitting control transistor M6 and the second light emitting control transistor M7 to be turned on, and a low level of the light emitting control signal Emit controls the first light emitting control transistor M6 and the second light emitting control transistor M7 to be turned off. When the first light emitting control transistor M6 and the second light emitting control transistor M7 are both PMOS transistors, a low level of the light emitting control signal Emit controls the first light emitting control transistor M6 and the second light emitting control transistor M7 to be turned on, and a high level of the light emitting control signal Emit controls the first light emitting control transistor M6 and the second light emitting control transistor M7 to be turned off. In this way, by controlling the duty cycle of the light emitting control signal Emit, the on duration of the first light emitting control transistor M6 and the second light emitting control transistor M7 can be controlled.

[0102] It can be understood that when the first light emitting control transistor M6 and the second light emitting control transistor M7 are both turned on, the positive power supply signal PVDD can control the first light emitting control transistor M6 to transmit to the source of the driving transistor M1, so that the driving transistor M1 is turned on and generates a driving current, and the driving current generated by the driving transistor M1 can be transmitted to the anode of the light emitting element 200 through the turned-on second light emitting control transistor M7, so that the light emitting element 200 emits light. That is, the stage when the first light emitting control transistor M6 and the second light emitting control transistor M7 are both turned on is the light emitting stage Ta, and the stage when the first light emitting control transistor M6 and the second light emitting control transistor M7 are both turned off is the non-light emitting stage Tb. By controlling the duty cycle of the light emitting control signal Emit, the length of the light emitting stage Ta can be controlled.

[0103] Thus, when at least one of the bias adjustment phase Tc and the bias maintaining phase Td of the display panel 10 in different working modes is different, the time length of at least one of the bias adjustment phase Tc and the bias maintaining phase Td can be controlled by adjusting the relative time between the start time and / or the end time of the enable level of the bias adjustment control signal S-P* provided to the bias adjustment module 12 and the start time of the enable level of the light emitting control signal Emit provided to the light emitting control module 16.

[0104] It should be noted that, Figure 2 Only the driving transistor M1 is exemplarily taken as a PMOS transistor to exemplarily describe the connection light emitting of the first light emitting control transistor M6 and the second light emitting control transistor M7; and in the embodiment of the present application, the driving transistor M1 can also be an NMOS transistor, as shown in FIG. 6, in which the second electrode of the first light emitting control transistor M6 is electrically connected with the drain electrode of the driving transistor M1, and the first electrode of the second light emitting control transistor M7 is electrically connected with the source electrode of the driving transistor M1. Figure 3

[0105] It should be noted that, the above embodiments are exemplarily described by taking the data writing module 13 and the bias adjustment module 12 as two different modules respectively, and in the embodiment of the present application, other cases can also be used.

[0106] Optionally, Figure 13 is another structure schematic diagram of a pixel circuit in a display panel provided by the embodiment of the present application, Figure 14 is another structure schematic diagram of a pixel circuit in a display panel provided by the embodiment of the present application, referring to Figure 13 and Figure 14 Any one of the accompanying drawings, the data writing module 13 can be multiplexed as the bias adjustment module 12.

[0107] Exemplarily, taking the data writing module 13 including the PMOS type data writing transistor M3 as an example, Figure 15 is a working timing diagram of a pixel circuit in another display panel provided by the embodiment of the present application, referring to Figure 13-14 ​Since the time of the data writing stage Te and the bias adjustment stage Tc does not overlap, that is, the writing of the data signal Vdata and the writing of the bias adjustment signal Vpark are time-division, the enable level of the scan signal S-P can be provided to the data writing transistor M3 in the data writing stage Te and the bias adjustment stage Tc respectively, so that in the data writing stage Te, the data writing transistor M3 can write the data signal Vdata to the gate of the driving transistor M1, and in the bias adjustment stage Tc, the data writing transistor M3 can provide the bias adjustment signal Vpark to the source and the drain of the driving transistor M1; in this way, without additionally setting a bias adjustment module, the structure of the pixel circuit 100 can be simplified, which is conducive to increasing the number of pixel circuits 100 in a unit area of the display panel 10, thereby improving the resolution of the display panel 10; meanwhile, when the data writing module 13 is multiplexed as a bias adjustment module, the number of signals provided to the pixel circuit 100 can also be reduced, thereby being conducive to simplifying the structure of the shift register circuit 300 in the non-display area 120 of the display panel 10, and being conducive to the narrow frame of the display panel 10.

[0108] It can be understood that the pixel circuit and the driving timing diagram thereof are only exemplary figures of the embodiments of the present application, and the specific setting mode of the bias adjustment stage and the bias maintenance stage in different working modes is not limited in the embodiments of the present application on the premise that the bias of the driving transistor can be adjusted to different degrees in different working modes.

[0109] In an optional embodiment, the relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel 10 is as follows:

[0110]

[0111] wherein DBV1 is the brightness of the display panel in the first mode, t1 is the time length of the bias maintenance stage in the first mode; DBV2 is the brightness of the display panel in the second mode, t2 is the time length of the bias maintenance stage in the second mode; and T is the time length of the first non-emitting stage.

[0112] It can be understood that DBV1 can be the display brightness of the display panel when the highest brightness level corresponding data signal is provided to each pixel circuit of the display panel in the first mode; DBV2 can be the display brightness of the display panel when the highest brightness level corresponding data signal is provided to each pixel circuit of the display panel in the second mode. By adjusting the relationship between the gray scale and the data signal, the display panel presents different brightness in different working modes, and the light emitting brightness level of the light emitting element includes 0-255 gray scales, for example, for the same pixel circuit, the data signal corresponding to 255 gray scales in the first mode is different from the data signal corresponding to 255 gray scales in the second mode; in a mode, the data signal corresponding to 255 gray scales is provided to each pixel circuit of the display panel, so that the display brightness of the display panel is DBV1; in the second mode, the data signal corresponding to 255 gray scales is provided to each pixel circuit of the display panel, so that the display brightness of the display panel is DBV2. In this way, by providing the data signal corresponding to 255 gray scales to each pixel circuit of the display panel respectively, and driving the light emitting element to emit light by the driving module of each pixel circuit, the display brightness of the display panel in different working modes can be measured by using the corresponding brightness test equipment.

[0113] Correspondingly, in the first mode, after providing the data signal corresponding to 255 gray scales in the mode to each pixel circuit of the display panel, the length of the bias maintaining stage is adjusted to make the brightness of the display panel be DBV1 when the light emitting element emits light in the light emitting stage, at this time, the length of the bias maintaining stage is the length of the bias maintaining stage t1 that should be set in the first mode; similarly, in the second mode, after providing the data signal corresponding to 255 gray scales in the mode to each pixel circuit of the display panel, the length of the bias maintaining stage is adjusted to make the brightness of the display panel be DBV2 when the light emitting element emits light in the light emitting stage, at this time, the length of the bias maintaining stage is the length of the bias maintaining stage t2 that should be set in the second mode.

[0114] It should be noted that in the actual test process, the length of the bias maintaining stage corresponding to each working mode can be determined for different working modes, so as to determine the relationship curve between the brightness and the bias maintaining stage, and the corresponding relationship formula is determined based on the relationship curve.

[0115] Exemplarily, Figure 16 is a relationship curve between the brightness of the display panel and the bias maintaining stage provided by an embodiment of the application, and reference is made to Figure 13 、 Figure 15 and Figure 16As shown, the display brightness DBV and the time length t of the bias maintaining stage Td satisfy a linear relationship, at this time, the brightness linear relationship can be determined based on the display brightness DBV1 and the time length t1 of the bias maintaining stage Td1 of the display panel in the first mode, and the display brightness DBV2 and the time length t2 of the bias maintaining stage Td2 of the display panel in the second mode. Thus, when the display panel displays a frame of picture, the working mode of the display panel when displaying the frame of picture can be known in advance, that is, the DBV corresponding to the frame of picture can be determined in advance, the DBV is substituted into the above relationship, and a time t0 can be determined, based on the time t0, the upper limit of the value of the bias maintaining stage t in the working mode is t0+0.25*T, and the lower limit of the value of the bias maintaining stage t in the working mode is t0-0.25*T, according to which it can be concluded that the time length t of the bias maintaining stage Td required at any display brightness DBV; at the same time, by making the time length t of the bias maintaining stage Td take a value within the range of t0-0.25*T to t0+0.25*T, the bias maintaining stage Td can meet different display control requirements on the premise that the bias maintaining stage Td is within the first non-emitting stage Tb.

[0116] Optionally, continue to combine with reference to Figure 7 , Figure 13 and Figure 15 , the correction relationship of the time t of the bias maintaining stage Td is:

[0117] or,

[0118] wherein t' is the time of the corrected bias maintaining stage Td, is the integer value of , H=1 / (F*Lines), F is the refresh frequency of the display panel, and Lines is the number of rows of the pixel circuit 100 in the display panel.

[0119] For example, when the bias adjustment module 12 includes a bias adjustment transistor M2, and the bias adjustment transistor M2 is turned on or off under the control of a bias adjustment control signal S-P*, the bias adjustment control signal S-P* is provided by the corresponding shift register circuit 300, the bias adjustment control signal S-P* output by each shift register unit 310 of the shift register circuit 300 can scan the pixel circuit 100 row by row, and the length of time when each row of pixel circuit 100 is scanned is controlled by the corresponding row synchronization signal. At this time, according to the linear relationship between the brightness and the bias maintenance stage, the length of time t of the bias maintenance stage Td can be determined, and the starting time and the ending time of the bias adjustment stage Tc are determined based on the length of time t of the bias maintenance stage Td. However, since there is a length of time t of the bias maintenance stage Td that is not an integer multiple of the length of time of scanning a row of pixel circuit 100, thus, when the mode of the display panel is switched, the amount of translation of the starting time and the ending time of the bias adjustment stage Tc determined based on the length of time t of the bias maintenance stage Td is not an integer multiple of the length of time of scanning a row of pixel circuit 100, so the row synchronization signal needs to be adjusted accordingly, which requires a complex control method to achieve the translation of the bias adjustment stage Tc.

[0120] Based on the above problems, after determining the length of time of the bias maintenance stage corresponding to the current frame of picture, the length of time t of the bias maintenance stage Td calculated using the linear relationship between the brightness and the bias maintenance stage can be corrected using the time correction relationship of the bias maintenance stage, so that the corrected length of time t of the bias maintenance stage Td is an integer multiple of the length of time H of the bias adjustment stage Tc, that is, the corrected length of time t' of the bias maintenance stage Td is an integer multiple of the length of time of scanning a row of pixel circuit, so that when the mode of the display panel is switched, the length of the row synchronization signal does not need to be changed, and only a simple translation of one or more control signals provided to the shift register circuit is needed, which is conducive to simplifying the control method of the display panel, improving the mode switching speed of the display panel, and facilitating the high-quality display requirements of the display panel.

[0121] It can be understood that in the above correction relationship, is rounded down, that is, when , is equal to 1; when , is also equal to 1. Thus, after the length t1 of the bias maintenance stage Td1 in the first mode is determined, the enable level time of the bias adjustment control signal S-P* can be translated to achieve mode switching based on the length t1 of the bias maintenance stage Td1 in the first mode. When the corrected length of the bias maintenance stage Td of a frame of picture When the frame picture is in the bias adjustment stage Tc, the bias adjustment control signal S-P* is enabled for a time period of the enable level of the bias adjustment control signal S-P*. When the frame picture is in the bias maintenance stage Td, the bias adjustment control signal S-P* is disabled for a time period of the disable level of the bias adjustment control signal S-P*. When the frame picture is in the bias adjustment stage Tc, the bias adjustment control signal S-P* is enabled for a time period of the enable level of the bias adjustment control signal S-P*. When the frame picture is in the bias maintenance stage Td, the bias adjustment control signal S-P* is disabled for a time period of the disable level of the bias adjustment control signal S-P*.

[0122] It should be noted that the display panel can include a plurality of pixel circuits arranged in an array, and the time for the display panel to display a frame picture is the inverse of the refresh frequency F, i.e., 1 / F; after the time for the display panel to display a frame picture is known, the average time for scanning each row of pixels can be further determined, and the time is H = 1 / (F*Lines).

[0123] It can be understood that the technical solutions of the embodiments of the present application are exemplarily described by exemplarily taking the bias adjustment stage Tc as a continuous time period, and the bias adjustment stage Tc in the embodiments of the present application can also be a plurality of non-continuous stages.

[0124] Optionally, with reference to any one of the accompanying drawings of Figure 2-3 10-11, and 12-13, when the first electrode of the driving transistor M1 is the source electrode or the drain electrode of the driving transistor M1, and the bias adjustment module 12 is electrically connected between the bias adjustment signal end and the first electrode of the driving transistor M1, each bias adjustment stage Tc includes at least two bias adjustment sub-stages Tc'; in each bias adjustment sub-stage Tc', the bias adjustment module 12 is turned on; and in the time period between the adjacent two bias adjustment sub-stages Tc', the bias adjustment module 12 is turned off.

[0125] Exemplarily, the bias adjustment module includes a bias adjustment transistor M2, the bias adjustment transistor M2 is multiplexed as a data writing transistor, and the bias adjustment transistor M2 is a PMOS type transistor electrically connected to the source electrode of the driving transistor M1 as an example, Figure 17 is another driving timing diagram of a pixel circuit in a display panel provided by the embodiments of the present application, and the combination of Figure 13 and Figure 17Before entering the bias adjustment stage Tc, the source of the driving transistor M1 receives a positive power signal PVDD, so that the driving transistor M1 can generate a corresponding driving current, so that at the starting moment of the bias adjustment stage Tc, the bias adjustment signal Vpark needs to be written on the basis of the positive power signal PVDD, which will have a certain influence on the writing of the bias adjustment signal Vpark. At this time, by dividing the bias adjustment stage Tc into a plurality of bias adjustment sub-stages Tc', in the first bias adjustment sub-stage Tc', the bias adjustment signal Vpark provided to the source of the driving transistor M1 is written on the basis of part of the bias adjustment signal Vpark, so as to reduce the voltage difference between the source potential of the driving transistor M1 and the bias adjustment signal Vpark; in the next bias adjustment stage Tc', the bias adjustment signal Vpark can be continuously written on the basis of the signal written in the previous bias adjustment sub-stage Tc', so as to further reduce the difference between the source potential of the driving transistor M1 and the bias adjustment signal Vpark; and so on. By setting a plurality of bias adjustment sub-stages Tc' in a bias adjustment stage Tc, the source potential of the driving transistor M1 can be kept consistent with the bias adjustment signal Vpark, that is, the accurate writing of the bias adjustment signal Vpark can be ensured, so that the effect of bias adjustment of the driving transistor M1 can be improved based on the accurate bias adjustment signal Vpark.

[0126] It can be understood that when the bias adjustment stage Tc includes a plurality of bias adjustment sub-stages Tc', the bias adjustment sub-stages Tc' can be set in the same way or differently in different working modes. In an optional embodiment, by making different working modes have different bias adjustment sub-stages Tc', different lengths of time of the bias adjustment stage Tc in different working modes can be obtained.

[0127] In an optional embodiment, Figure 18 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, which is described in combination with Figure 13 and Figure 18 The length of time of each bias adjustment sub-stage Tc' in the first mode is the same as the length of time of each bias adjustment sub-stage Tc' in the second mode, and the number of bias adjustment sub-stages Tc' in each bias adjustment stage Tc in the first mode is different from the number of bias adjustment sub-stages Tc' in each bias adjustment stage Tc in the second mode.

[0128] Specifically, since the bias condition of the driving transistor M1 in the light emitting stage in the first mode is different from the bias condition of the driving transistor M1 in the light emitting stage in the second mode, at this time, if the time length of each bias adjustment sub-stage Tc' is the same, the number of bias adjustment sub-stages Tc' included in the bias adjustment stage Tc can be adjusted so that the total time length of the bias adjustment stage Tc in the first mode and the second mode is different, so that the bias adjustment condition of the driving transistor M1 in the first mode and the second mode can be adjusted, thereby facilitating the realization of the display uniformity of the display panel in different working modes.

[0129] In another optional embodiment, Figure 19 is another driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present application, referring to Figure 13 and Figure 19 the time length of each bias adjustment sub-stage Tc' in the first mode is different from the time length of each bias adjustment sub-stage Tc' in the second mode; and the number of bias adjustment sub-stages Tc' in each bias adjustment stage Tc in the first mode is the same as the number of bias adjustment sub-stages Tc' in each bias adjustment stage Tc in the second mode.

[0130] Specifically, when the time length of the bias adjustment sub-stage Tc' in different working modes is set to be different, but the number of bias adjustment sub-stages Tc' in each bias adjustment stage Tc is the same, the time length of the bias adjustment stage Tc in different working modes can also be made different, so that the bias state of the driving transistor M1 in different working modes can be adjusted differently, thereby facilitating the realization of the display uniformity of the display panel in different working modes.

[0131] Optionally, in the same first non-light emitting stage, the termination time of the bias adjustment stage is located before the termination time of the first non-light emitting stage.

[0132] Exemplarily, referring to Figure 13 and Figure 19As shown, in the first non-light emitting stage Tb10, the driving transistor M1 stops providing the driving current to the light emitting element 200, and the light emitting element 200 does not emit light; when the first non-light emitting stage Tb10 ends, the light emitting stage Ta is entered again, and the driving transistor M1 needs to provide the driving current to the light emitting element 200. When the first non-light emitting stage Tb10 ends and the light emitting stage Ta is entered again, the source of the driving transistor M1 needs to receive the positive power signal PVDD, and generate the corresponding driving current based on the positive power signal PVDD and the gate potential of the driving transistor M1. In this way, by setting the end time of the bias adjustment stage Tc before the end time of the first non-light emitting stage Tb10, when the next light emitting stage Ta comes, the bias adjustment signal Vpark is stopped from being provided to the source and / or the drain of the driving transistor M1, so as to prevent the bias adjustment signal from affecting the writing of the positive power signal PVDD, and cause the driving transistor M1 to fail to accurately generate the driving current, thereby improving the accuracy of the driving current generated by the driving transistor M1, and improving the accuracy of the display and light emission of the light emitting element 200, and further improving the display quality of the display panel.

[0133] It can be understood that, in the embodiment of the present application, the first non-light emitting stage can be the first non-light emitting stage of a frame of picture, or can be another non-light emitting stage of a frame of picture, as long as the bias adjustment of the driving transistor M1 can be realized, which is not limited in the embodiment of the present application.

[0134] It can be understood that, in the embodiment of the present application, the first non-light emitting stage can be the first non-light emitting stage of a frame of picture, or can be another non-light emitting stage of a frame of picture, as long as the bias adjustment of the driving transistor M1 can be realized, which is not limited in the embodiment of the present application. Figure 13 Figure 19 In an optional embodiment, the above description is continued by referring to Figure 13 and Figure 19 , the first non-light emitting stage Tb10 is located after at least part of the light emitting stage Ta in a frame of picture of the display panel.

[0135] Specifically, in the light emitting stage Ta, the source of the driving transistor M1 receives the positive power signal PVDD, so that the driving transistor M1 generates a driving current, and the driving current generated by the driving transistor charges the node N3 electrically connected to the drain of the driving transistor, so that the drain potential of the driving transistor is equivalent to the potential charged to the third node. During this period, there is a difference between the gate potential of the driving transistor M1 and the source and drain potentials of the driving transistor M1, which causes the ion polarization inside the driving transistor M1, and further causes the formation of an internal built-in electric field inside the driving transistor M1, which causes the threshold voltage of the driving transistor to continuously drift, so that the driving transistor M1 is biased, that is, the driving transistor M1 needs to be biased. At this time, by setting the first non-light emitting stage Tb10 after at least part of the light emitting stage Ta, the bias adjustment stage of the first non-light emitting stage Tb10 can be entered after the driving transistor M1 is biased for a period of time, so as to adjust the bias of the driving transistor M1, thereby ensuring that the driving transistor M1 can accurately provide a driving current in the next light emitting stage Ta, ensuring that the light emitting element 200 accurately emits light, and further improving the display effect of the display panel.

[0136] On the basis of the above-mentioned embodiments, with reference to any one of the accompanying drawings, Figure 2-3 , Figure 10-11 , and Figure 13-14 The pixel circuit 100 can further include a reset module 17, which can provide a reset signal Vref2 to the anode of the light emitting element 200 in a reset stage to reset the anode of the light emitting element 200, so as to prevent the signal provided to the anode of the light emitting element 200 in the previous light emitting stage from affecting the light emitting accuracy of the light emitting element 200 in the next light emitting stage. Therefore, the reset stage in which the reset module 17 provides the reset signal Vref2 to the light emitting element 200 should be located in a non-light emitting stage before the light emitting stage, for example, the data writing stage can be multiplexed as the reset stage, and at this time, the scan signal S-P used to control the data writing module 12 can be multiplexed as the scan signal used to control the reset module 17.

[0137] In an exemplary embodiment, one end of the reset module 17 can receive a reset signal Vref2, and the other end can be electrically connected to the anode of the light emitting element 200. The reset module 17 can be turned on or off under the control of the scan signal S-P, and when the reset module 17 is turned on under the control of the scan signal S-P, the reset module 17 can transmit the reset signal Vref2 to the anode of the light emitting element 200 to reset the light emitting element 200. At this time, the reset module 17 can include a reset transistor M8, the gate of the reset transistor M8 can receive the scan signal S-P, the first pole of the reset transistor M8 receives the reset signal Vref2, and the second pole of the reset transistor M8 is electrically connected to the anode of the light emitting element 200. The reset transistor M8 can be an NMOS transistor or a PMOS transistor. When the reset transistor M8 is an NMOS transistor, the reset transistor M8 is turned on when the scan signal S-P is high, and the reset transistor M8 is turned off when the scan signal S-P is low. Conversely, when the reset transistor M8 is a PMOS transistor, the reset transistor M8 is turned on when the scan signal S-P is low, and the reset transistor M8 is turned off when the scan signal S-P is high. The type of reset transistor M8 is not limited in the embodiment of the application.

[0138] The reset signal Vref2 and the initialization signal Vref1 can be the same or different, and the embodiment of the application does not make specific limitations on this premise that the driving transistor M1 can be accurately initialized and the anode of the light emitting element 200 can be accurately reset.

[0139] In addition, with reference to Figure 2-3 , FIG. 1, and any of the accompanying drawings, the pixel circuit 100 can further include a storage capacitor C, which can be used to store the gate potential of the driving transistor M1. The specific connection mode of the storage capacitor C can be determined according to specific circumstances, and the connection mode of the storage capacitor is not limited in the embodiment of the application on the premise that the storage of the gate potential of the driving transistor M1 can be achieved.

[0140] Based on the same inventive concept, the embodiment of the present application further provides a driving method of a display panel, which is used for driving the display panel provided by the embodiment of the present application, and the display panel comprises at least a pixel circuit and a light emitting element; the pixel circuit comprises at least a driving module and a bias adjustment module; the driving module is used for providing a driving current for the light emitting element in a light emitting stage; the driving module comprises a driving transistor; the bias adjustment module is used for providing a bias adjustment signal for the source and / or drain of the driving transistor in a bias adjustment stage; one frame of picture time of the display panel comprises at least one light emitting stage and at least one non-light emitting stage; at least part of the non-light emitting stage is a first non-light emitting stage; the first non-light emitting stage comprises the bias adjustment stage; in the same first non-light emitting stage, the time between the end time of the bias adjustment stage and the end time of the first non-light emitting stage is a bias maintenance stage.

[0141] The driving method of the display panel provided by the embodiment of the present application can be executed by a driving chip in the display device provided by the embodiment of the present application, and the driving chip can be arranged in a non-display area of the display panel to drive the display panel provided by the embodiment of the present application. Figure 20 is a flowchart of a driving method of a display panel provided by the embodiment of the present application, referring to Figure 20 , the driving method specifically comprises:

[0142] S110, acquiring a display mode of the display panel.

[0143] The display panel can comprise multiple working modes, for example, a first mode and a second mode, wherein the brightness of the first mode and the second mode is different.

[0144] Specifically, the corresponding relationship between the display light emitting brightness level (for example, 0-255 gray scale) of the light emitting element in the display panel and the voltage of the data signal is different in different working modes, or the duty cycle of the light emitting stage of the display panel is different, so that the display brightness finally presented by the display panel is different. When the display panel presents different brightness, the data signal provided to the driving transistor is different, or the light emitting duration of the light emitting element is different, resulting in different bias conditions of the driving transistor, i.e., different threshold voltage drift conditions of the driving transistor. When the display panel displays one frame of picture, the working mode of the display panel can be pre-acquired or displayed when the frame of picture is displayed, so that the driving transistor can be biased and adjusted to different degrees according to different working modes.

[0145] S120, determining the time length of the bias adjustment stage and the time length of the bias maintenance stage according to the display mode.

[0146] At least one of the length of time of the bias adjustment stage and the length of time of the bias maintaining stage is different when the display mode of the display panel is the first mode and when the display mode of the display panel is the second mode.

[0147] Specifically, when the data signal has been written to the gate of the driving transistor before the bias adjustment stage, for example, the gate potential of the driving transistor only includes the data signal, in the bias adjustment stage, the bias adjustment module provides a bias adjustment signal to the source and / or the drain of the driving transistor, so that the voltage difference between the gate and the source and / or the drain of the driving transistor is the difference between the data signal and the bias adjustment signal; in the bias maintaining stage, although the bias adjustment module stops providing the bias adjustment signal to the source and / or the drain of the driving transistor, the source and / or the drain of the driving transistor still remains equivalent to the bias adjustment signal because no other signal is provided to the source and / or the drain of the driving transistor. In this way, in the bias adjustment stage and the bias maintaining stage, the voltage difference between the gate and the source and / or the drain of the driving transistor is the voltage difference between the data signal and the bias adjustment signal, so that in the bias adjustment stage and the bias maintaining stage, the threshold voltage drift generated by the driving transistor in the light-emitting stage before the bias adjustment stage can be alleviated or offset. At the same time, based on the difference in brightness in different working modes, i.e., the difference in threshold voltage drift of the driving transistor in different working modes, the bias state of the driving transistor can be adjusted differently in different modes to adjust the bias state of the driving transistor in each working mode. In addition, under the premise of being able to adjust the bias state of the driving transistor in each working mode, the voltage of the bias adjustment signal provided by the bias adjustment module does not need to be changed, so that additional power consumption caused by repeated charging and discharging of the circuit, signal line, etc. due to the voltage change of the bias adjustment signal can be reduced, thereby reducing the power consumption of the display panel while ensuring the display uniformity of the display panel.

[0148] S130, according to the length of time of the bias adjustment stage and the length of time of the bias maintaining stage, control the time when the bias adjustment module provides the bias adjustment signal to the source and / or the drain of the driving transistor.

[0149] Specifically, in different working modes, i.e., the first mode and the second mode, the time length of the bias adjustment stage and / or the bias maintaining stage is different, at this time, the time length of the bias adjustment stage in the first mode and the second mode can be the same, but the bias maintaining stage is different, at this time, the time length of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor is the same, but the relative time of the start time and the end time of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor and the end time of the first non-emitting stage is different; or, the time length of the bias adjustment stage in the first mode and the second mode is different, but the bias maintaining stage is the same, at this time, the time length of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor is different, but the relative time of the end time of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor and the end time of the first non-emitting stage is the same; or, the time length of the bias adjustment stage in the first mode and the second mode is different, and the bias maintaining stage is also different, at this time, the time length of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor is different, and the relative time of the start time and the end time of the bias adjustment module providing the bias adjustment signal to the source and / or the drain of the driving transistor and the end time of the first non-emitting stage is also different.

[0150] It can be understood that the time length relationship of the bias adjustment stage and the bias maintaining stage in different working modes of the display panel can be set according to actual needs, and the embodiments of the present application do not make specific limitations.

[0151] In summary, when the display panel is in different modes, the display panel presents different display brightness, and when the display panel presents different display brightness, the gate voltage of the driving transistor is different, at this time, by controlling at least one of the bias adjustment stage and the bias position stage in different brightness modes to be different, the source and / or the drain of the driving transistor can be kept for different time lengths of the bias adjustment signal, so as to adjust the bias state of the driving transistor in each brightness mode, thereby ensuring the display uniformity in different brightness modes. In addition, under the premise of controlling at least one of the bias adjustment stage and / or the bias maintaining stage in different brightness modes to be different to adjust the bias state of the driving transistor in each brightness mode, the bias adjustment signal provided by the driving chip does not need to be changed, thereby being able to reduce the additional power consumption caused by the repeated charging and discharging of the circuit, the signal line and the like due to the change of the bias adjustment signal, and further ensuring the display effect of the display panel under the premise of improving the display uniformity of the display panel.

[0152] It can be understood that, according to the display mode, the way of determining the time length of the bias adjustment stage and the time length of the bias maintenance stage can be determined based on an experimentally determined display mode and bias adjustment stage time length and bias maintenance stage time length relationship table, or can be determined based on other ways.

[0153] In an optional embodiment, Figure 21 is a flowchart of a bias maintenance stage time length determination method provided by an embodiment of the application, and the method comprises:

[0154] S121, determining the current brightness of the display panel according to the display mode.

[0155] Specifically, after determining the current display mode of the display panel, the display brightness expected to be presented by the display panel in the current display mode can be known; the display brightness expected to be presented DBV is the display brightness presented by the display panel when the driving module of each pixel circuit drives the light emitting element to emit light after the display panel provides the highest brightness level corresponding data signal to each pixel circuit in the working mode.

[0156] S122, determining the time length of the bias maintenance stage corresponding to the current brightness of the display panel based on the relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel.

[0157] Wherein, the time length t of the bias maintenance stage and the display brightness DBV satisfy the following relationship:

[0158]

[0159] DBV1 is the brightness of the display panel in the first mode, t1 is the time length of the bias maintenance stage in the first mode; DBV2 is the brightness of the display panel in the second mode, t2 is the time length of the bias maintenance stage in the second mode; T is the time length of the first non-emitting stage.

[0160] It can be understood that the DBV1 can be the display brightness of the display panel when the highest brightness level corresponding data signal is provided to each pixel circuit of the display panel in the first mode; the DBV2 can be the display brightness of the display panel when the highest brightness level corresponding data signal is provided to each pixel circuit of the display panel in the second mode. For example, by adjusting the relationship between the gray scale and the data signal, the display panel presents different brightness in different working modes, and the light emitting brightness level of the light emitting element includes 0-255 gray scales, for the same pixel circuit, the data signal corresponding to 255 gray scales in the first mode is different from the data signal corresponding to 255 gray scales in the second mode; in one mode, the data signal corresponding to 255 gray scales is provided to each pixel circuit of the display panel, so that the display brightness of the display panel is DBV1; in the second mode, the data signal corresponding to 255 gray scales is provided to each pixel circuit of the display panel, so that the display brightness of the display panel is DBV2. In this way, by providing the data signal corresponding to 255 gray scales to each pixel circuit of the display panel respectively, and driving the light emitting element to emit light by the driving module of each pixel circuit, the display brightness of the display panel in different working modes can be measured by using the corresponding brightness test equipment.

[0161] Correspondingly, in the first mode, after the data signal corresponding to 255 gray scales in the mode is provided to each pixel circuit of the display panel, the length of time of the bias maintaining stage is adjusted, so that the brightness of the display panel is DBV1 when the light emitting element emits light in the light emitting stage, at this time, the length of time of the bias maintaining stage is the length of time t1 of the bias maintaining stage that should be set in the first mode; similarly, in the second mode, after the data signal corresponding to 255 gray scales in the mode is provided to each pixel circuit of the display panel, the length of time of the bias maintaining stage is adjusted, so that the brightness of the display panel is DBV2 when the light emitting element emits light in the light emitting stage, at this time, the length of time of the bias maintaining stage is the length of time t2 of the bias maintaining stage that should be set in the second mode.

[0162] It should be noted that in the actual test process, the length of time of the bias maintaining stage corresponding to each working mode can be determined respectively for different working modes, so as to determine the relationship curve between the brightness and the bias maintaining stage, and the corresponding relationship formula is determined based on the relationship curve.

[0163] For example, the display brightness DBV and the length of time t of the bias maintaining stage Td satisfy a linear relationship, at this time, the brightness linear relationship formula can be determined based on the brightness DBV1 of the display panel in the first mode and the length of time t1 of the bias maintaining stage Td1, and the brightness DBV2 of the display panel in the second mode and the length of time t2 of the bias maintaining stage Td2. Thus, when a frame is displayed on the display panel, the operating mode of the display panel can be known in advance, that is, the DBV corresponding to the frame can be determined in advance. Substituting the DBV into the above relationship, a time t0 can be determined. Based on the time t0, the upper limit of the bias maintenance stage t corresponding to this operating mode can be determined as t0+0.25*T, and the lower limit is t0-0.25*T. Based on this, the duration t of the bias maintenance stage Td required under any display brightness DBV can be derived. At the same time, by making the duration t of the bias maintenance stage Td take values ​​in the range of t0-0.25*T to t0+0.25*T, the bias maintenance stage Td can meet different display control requirements within the first non-light-emitting stage Tb.

[0164] In an optional embodiment, after determining the duration of the bias maintenance phase, the duration t of the bias maintenance phase can be corrected based on the time correction formula of the bias maintenance phase to determine the corrected duration t′ of the bias maintenance phase.

[0165] The time correction formula for the bias maintenance phase is as follows:

[0166] or,

[0167] for The floor value is H = 1 / (F*Lines), where F is the refresh rate of the display panel and Lines is the number of rows of pixel circuits in the display panel.

[0168] For example, when the bias adjustment module includes a bias adjustment transistor, and the bias adjustment transistor is turned on or off under the control of the bias adjustment control signal, the bias adjustment control signal is provided by the corresponding shift register circuit. The bias adjustment control signal output by each shift register unit of the shift register circuit can scan the pixel circuit line by line, and the scanning time of each row of pixel circuits by the shift register circuit is controlled by the line synchronization signal. At this time, according to the above linear relationship between brightness and bias maintenance phase, the duration t of a bias maintenance phase can be determined, so as to further determine the start and end times of the bias adjustment phase. However, since there are cases where the duration t of the bias maintenance phase is not an integer multiple of the scanning time of a row of pixel circuits, a complex control method is required to achieve the shifting of the bias adjustment phase when the display panel switches modes.

[0169] Based on the above problems, after determining the time length of the bias maintaining stage corresponding to the current frame picture, the time of the bias maintaining stage Td calculated by the linear relationship between the brightness and the bias maintaining stage is corrected by using the time correction relationship of the bias maintaining stage, so that the time t of the corrected bias maintaining stage Td is an integer multiple of the time length H of scanning a row of pixel circuits, thereby when the mode of the display panel is switched, the length of the row synchronization signal does not need to be changed, only a simple translation of one or more control signals provided to the shift register circuit is needed, thereby facilitating the simplification of the control mode of the display panel, improving the mode switching speed of the display panel, and facilitating the high-quality display requirements of the display panel.

[0170] It should be noted that the relationship between the time length t of the bias maintaining stage and the display brightness DBV can be used to determine the time length of the bias maintaining stage under each display brightness DBV. Generally, the display brightness of the display panel has N levels, for example, N can be equal to 4096, each level corresponds to a display brightness DBV, if the relationship is used to calculate the time length of the bias maintaining stage for each level, the workload of the driving chip for executing the driving method of the display panel will be increased.

[0171] In an optional embodiment, when the time length of the bias maintaining stage corresponding to the current brightness of the display panel is determined based on the relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel, the brightness interval corresponding to the current brightness of the display panel can be determined first, and then the time length of the bias maintaining stage corresponding to the brightness reference value corresponding to the brightness interval is determined. Figure 22 is a flowchart of another bias maintaining stage time length determination method provided by the embodiment of the application, and the method further comprises:

[0172] S1221, determining whether the current brightness of the display panel is less than or equal to a first preset brightness; if yes, performing S1222; if no, performing S1223.

[0173] The first preset brightness can be any brightness value between 50 nit and 100 nit, for example, the first preset brightness is 50 nit, and when the brightness of the display panel is between 0 nit and 50 nit, the time length of the bias maintenance stage corresponding to each brightness level can be determined respectively, so as to adjust the bias of the drive transistor to different degrees. It should be noted that the above is only an example of the value of the first preset brightness, and the first preset brightness can be a larger or smaller value according to the display requirements of the display panel, and the embodiments of the present application do not make specific limitations thereto.

[0174] In S1222, the current brightness of the display panel is substituted into the relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel to determine the time length of the bias maintenance stage corresponding to the current brightness of the display panel.

[0175] Specifically, when it is determined that the current brightness of the display panel is less than or equal to the first preset brightness, the current brightness of the display panel can be directly substituted into the relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel, so as to determine the time length of the bias maintenance stage corresponding to the current display brightness, so as to ensure that the bias state of the drive transistor can be adjusted according to the current brightness, so that the drive transistor can provide accurate drive current to the light emitting element, and thus the light emitting element can emit light accurately.

[0176] In an exemplary embodiment, if the first preset brightness is 50 nit and the current display brightness is 20 nit, 20 nit can be directly substituted into the relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel, and the corresponding time t0 can be calculated. According to the calculated time t0, the value range of the bias maintenance stage t corresponding to the current brightness DBV can be determined, that is, [t0-0.25*T, t0+0.25*T].

[0177] In S1223, the current brightness of the display panel belongs to a brightness interval.

[0178] In S1224, the brightness reference value corresponding to the current brightness of the display panel is determined according to the brightness interval to which the current brightness of the display panel belongs.

[0179] The first preset brightness is greater than a second preset brightness. The brightness greater than the first preset brightness forms at least one brightness interval. Each brightness interval includes at least two brightnesses that are consecutive in level. The brightnesses in the same brightness interval correspond to the same brightness reference value. The brightnesses in different brightness intervals correspond to different brightness reference values.

[0180] Specifically, when the current brightness is greater than the first preset brightness, the sensitivity of the human eye to the brightness changes in a leap. The change of the display brightness from one display brightness interval to multiple display brightnesses is perceived by the human eye, that is, the sensitivity of the human eye to the brightness change at this time is low. At this time, the bias of the driving transistor can be adjusted according to the brightness interval. That is, when it is determined that the current brightness is greater than the first preset brightness, the brightness interval in which the current brightness is located is determined, the length of time of the corresponding bias maintenance stage is derived through the brightness reference value in the brightness interval, and then the driving transistor is biased and adjusted. Based on this, the bias of the driving transistor is adjusted according to the brightness interval, which not only ensures the display effect of the display panel, but also reduces the workload of the driving chip and improves the processing efficiency.

[0181] For example, the first preset brightness can be any brightness value between 50 nit and 100 nit. Taking the brightness of the display panel as 150 nit as an example, the brightness interval in which the 150 nit brightness value is located is obtained, that is, 100 nit-200 nit. Based on this, the brightness reference value of the determined brightness interval 100 nit-200 nit is determined. Taking the brightness reference value of 150 nit as an example, the length of time of the corresponding bias maintenance stage is obtained by substituting 150 nit into the formula, and then the driving transistor is biased and adjusted. In the case of determining the brightness interval, the length of time t of the maintenance stage under different display brightness DBV can no longer be adjusted step by step. The length of time t of the maintenance stage is obtained through the brightness reference value of the brightness interval, which can reduce the workload of the driving chip and improve the operation speed and processing efficiency.

[0182] In an optional embodiment, if the brightness interval includes a first brightness interval and a second brightness interval, and the brightness in the first brightness interval is less than the brightness in the second brightness interval, the brightness reference value corresponding to the second brightness interval should be greater than the brightness reference value corresponding to the first brightness interval.

[0183] Specifically, when the luminance in the first mode is less than the luminance in the second mode, and the luminance in the first mode belongs to the first luminance interval and the luminance in the second mode belongs to the second luminance interval, the luminance reference value corresponding to the luminance in the first mode can be the first luminance reference value, and the luminance reference value corresponding to the luminance in the second mode can be the second luminance reference value. At this time, for the case that the driving transistor is a PMOS transistor, the data signals corresponding to the same gray scale written to the driving transistor in the first mode and in the second mode are different, that is, the data signal written to the driving transistor in the first mode is greater than the data signal written to the driving transistor in the second mode, so that the threshold drift of the driving transistor in the first mode is less than the threshold drift of the driving transistor in the second mode. At this time, when the bias adjustment is performed, the bias maintenance time in the first mode can be set to be less than the bias maintenance time in the second mode. Based on the above relationship, it can be known that the greater the value of DBV substituted is, the smaller the t0 calculated is. Therefore, by making the luminance reference value corresponding to the one with greater luminance in the luminance interval greater than the luminance reference value corresponding to the one with smaller luminance in the luminance interval, it is beneficial to adjust the bias of the driving transistor under different luminances in different luminance intervals.

[0184] In an exemplary embodiment, when the first luminance interval is 100 nit to 150 nit, and the second luminance interval is 150 nit to 300 nit, the luminance reference value of the first luminance interval can be 100 nit, and the luminance reference value of the second luminance interval can be 150 nit.

[0185] It can be understood that the above only exemplarily illustrates that the luminance reference value corresponding to each luminance interval is the lower limit value of the luminance interval, and in other embodiments, the luminance reference value corresponding to each luminance interval can be the upper limit value of the luminance interval, for example, the luminance reference value of the first luminance interval can be 150 nit, and the luminance reference value of the second luminance interval can be 300 nit; or, in other embodiments, the luminance reference value corresponding to each luminance interval can also be the middle value of the luminance interval, for example, the luminance reference value of the first luminance interval can be 125 nit, and the luminance reference value of the second luminance interval can be 275 nit; or, in other embodiments, the luminance reference value corresponding to each luminance interval can also be the average value of each luminance in the luminance interval, etc., and the embodiments of the present application do not make specific limitations thereon.

[0186] It should be noted that the first luminance interval and the second luminance interval not only refer to two luminance intervals, but also refer to two different luminance intervals, and the embodiments of the present application only exemplarily illustrate the first luminance interval and the second luminance interval.

[0187] In other optional embodiments, each luminance greater than the first preset luminance can belong to the same luminance interval, and the luminance reference value corresponding to the luminance interval is the first preset luminance.

[0188] Specifically, at a higher display luminance, the sensitivity of the human eye to luminance changes is relatively low, so when the current luminance interval exceeds the first preset luminance, it can be considered that the luminance under the current working mode is high, and the luminance change caused by the different degrees of bias of the driving transistor will not be perceived by the human eye. At this time, each luminance greater than the first preset luminance can be determined as one luminance interval, and at this time, each luminance greater than the first preset luminance corresponds to one luminance reference value, which can be the lower limit of the luminance interval, i.e., the first preset luminance. In this way, while ensuring the display effect, the calculation process of the time length t of the bias maintenance stage can be simplified, the workload of the calculation of the driving chip can be reduced, and the processing efficiency can be improved.

[0189] S1225, substituting the luminance reference value into the relationship between the time length t of the bias maintenance stage and the luminance DBV of the display panel to determine the time length of the bias maintenance stage corresponding to the current luminance of the display panel.

[0190] Specifically, since each luminance interval includes at least two continuous luminances, at this time, when the luminance of the display panel changes within a small range, it can be considered that it belongs to the same luminance interval and corresponds to the same luminance reference value. Using the luminance reference value can calculate the same time length range of the bias maintenance stage, so that when the luminance of the display panel changes within a small range, the luminance change caused by the bias of the driving transistor will not be recognized by the human eye, and there is no need to adjust the time length range of the bias maintenance stage, and the display effect of the display panel can also be ensured. In this way, after determining the luminance interval in which the current display luminance DBV is located based on the current display luminance DBV, the luminance reference value corresponding to the luminance interval can be substituted into the above relationship to determine the time length t of the bias maintenance stage under the current luminance.

[0191] Optionally, when the luminance interval includes a first luminance interval and a second luminance interval, and the luminance in the first luminance interval is less than the luminance in the second luminance interval; the number of levels of luminance contained in the second luminance interval is greater than the number of levels of luminance contained in the first luminance interval.

[0192] Specifically, at a lower brightness, the human eye is more sensitive to changes in brightness, and thus a small degree of jump in the brightness level is not easily recognized by the human eye, but a large degree of jump in the brightness level can be recognized by the human eye. At a higher brightness, the human eye is less sensitive to changes in brightness, and a large degree of jump in the brightness level is also not easily recognized by the human eye. Thus, when the brightness in the first brightness interval is less than the brightness in the second brightness interval, by differentiating the number of brightness levels in different brightness intervals, the number of levels in the adaptive increased brightness interval is increased as the brightness contained in the brightness interval is increased, for example, the number of levels in the first brightness interval is set to be less than the number of levels in the second brightness interval, so that the adjustment of the length of time of the bias maintenance stage is more rough, so as to reduce the calculation cost of the length of time of the bias maintenance stage while meeting the recognition degree of the display brightness by the human eye, and also ensure the display effect of the display panel.

[0193] For example, the first brightness interval is 100 nit to 150 nit, and 1000 brightness levels can be included in the brightness interval; the second brightness interval is 150 nit to 300 nit, and 2000 brightness levels can be included in the brightness interval; that is, when the brightness in the first brightness interval is less than the brightness in the second brightness interval, the brightness level in the first brightness interval is also less than the brightness level in the second brightness interval, and the size of the brightness interval and the number of brightness levels are not specifically limited by the embodiments of the present application.

[0194] Based on the same inventive concept, the embodiments of the present application also provide a display device, which comprises the display panel provided by the embodiments of the present application. Therefore, the display device has the technical features of the display panel and the driving method provided by the embodiments of the present application, and can achieve the beneficial effects of the display panel provided by the embodiments of the present application. The same parts can be referred to the description of the display panel provided by the embodiments of the present application, which will not be repeated here.

[0195] For example, Figure 23 is a structural schematic diagram of a display device provided by an embodiment of the present application, as Figure 23 shown, the display device 1 comprises the display panel 10 provided by the embodiments of the present application. The display device 1 provided by the embodiments of the present application can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., and the embodiments of the present application do not make special limitation thereto.

[0196] It should be understood that the order of the stages of the operation of the various forms of pixel circuit shown above can be reordered, added to, or deleted from without departing from the scope of the application. For example, the stages of the operation of the various pixel circuits described in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application are achieved, which is not limited herein.

[0197] The specific implementation described above does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a bias adjustment module; the driving module is configured to provide a driving current for the light emitting element in a light emitting stage; the driving module comprises a driving transistor; the bias adjustment module is configured to provide a bias adjustment signal for a source electrode and / or a drain electrode of the driving transistor in a bias adjustment stage; one frame of the display panel comprises at least one light emitting stage and at least one non-light emitting stage; at least part of the non-light emitting stage is a first non-light emitting stage; the first non-light emitting stage comprises the bias adjustment stage; in the same first non-light emitting stage, the time between the end time of the bias adjustment stage and the end time of the first non-light emitting stage is a bias maintenance stage; the working module of the display panel comprises a first mode and a second mode; the brightness of the display panel in the first mode is different from the brightness of the display panel in the second mode; at least one of the time length of the bias adjustment stage and the time length of the bias maintenance stage in the first mode is different from that in the second mode; the brightness DBV of the display panel and the time length t of the bias maintenance stage satisfy a linear relationship; the time of the bias maintenance stage calculated by using the linear relationship of the brightness and the bias maintenance stage is corrected, so that the time of the corrected bias maintenance stage is an integer multiple of the time of the bias adjustment stage.

2. The display panel of claim 1, wherein, The relationship between the time length t of the bias maintenance stage and the brightness DBV of the display panel is: ； wherein DBV1 is the brightness of the display panel in the first mode, t1 is the time length of the bias maintenance stage in the first mode; DBV2 is the brightness of the display panel in the second mode, t2 is the time length of the bias maintenance stage in the second mode; T is the time length of the first non-light emitting stage.

3. The display panel of claim 2, wherein, The time correction relationship of the bias maintenance stage is: ； Wherein t' is the time of the corrected bias maintaining stage, is the floor value of H=1 / (F*Lines), F is the refresh frequency of the display panel, and Lines is the number of rows of the pixel circuit in the display panel.

4. The display panel of claim 1, wherein, the bias adjustment module is electrically connected between a bias adjustment signal end and a first electrode of the driving transistor; the first electrode of the driving transistor is the source electrode or the drain electrode of the driving transistor; each bias adjustment stage comprises at least two bias adjustment sub-stages; in each bias adjustment sub-stage, the bias adjustment module is turned on; in the time period between adjacent two bias adjustment sub-stages, the bias adjustment module is turned off.

5. The display panel of claim 4, wherein, the time length of each bias adjustment sub-stage in the first mode is the same as that in the second mode; the number of bias adjustment sub-stages in each bias adjustment stage in the first mode is different from that in the second mode.

6. The display panel of claim 4, wherein, the time length of each bias adjustment sub-stage in the first mode is different from that in the second mode; the number of bias adjustment sub-stages in each bias adjustment stage in the first mode is the same as that in the second mode.

7. The display panel of claim 1, wherein, The pixel circuit further comprises a data writing module; The data writing module is configured to provide a data signal to the gate of the driving transistor in a data writing stage; The non-emitting stage of one frame of the display panel comprises the data writing stage; The time of the data writing stage and the time of the bias adjusting stage do not overlap in the same pixel circuit.

8. The display panel of claim 7, wherein, The data writing module is multiplexed as the bias adjusting module.

9. The display panel of claim 1, wherein, The termination time of the bias adjusting stage is before the termination time of the first non-emitting stage in the same first non-emitting stage.

10. The display panel of claim 1, wherein, The first non-emitting stage is located after at least part of the emitting stage in one frame of the display panel.

11. The display panel of claim 1, wherein, The voltage of the bias adjusting signal in the first mode is the same as the voltage of the bias adjusting signal in the second mode.

12. A driving method of a display panel, characterized by, The display panel comprises a pixel circuit and an emitting element; the pixel circuit comprises a driving module and a bias adjusting module; the driving module is configured to provide a driving current for the emitting element in an emitting stage; the driving module comprises a driving transistor; the bias adjusting module is configured to provide a bias adjusting signal for the source and / or drain of the driving transistor in a bias adjusting stage; one frame of the display panel comprises at least one emitting stage and at least one non-emitting stage; at least part of the non-emitting stage is a first non-emitting stage; the first non-emitting stage comprises the bias adjusting stage; the termination time of the bias adjusting stage and the termination time of the first non-emitting stage are separated by a bias maintaining stage in the same first non-emitting stage. The driving method of the display panel comprises: acquiring a display mode of the display panel; the display mode comprises at least a first mode and a second mode with different brightnesses; determining the time length of the bias adjusting stage and the time length of the bias maintaining stage according to the display mode; wherein at least one of the time length of the bias adjusting stage and the time length of the bias maintaining stage is different when the display mode of the display panel is the first mode and when the display mode of the display panel is the second mode; controlling the bias adjusting module to provide a bias adjusting signal to the source and / or drain of the driving transistor according to the time length of the bias adjusting stage and the time length of the bias maintaining stage; the brightness DBV of the display panel and the time length t of the bias maintaining stage satisfy a linear relationship; the time of the bias maintaining stage calculated by the linear relationship between brightness and bias maintaining stage is corrected so that the corrected time of the bias maintaining stage is an integer multiple of the time of the bias adjusting stage.

13. The driving method of the display panel according to claim 12, wherein determining the time length of the bias maintaining stage according to the display mode, comprises: determining the current brightness of the display panel according to the display mode; determining the time length of the bias maintaining stage corresponding to the current brightness of the display panel based on a relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel, wherein the relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel is: ； DBV1 is the brightness of the display panel in the first mode, t1 is the time length of the bias maintaining stage in the first mode; DBV2 is the brightness of the display panel in the second mode, t2 is the time length of the bias maintaining stage in the second mode; T is the time length of the first non-emitting stage.

14. The driving method of the display panel according to claim 13, wherein After determining the bias adjustment time of the driving transistor according to the display mode, the method further comprises: correcting the time length t of the bias maintaining stage based on a time correction relationship of the bias maintaining stage, and determining the corrected time length t' of the bias maintaining stage, wherein the time correction relationship of the bias maintaining stage is: ； for The floor value is H = 1 / (F*Lines), where F is the refresh rate of the display panel and Lines is the number of rows of the pixel circuits in the display panel.

15. The driving method of the display panel according to claim 13, wherein determining the time length of the bias maintaining stage corresponding to the current brightness of the display panel based on a relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel, comprising: determining whether the current brightness of the display panel is less than or equal to a first preset brightness; If yes, substituting the current brightness of the display panel into the relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel to determine the time length of the bias maintaining stage corresponding to the current brightness of the display panel.

16. The driving method of the display panel according to claim 15, wherein determining the time length of the bias maintaining stage corresponding to the current brightness of the display panel based on a relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel, further comprising: If the current brightness of the display panel is greater than the first preset brightness, determining the brightness interval to which the current brightness of the display panel belongs; each of the brightness greater than the first preset brightness constitutes at least one brightness interval; each of the brightness intervals comprises at least two brightness levels that are continuous in rank; each of the brightness in the same brightness interval corresponds to a same brightness reference value; the brightness in different brightness intervals correspond to different brightness reference values; determining the brightness reference value corresponding to the current brightness of the display panel according to the brightness interval to which the current brightness of the display panel belongs; substituting the brightness reference value into the relationship between the time length t of the bias maintaining stage and the brightness DBV of the display panel to determine the time length of the bias maintaining stage corresponding to the current brightness of the display panel.

17. The driving method of the display panel according to claim 16, wherein The brightness interval comprises a first brightness interval and a second brightness interval; the brightness in the first brightness interval is less than the brightness in the second brightness interval. The number of levels of the brightness included in the second brightness interval is greater than the number of levels of the brightness included in the first brightness interval.

18. The driving method of the display panel according to claim 16, wherein The brightness interval comprises a first brightness interval and a second brightness interval; the brightness in the first brightness interval is less than the brightness in the second brightness interval. The brightness interval comprises a first brightness interval and a second brightness interval; the brightness in the first brightness interval is less than the brightness in the second brightness interval. The luminance reference value corresponding to the second luminance interval is greater than the luminance reference value corresponding to the first luminance interval.

19. The driving method of the display panel according to claim 15, wherein Each luminance greater than the first preset luminance belongs to the same luminance interval. The luminance reference value corresponding to the luminance interval is the first preset luminance.

20. A display device, characterized in that, Comprising: The display panel of any one of claims 1-11.

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