Pixel and display device including same

Abstract

Provided are a pixel and a display device, the pixel including: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color. Each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a pulse width modulator that controls the width of the drive current. The first sub-pixel and the second sub-pixel share a pulse amplitude modulator that controls the amplitude of the drive current.

Description

Technical Field

[0001] This disclosure generally relates to display devices. More specifically, this disclosure relates to pixels including subpixels and display devices including such pixels. Background Technology

[0002] Multiple pixels can exist in a display device to display an image. Each pixel can include multiple subpixels that display different colors.

[0003] To make pixels display accurate and uniform colors, the number of components included in a pixel (e.g., transistors, capacitors, etc.) can be increased. While the pixel size can increase as the number of components increases, this limits the ability to increase the resolution of a display device. Utility Model Content

[0004] The implementation provides pixels with reduced dimensions.

[0005] The implementation provides a display device with increased resolution.

[0006] A pixel according to an embodiment may include: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color. Each of the first and second sub-pixels may include: a light-emitting element through which a driving current flows; and a pulse width modulator for controlling the width of the driving current. The first and second sub-pixels may share the pulse width modulator for controlling the amplitude of the driving current.

[0007] A frame period can include a first subframe period and a second subframe period. A first subpixel can display a first color in the first subframe period, and a second subpixel can display a second color in the second subframe period.

[0008] A first data voltage can be applied to the pulse width modulator of the first sub-pixel during the first sub-frame period, and a second data voltage can be applied to the pulse width modulator of the second sub-pixel during the second sub-frame period.

[0009] The pulse width modulator may include: a first transistor including a gate for receiving a scan signal, a first terminal for receiving a data voltage, and a second terminal electrically connected to a first node; a capacitor including a first terminal for receiving a sweep signal and a second terminal electrically connected to the first node; a second transistor including a gate electrically connected to a second node, a first terminal electrically connected to a pulse amplitude modulator, and a second terminal electrically connected to a light-emitting element; and an inverter electrically connected between the first node and the second node.

[0010] A pulse amplitude modulator may include a current source.

[0011] The pulse amplitude modulator can be electrically connected to a line that transmits high power voltage, the light-emitting element can be electrically connected to a line that transmits low power voltage, and the pulse width modulator can be electrically connected between the pulse amplitude modulator and the light-emitting element.

[0012] The light-emitting element can be electrically connected to a line that transmits high power voltage, the pulse amplitude modulator can be electrically connected to a line that transmits low power voltage, and the pulse width modulator can be electrically connected between the light-emitting element and the pulse amplitude modulator.

[0013] A pixel may also include a third sub-pixel, which displays a third color and includes a light-emitting element and a pulse width modulator. The first, second, and third sub-pixels may share the pulse amplitude modulator.

[0014] A frame period can include a first subframe period, a second subframe period, and a third subframe period. A first subpixel can display a first color in the first subframe period, a second subpixel can display a second color in the second subframe period, and a third subpixel can display a third color in the third subframe period.

[0015] A first data voltage can be applied to the pulse width modulator of the first sub-pixel during the first sub-frame period, a second data voltage can be applied to the pulse width modulator of the second sub-pixel during the second sub-frame period, and a third data voltage can be applied to the pulse width modulator of the third sub-pixel during the third sub-frame period.

[0016] A pixel according to an embodiment may include: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color. Each of the first and second sub-pixels may include: a light-emitting element through which a driving current flows; and a transistor that controls the width of the driving current in response to an emission signal. The first and second sub-pixels may share a pulse amplitude modulator that controls the amplitude of the driving current.

[0017] A frame period can include a first subframe period and a second subframe period. A first subpixel can display a first color in the first subframe period, and a second subpixel can display a second color in the second subframe period.

[0018] The first data voltage can be applied to the pulse amplitude modulator during the first subframe period, and the second data voltage can be applied to the pulse amplitude modulator during the second subframe period.

[0019] A transistor may include: a gate for receiving a transmitted signal, a first terminal electrically connected to a pulse amplitude modulator, and a second terminal electrically connected to a light-emitting element.

[0020] The pulse amplitude modulator can be electrically connected to a line that transmits high power voltage, the light-emitting element can be electrically connected to a line that transmits low power voltage, and the transistor can be electrically connected between the pulse amplitude modulator and the light-emitting element.

[0021] The light-emitting element can be electrically connected to a line that transmits high power voltage, the pulse amplitude modulator can be electrically connected to a line that transmits low power voltage, and the transistor can be electrically connected between the light-emitting element and the pulse amplitude modulator.

[0022] A display device according to an embodiment may include a plurality of pixels, each of the plurality of pixels including a first sub-pixel displaying a first color and a second sub-pixel displaying a second color. Each of the first sub-pixel and the second sub-pixel may include: a light-emitting element through which a driving current flows; and a pulse width modulator for controlling the width of the driving current. The first sub-pixel and the second sub-pixel may share the same pulse width modulator for controlling the amplitude of the driving current.

[0023] A frame period can include a first subframe period and a second subframe period. A first subpixel can display a first color in the first subframe period, and a second subpixel can display a second color in the second subframe period.

[0024] A first data voltage can be applied to the pulse width modulator of the first sub-pixel during the first sub-frame period, and a second data voltage can be applied to the pulse width modulator of the second sub-pixel during the second sub-frame period.

[0025] The pulse width modulator may include: a first transistor including a gate for receiving a scan signal, a first terminal for receiving a data voltage, and a second terminal electrically connected to a first node; a capacitor including a first terminal for receiving a sweep signal and a second terminal electrically connected to the first node; a second transistor including a gate electrically connected to a second node, a first terminal electrically connected to a pulse amplitude modulator, and a second terminal electrically connected to a light-emitting element; and an inverter electrically connected between the first node and the second node.

[0026] In the pixel according to the embodiment, sub-pixels included in the pixel can share a pulse amplitude modulator, thereby reducing the pixel size. Furthermore, in the display device according to the embodiment, the size of the pixels included in the display device can be reduced, thereby increasing the resolution of the display device. Attached Figure Description

[0027] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 It is shown that it includes Figure 1 A schematic diagram illustrating an example of pixels in a display device.

[0030] Figure 3 It shows the flow included in Figure 2 A schematic diagram of the driving current of the light-emitting element of a sub-pixel in a pixel.

[0031] Figure 4 It is used to describe Figure 2 A schematic diagram of pixel operations.

[0032] Figure 5 It is shown that it includes Figure 2 A schematic circuit diagram illustrating an example of a sub-pixel within a pixel.

[0033] Figure 6 It is used to describe Figure 5 A schematic diagram of the operation of sub-pixels.

[0034] Figure 7 This is a schematic diagram showing pixels according to an embodiment.

[0035] Figure 8 This is a schematic diagram showing pixels according to an embodiment.

[0036] Figure 9 It is used to describe Figure 8 A schematic diagram of pixel operations.

[0037] Figure 10 This is a schematic diagram showing pixels according to an embodiment.

[0038] Figure 11 It is used to describe Figure 10 A schematic diagram of pixel operations.

[0039] Figure 12 This is a schematic diagram showing pixels according to an embodiment.

[0040] Figure 13 This is a schematic diagram showing pixels according to an embodiment.

[0041] Figure 14 It is used to describe Figure 13 A schematic diagram of pixel operations.

[0042] Figure 15 This is a schematic block diagram illustrating an electronic device according to an embodiment.

[0043] Figure 16 It is shown that Figure 15 A schematic diagram illustrating an example of an electronic device implemented as a smartwatch. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the various embodiments or implementations of this disclosure. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of the apparatus or methods disclosed herein. However, it will be apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Herein, the various embodiments are not necessarily exclusive or limiting of this disclosure. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment.

[0045] Unless otherwise indicated, the described embodiments should be understood as providing exemplary features of this disclosure. Therefore, unless otherwise indicated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from this disclosure.

[0046] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular process sequence may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals and / or figure marks denote the same elements.

[0047] When an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it can be directly on, directly connected to, or directly attached to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly" on, directly connected to, or directly attached to another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system, such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0048] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0049] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another element (or multiple elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to allow for inherent deviations in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0051] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of implementations and / or intermediate structures. Therefore, variations in the shapes shown in the drawings should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein should not necessarily be construed as limited to the specific shapes shown for a particular area, but should include, for example, deviations in shape due to manufacturing processes. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and this is not necessarily intended to be limiting.

[0052] Figure 1 This is a schematic block diagram illustrating a display device 100 according to an embodiment.

[0053] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, and a controller 140.

[0054] Display panel 110 may include multiple pixels PX. Each of the pixels PX may include multiple sub-pixels.

[0055] Gate driver 120 can provide a gate signal GS to display panel 110. Gate driver 120 can generate gate signal GS based on a first control signal CNT1 generated from controller 140. The first control signal CNT1 may include a gate clock signal, a gate start signal, etc.

[0056] Data driver 130 can provide a data signal DS to display panel 110. Data driver 130 can generate data signal DS based on second image data IMD2 generated from controller 140 and second control signal CNT2. Second control signal CNT2 may include data clock signal, load signal, etc. Data driver 130 can convert the digital form of second image data IMD2 into analog form of data signal DS.

[0057] The controller 140 can control the operation (or drive) of the gate driver 120 and the data driver 130. The controller 140 can provide a first control signal CNT1 to the gate driver 120 and a second image data IMD2 and a second control signal CNT2 to the data driver 130. The controller 140 can generate the first control signal CNT1, the second image data IMD2, and the second control signal CNT2 based on the first image data IDAT and the control signal CNT, which can be generated from an external source. The controller 140 can compensate the first image data IDAT to generate the second image data IMD2.

[0058] Figure 2 It is shown that it includes Figure 1 A schematic diagram of an example of a pixel PX in a display device 100. Figure 3 It shows the flow included in Figure 2 A schematic diagram of the driving current ID of the light-emitting element EL of the sub-pixel in pixel PX.

[0059] refer to Figure 2 and Figure 3 A pixel PX can include a first sub-pixel PS1, a second sub-pixel PS2, and a third sub-pixel PS3. The first sub-pixel PS1, the second sub-pixel PS2, and the third sub-pixel PS3 can respectively display a first color, a second color, and a third color. A pixel PX can display a color by combining the first color displayed by the first sub-pixel PS1, the second color displayed by the second sub-pixel PS2, and the third color displayed by the third sub-pixel PS3.

[0060] The first color, the second color, and the third color can be red, green, and blue, respectively. In another embodiment, the first color, the second color, and the third color can be cyan, magenta, and yellow, respectively.

[0061] Each of the first sub-pixel PS1, the second sub-pixel PS2, and the third sub-pixel PS3 may include a light-emitting element EL and a pulse width modulator PWM.

[0062] A drive current ID can flow through the light-emitting element EL. For example, the drive current ID can flow from a pulse width modulator (PWM) to the light-emitting element EL. The light-emitting element EL can then emit light with a brightness LUM corresponding to the drive current ID. Figure 3 As shown, the brightness LUM of the light emitted from the light-emitting element EL can be corresponding to the product of the width W_ID and the amplitude A_ID of the drive current ID. Therefore, the brightness LUM of the light emitted from the light-emitting element EL can be controlled by changing the width W_ID and the amplitude A_ID of the drive current ID.

[0063] The light-emitting element EL can be a micro light-emitting diode (μLED). A micro light-emitting diode can refer to an ultra-small light-emitting diode with a size of about 100 μm or smaller. In another embodiment, the light-emitting element EL can be an organic light-emitting diode (OLED). In yet another embodiment, the light-emitting element EL can be one of a nano light-emitting diode (NED), a quantum dot light-emitting diode, and an inorganic light-emitting diode.

[0064] The pulse width modulator (PWM) controls the width W_ID of the drive current ID. The PWM receives a data voltage used to control the width W_ID of the drive current ID. The PWM of the first sub-pixel PS1 receives a first data voltage VDAT1, the PWM of the second sub-pixel PS2 receives a second data voltage VDAT2, and the PWM of the third sub-pixel PS3 receives a third data voltage VDAT3. Figure 1 The data signal DS may include a first data voltage VDAT1, a second data voltage VDAT2, and a third data voltage VDAT3.

[0065] The first sub-pixel PS1, the second sub-pixel PS2, and the third sub-pixel PS3 can share a pulse amplitude modulator (PAM), such as the same PAM or a single PAM. For example, a pixel PX can include a PAM electrically connected to each of the pulse width modulators (PWM). The PAM can control the amplitude A_ID of the drive current ID.

[0066] A pulse amplitude modulator (PAM) can be electrically connected to the line transmitting the high power voltage VDD, an LED (EL) can be electrically connected to the line transmitting the low power voltage VSS, and a pulse width modulator (PWM) can be electrically connected between the PAM and the EL. The voltage level of the high power voltage VDD can be higher than the voltage level of the low power voltage VSS, allowing the drive current ID to flow from the line transmitting the high power voltage VDD to the line transmitting the low power voltage VSS.

[0067] Figure 4 It is used to describe Figure 2 A schematic diagram of the operation of pixel PX.

[0068] refer to Figures 2 to 4 The frame period (FRM) can include a first subframe period (FS1), a second subframe period (FS2), and a third subframe period (FS3). The first subpixel (PS1) can display a first color in the first subframe period (FS1), the second subpixel (PS2) can display a second color in the second subframe period (FS2), and the third subpixel (PS3) can display a third color in the third subframe period (FS3).

[0069] A first data voltage VDAT1 can be applied to the pulse width modulator (PWM) of the first sub-pixel PS1 during the first subframe period FS1, a second data voltage VDAT2 can be applied to the PWM of the second sub-pixel PS2 during the second subframe period FS2, and a third data voltage VDAT3 can be applied to the PWM of the third sub-pixel PS3 during the third subframe period FS3. Therefore, a drive current ID with a width W_ID corresponding to the first data voltage VDAT1 can flow through the light-emitting element EL of the first sub-pixel PS1 during the first subframe period FS1, a drive current ID with a width W_ID corresponding to the second data voltage VDAT2 can flow through the light-emitting element EL of the second sub-pixel PS2 during the second subframe period FS2, and a drive current ID with a width W_ID corresponding to the third data voltage VDAT3 can flow through the light-emitting element EL of the third sub-pixel PS3 during the third subframe period FS3.

[0070] The pulse amplitude modulator (PAM) can control the amplitude A_ID of the drive current ID to be substantially equal in each of the first subframe period FS1, the second subframe period FS2, and the third subframe period FS3. For example, the amplitude A_ID of the drive current ID flowing through the light-emitting element EL of the first sub-pixel PS1 in the first subframe period FS1, the amplitude A_ID of the drive current ID flowing through the light-emitting element EL of the second sub-pixel PS2 in the second subframe period FS2, and the amplitude A_ID of the drive current ID flowing through the light-emitting element EL of the third sub-pixel PS3 in the third subframe period FS3 can be substantially equal to each other.

[0071] In another embodiment, the pulse amplitude modulator (PAM) can control the amplitude A_ID of the drive current ID differently in each of the first subframe period FS1, the second subframe period FS2, and the third subframe period FS3. For example, the PAM can control the amplitude A_ID of the drive current ID differently in each of the first subframe period FS1, the second subframe period FS2, and the third subframe period FS3, taking into account the characteristics of the light-emitting elements EL (e.g., red light-emitting elements) of the first sub-pixel PS1, the light-emitting elements EL (e.g., green light-emitting elements) of the second sub-pixel PS2, and the light-emitting elements EL (e.g., blue light-emitting elements) of the third sub-pixel PS3. For example, the amplitude A_ID of the drive current ID flowing through the light-emitting elements EL of the first sub-pixel PS1 in the first subframe period FS1, the amplitude A_ID of the drive current ID flowing through the light-emitting elements EL of the second sub-pixel PS2 in the second subframe period FS2, and the amplitude A_ID of the drive current ID flowing through the light-emitting elements EL of the third sub-pixel PS3 in the third subframe period FS3 can be different from each other.

[0072] Figure 5 It is shown that it includes Figure 2 A schematic circuit diagram of an example of a sub-pixel PS in a pixel PX. Figure 5 The subpixel PS can be included in Figure 2 One of the first sub-pixel PS1, the second sub-pixel PS2, and the third sub-pixel PS3 in pixel PX.

[0073] refer to Figure 5 The sub-pixel PS may include a light-emitting element EL, a pulse width modulator (PWM), and a pulse amplitude modulator (PAM). For example, one end of the PWM may be electrically connected to the PAM, and the other end of the PWM may be electrically connected to the light-emitting element EL. Furthermore, the PAM may be electrically connected to a first power line PL1, and the EL may be electrically connected to a second power line PL2. However, the configuration of these components is not limited to this.

[0074] The light-emitting element EL may include a first terminal electrically connected to a pulse width modulator (PWM) and a second terminal electrically connected to a second power line PL2 that transmits a low power voltage (VSS). A drive current ID may flow through the light-emitting element EL, and the light-emitting element EL may emit light with a brightness corresponding to the drive current ID.

[0075] A pulse width modulator (PWM) may include a first transistor T1, a capacitor CAP, a second transistor T2, and an inverter INV. However, in another embodiment, the PWM may include additional components for controlling the width of the drive current ID.

[0076] The first transistor T1 may include a gate for receiving a scan signal SS, a first terminal for receiving a data voltage VDAT, and a second terminal electrically connected to the first node N1. Figure 1 The gate signal GS may include a scan signal SS. The first transistor T1 may transmit a data voltage VDAT to the first node N1 in response to the scan signal SS.

[0077] The capacitor CAP may include a first terminal for receiving the sweep frequency signal SWP and a second terminal electrically connected to the first node N1. The capacitor CAP may store the voltage of the first node N1.

[0078] The second transistor T2 may include a gate electrically connected to the second node N2, a first terminal electrically connected to the pulse amplitude modulator PAM, and a second terminal electrically connected to the first terminal of the light-emitting element EL. The second transistor T2 can transmit a drive current ID generated by the pulse amplitude modulator PAM to the light-emitting element EL in response to the voltage of the second node N2.

[0079] The inverter INV can be electrically connected between the first node N1 and the second node N2. The inverter INV can reverse the voltage at the first node N1 and output the reversed voltage to the second node N2.

[0080] A pulse amplitude modulator (PAM) may include a current source CS. However, in another embodiment, the PAM may include different components for controlling the amplitude of the drive current ID.

[0081] The current source CS can be electrically connected between the first power line PL1, which transmits the high power voltage VDD, and the first terminal of the second transistor T2. The current source CS can generate a drive current ID with a constant amplitude.

[0082] Figure 6 It is used to describe Figure 5 A schematic diagram of the operation of subpixel PS.

[0083] refer to Figure 5 and Figure 6 In the first cycle P1, the first transistor T1 can be turned on in response to a scan signal SS having a turn-on voltage level, and the data voltage VDAT can be applied to the first node N1.

[0084] In the second cycle P2, the sweep signal SWP can increase linearly from a low voltage level to a high voltage level, and due to the coupling effect of capacitor CAP, the voltage of the first node N1 can increase linearly in response to the sweep signal SWP. The voltage of the second node N2 can be linearly decreased in the opposite direction to the voltage of the first node N1 through the inverter INV.

[0085] In the third cycle P3, where the voltage of the second node N2 has a turn-on voltage level that turns on the second transistor T2, the second transistor T2 can turn on in response to the voltage of the second node N2, and the drive current ID generated from the current source CS can flow through the light-emitting element EL via the turned-on second transistor T2.

[0086] Figure 7 This is a schematic diagram illustrating a pixel PX according to an embodiment.

[0087] omission and reference Figure 2 The components of the described pixel PX are substantially the same or similar to those in the reference. Figure 7 Description of the components of pixel PX.

[0088] refer to Figure 7 Each of the light-emitting elements EL can be electrically connected to the line that transmits the high power voltage VDD, the pulse amplitude modulator PAM can be electrically connected to the line that transmits the low power voltage VSS, and the pulse width modulator PWM can be electrically connected between the light-emitting element EL and the pulse amplitude modulator PAM.

[0089] Figure 8 This is a schematic diagram showing pixels PX1 and PX2 according to an embodiment.

[0090] omission and reference Figure 2 The components of the described pixel PX are substantially the same or similar to those in the reference. Figure 8 Description of the components of pixels PX1 and PX2.

[0091] refer to Figure 8 The first pixel PX1 may include a first sub-pixel PS1 and a second sub-pixel PS2, and the second pixel PX2 may include a third sub-pixel PS3 and a second sub-pixel PS2. The first pixel PX1 and the second pixel PX2 can display a color by combining a first color displayed by the first sub-pixel PS1, a second color displayed by the second sub-pixel PS2, and a third color displayed by the third sub-pixel PS3. The first sub-pixel PS1 and the second sub-pixel PS2 of the first pixel PX1 may share the same pulse amplitude modulator PAM (i.e., the first pulse amplitude modulator PAM), and the third sub-pixel PS3 and the second sub-pixel PS2 of the second pixel PX2 may share the same pulse amplitude modulator PAM (i.e., the second pulse amplitude modulator PAM). For example, each of the first pixel PX1 and the second pixel PX2 may each include a pulse amplitude modulator PAM. Furthermore, each of the light-emitting elements EL may be electrically connected to a line transmitting a low power voltage VSS. Figure 9 It is used to describe Figure 8 A schematic diagram of the operation of pixels PX1 and PX2.

[0092] refer to Figure 8 and Figure 9 The frame period FRM can include a first subframe period FS1 and a second subframe period FS2. The first subpixel PS1 can display a first color in the first subframe period FS1, the second subpixel PS2 can display a second color in the second subframe period FS2, and the third subpixel PS3 can display a third color in the first subframe period FS1.

[0093] The first data voltage VDAT1 and the third data voltage VDAT3 can be applied to the pulse width modulator (PWM) of the first sub-pixel PS1 and the pulse width modulator (PWM) of the third sub-pixel PS3, respectively, during the first subframe period FS1. The second data voltage VDAT2 can be applied to each of the PWMs of the second sub-pixel PS2 during the second subframe period FS2. Therefore, during the first subframe period FS1, a drive current ID with a width W_ID corresponding to the first data voltage VDAT1 can flow through the light-emitting element EL of the first sub-pixel PS1, and a drive current ID with a width W_ID corresponding to the third data voltage VDAT3 can flow through the light-emitting element EL of the third sub-pixel PS3. During the second subframe period FS2, a drive current ID with a width W_ID corresponding to the second data voltage VDAT2 can flow through each of the light-emitting elements EL of the second sub-pixel PS2.

[0094] Figure 10 This is a schematic diagram illustrating a pixel PX according to an embodiment. Figure 11 It is used to describe Figure 10 A schematic diagram of the operation of pixel PX.

[0095] omission and reference Figure 2 and Figure 4 The components of the described pixel PX are substantially the same or similar to those in the reference. Figure 10 and Figure 11 Description of the components of pixel PX.

[0096] refer to Figure 3 , Figure 10 and Figure 11 Each of the first sub-pixel PS1, the second sub-pixel PS2, and the third sub-pixel PS3 may include a light-emitting element EL and a transistor TR. Each of the light-emitting elements EL may be electrically connected to a line transmitting a low power voltage VSS. Furthermore, in the first sub-pixel PS1, the transistor TR may be electrically connected to a line transmitting a first transmission signal EM1. In the second sub-pixel PS2, the transistor TR may be electrically connected to a line transmitting a second transmission signal EM2. In the third sub-pixel PS3, the transistor TR may be electrically connected to a line transmitting a third transmission signal EM3.

[0097] The transistor TR can control the width W_ID of the drive current ID in response to the transmit signals EM1, EM2 and EM3. Figure 1 The gate signal GS can include transmit signals EM1, EM2, and EM3. The transistor TR can include a gate for receiving transmit signals EM1, EM2, and EM3, a first terminal electrically connected to the pulse amplitude modulator PAM, and a second terminal electrically connected to the light-emitting element EL. The gate of the transistor TR of the first sub-pixel PS1 can receive the first transmit signal EM1, the gate of the transistor TR of the second sub-pixel PS2 can receive the second transmit signal EM2, and the gate of the transistor TR of the third sub-pixel PS3 can receive the third transmit signal EM3.

[0098] The pulse amplitude modulator (PAM) can receive a data signal DS for controlling the amplitude A_ID of the drive current ID. The data signal DS may include a first data voltage VDAT1, a second data voltage VDAT2, and a third data voltage VDAT3.

[0099] The pulse amplitude modulator (PAM) can be electrically connected to the line transmitting the high power voltage VDD, the light-emitting element (EL) can be electrically connected to the line transmitting the low power voltage VSS, and the transistor (TR) can be electrically connected between the pulse amplitude modulator (PAM) and the light-emitting element (EL).

[0100] like Figure 11 As shown, in the first subframe period FS1, a first data voltage VDAT1 can be applied to the pulse amplitude modulator PAM, and the first transmit signal EM1 can have a turn-on voltage level. Therefore, in the first subframe period FS1, a drive current ID having an amplitude A_ID corresponding to the first data voltage VDAT1 can flow through the light-emitting element EL of the first sub-pixel PS1.

[0101] During the second subframe period FS2, the second data voltage VDAT2 can be applied to the pulse amplitude modulator PAM, and the second transmit signal EM2 can have a turn-on voltage level. Therefore, during the second subframe period FS2, a drive current ID with an amplitude A_ID corresponding to the second data voltage VDAT2 can flow through the light-emitting element EL of the second sub-pixel PS2.

[0102] In the third subframe period FS3, the third data voltage VDAT3 can be applied to the pulse amplitude modulator PAM, and the third transmit signal EM3 can have a turn-on voltage level. Therefore, in the third subframe period FS3, a drive current ID with an amplitude A_ID corresponding to the third data voltage VDAT3 can flow through the light-emitting element EL of the third sub-pixel PS3.

[0103] The width of the period of the first transmitted signal EM1 with the conduction voltage level, the width of the period of the second transmitted signal EM2 with the conduction voltage level, and the width of the period of the third transmitted signal EM3 with the conduction voltage level can be substantially the same. For example, the width W_ID of the driving current ID flowing through the light-emitting element EL of the first sub-pixel PS1 in the first sub-frame period FS1, the width W_ID of the driving current ID flowing through the light-emitting element EL of the second sub-pixel PS2 in the second sub-frame period FS2, and the width W_ID of the driving current ID flowing through the light-emitting element EL of the third sub-pixel PS3 in the third sub-frame period FS3 can be substantially the same.

[0104] Figure 12 This is a schematic diagram illustrating a pixel PX according to an embodiment.

[0105] omission and reference Figure 10 The components of the described pixel PX are substantially the same or similar to those in the reference. Figure 12 Description of the components of pixel PX.

[0106] refer to Figure 12 Each of the light-emitting elements EL can be electrically connected to a line transmitting a high power voltage VDD, the pulse amplitude modulator PAM can be electrically connected to a line transmitting a low power voltage VSS, and the transistor TR can be electrically connected between the light-emitting element EL and the pulse amplitude modulator PAM. Furthermore, in the first sub-pixel PS1, the transistor TR can be electrically connected to a line transmitting a first transmit signal EM1. In the second sub-pixel PS2, the transistor TR can be electrically connected to a line transmitting a second transmit signal EM2. In the third sub-pixel PS3, the transistor TR can be electrically connected to a line transmitting a third transmit signal EM3.

[0107] Figure 13 This is a schematic diagram showing pixels PX1 and PX2 according to an embodiment.

[0108] omission and reference Figure 10 The components of the described pixel PX are substantially the same or similar to those in the reference. Figure 13 Description of the components of pixels PX1 and PX2. Each of the light-emitting elements EL can be electrically connected to a line transmitting a low power voltage VSS. In the first sub-pixel PS1 of the first pixel PX1, transistor TR can be electrically connected to the line transmitting a first transmission signal EM1, and in the second sub-pixel PS2 of the first pixel PX1, transistor TR can be electrically connected to the line transmitting a second transmission signal EM2. Similarly, in the third sub-pixel PS3 of the second pixel PX2, transistor TR can be electrically connected to the line transmitting the first transmission signal EM1, and in the second sub-pixel PS2 of the second pixel PX2, transistor TR can be electrically connected to the line transmitting the second transmission signal EM2.

[0109] refer to Figure 13 Each of the gates of the transistor TR of the first sub-pixel PS1 and the transistor TR of the third sub-pixel PS3 can receive the first transmit signal EM1, and each of the gates of the transistor TR of the second sub-pixel PS2 can receive the second transmit signal EM2.

[0110] Figure 14 It is used to describe Figure 13 A schematic diagram of the operation of pixels PX1 and PX2.

[0111] omission and reference Figure 9 The steps and references for operating pixels PX1 and PX2 are described. Figure 11 The steps for operating the pixel PX described are essentially the same or similar to those in the reference. Figure 14 The steps of the operation of pixels PX1 and PX2 are described.

[0112] refer to Figure 13 and Figure 14 In the first subframe period FS1, a first data voltage VDAT1 can be applied to the pulse amplitude modulator (PAM) of the first pixel PX1, a third data voltage VDAT3 can be applied to the pulse amplitude modulator (PAM) of the second pixel PX2, and the first transmit signal EM1 can have a conduction voltage level. Therefore, in the first subframe period FS1, a drive current ID with an amplitude A_ID corresponding to the first data voltage VDAT1 can flow through the light-emitting element EL of the first sub-pixel PS1, and a drive current ID with an amplitude A_ID corresponding to the third data voltage VDAT3 can flow through the light-emitting element EL of the third sub-pixel PS3.

[0113] During the second subframe period FS2, the second data voltage VDAT2 can be applied to the pulse amplitude modulator (PAM) of each of the first pixel PX1 and the second pixel PX2, and the second transmit signal EM2 can have a turn-on voltage level. Therefore, during the second subframe period FS2, a drive current ID with an amplitude A_ID corresponding to the second data voltage VDAT2 can flow through each of the light-emitting elements (EL) of the second sub-pixel PS2.

[0114] Figure 15 This is a schematic block diagram showing an electronic device 1000 according to an embodiment. Figure 16 It is shown that Figure 15 A schematic diagram illustrating an example of an electronic device 1000 implemented as a smartwatch.

[0115] refer to Figure 15 and Figure 16The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include multiple ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0116] like Figure 16 As shown, the electronic device 1000 can be implemented as a smartwatch. However, this disclosure is not limited to this, and according to another embodiment, the electronic device 1000 can be implemented as a television, mobile phone, video phone, smart board, tablet PC, vehicle navigation, laptop computer, head-mounted display, etc.

[0117] Processor 1010 can perform specific calculations or tasks. For example, processor 1010 can be a microprocessor, central processing unit (CPU), etc. Processor 1010 can be electrically connected to other components via address bus, control bus, data bus, etc. For example, processor 1010 can also be electrically connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. Processor 1010 can provide first image data to display device 1060. Figure 1 IDAT) and control signals ( Figure 1 (CNT).

[0118] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM) and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), or mobile DRAM.

[0119] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc. I / O devices 1040 may include input devices such as keyboards, keypads, touchpads, touchscreens, or mice, and output devices such as speakers or printers. Power supply 1050 provides the power required for the operation of electronic device 1000. Display device 1060 may be electrically connected to other components via a bus or other communication link. Display device 1060 may correspond to... Figure 1 Display device 100.

[0120] Among the pixels included in the display device 1060, sub-pixels within a pixel can share a pulse amplitude modulator, allowing the pixel size to be reduced. Furthermore, as the pixel size decreases, the resolution of the display device 1060 can be increased.

[0121] The display device according to the embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, MP3 players, etc.

[0122] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of this disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A pixel, characterized by, The pixel includes: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color, wherein each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a pulse width modulator controlling a width of the driving current, and the first sub-pixel and the second sub-pixel share a pulse amplitude modulator controlling an amplitude of the driving current. 2.The pixel of claim 1, wherein a frame period includes a first sub-frame period and a second sub-frame period, the first sub-pixel displays the first color in the first sub-frame period, and the second sub-pixel displays the second color in the second sub-frame period.

3. The pixel of claim 1, wherein, The pulse width modulator includes: a first transistor including a gate for receiving a scan signal, a first terminal for receiving a data voltage, and a second terminal electrically connected to a first node; a capacitor including a first terminal for receiving a sweep signal and a second terminal electrically connected to the first node; a second transistor including a gate electrically connected to a second node, a first terminal electrically connected to the pulse amplitude modulator, and a second terminal electrically connected to the light emitting element; and an inverter electrically connected between the first node and the second node. 4.The pixel of claim 1, wherein the pulse amplitude modulator is electrically connected to a line transmitting a high power voltage, the light emitting element is electrically connected to a line transmitting a low power voltage, and the pulse width modulator is electrically connected between the pulse amplitude modulator and the light emitting element. 5.The pixel of claim 1, wherein the light emitting element is electrically connected to a line transmitting a high power voltage, the pulse amplitude modulator is electrically connected to a line transmitting a low power voltage, and the pulse width modulator is electrically connected between the light emitting element and the pulse amplitude modulator.

6. The pixel of claim 1, wherein, The pixel further includes: a third sub-pixel displaying a third color, wherein the third sub-pixel includes the light emitting element and the pulse width modulator, and the first sub-pixel, the second sub-pixel, and the third sub-pixel share the same pulse amplitude modulator. 7.The pixel of claim 6, wherein a frame period includes a first sub-frame period, a second sub-frame period, and a third sub-frame period, the first sub-pixel displays the first color in the first sub-frame period, the second sub-pixel displays the second color in the second sub-frame period, and the third sub-pixel displays the third color in the third sub-frame period.

8. A pixel characterized by, The pixel includes: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color, wherein each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a transistor controlling a width of the driving current in response to an emission signal, and the first sub-pixel and the second sub-pixel share a pulse amplitude modulator controlling an amplitude of the driving current.

9. The pixel of claim 8, wherein, The transistor includes: a gate for receiving the emission signal, a first terminal electrically connected to the pulse amplitude modulator, and a second terminal electrically connected to the light emitting element.

10. A display device, characterized by The display device includes: a plurality of pixels, each of the plurality of pixels including a first sub-pixel displaying a first color and a second sub-pixel displaying a second color, wherein each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a pulse width modulator that controls a width of the driving current, and the first sub-pixel and the second sub-pixel share a pulse amplitude modulator that controls an amplitude of the driving current.

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