Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first conductive type well region, which comprises a first device region, a first active region formed in the first device region, a first device unit formed in the first active region, and a first type driving current provided by the first device unit; a second device region connected with the first device region in a length direction of the first conductive type well region, a second active region formed in the second device region, a second device unit formed in the second active region, and a second type driving current provided by the second device unit, the current value of the second type driving current being higher than that of the first type driving current; and the well region width of the first device region is the same as that of the second device region. The application can effectively improve the performance and yield of semiconductor products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] For semiconductor devices such as MOS tubes, the width-length ratio of the conductive channel thereof is proportional to the driving current that can be provided thereby. That is, the greater the width-length ratio of the conductive channel, the greater the driving current that can be provided by the device. The conductive channel is located in the active region within the corresponding well region. Therefore, when designing a semiconductor structure, the width of the well region in which the device unit is located is usually set according to the size of the driving current that needs to be provided by the device unit. For device units that need to provide a larger driving current, the width of the well region in which the device unit is located is usually set to be larger.

[0003] However, when this design method is used, the performance and yield of products of smaller sizes are not ideal. SUMMARY

[0004] Therefore, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure and the manufacturing method thereof can effectively improve the performance and yield of semiconductor products.

[0005] To achieve the above-mentioned purpose, in one aspect, the present application provides a semiconductor structure, comprising a first conductive type well region, the first conductive type well region comprising:

[0006] a first device region, a first active region being formed in the first device region, the first active region forming a first device unit, the first device unit being used to provide a first type of driving current;

[0007] a second device region, the second device region being connected to the first device region in a length direction of the first conductive type well region, a second active region being formed in the second device region, the second active region forming a second device unit, the second device unit being used to provide a second type of driving current, a current value of the second type of driving current being higher than a current value of the first type of driving current;

[0008] the well region width of the first device region and the second device region is the same.

[0009] In one embodiment, the length direction of the first conductive type well region is a row direction, the transistors in the first device unit and the transistors in the second device unit are arranged in a row-column arrangement, and the width of the first active region and the width of the second active region are the same.

[0010] In one embodiment, the threshold voltage of the transistors in the second device unit is lower than the threshold voltage of the transistors in the first device unit.

[0011] In one of the embodiments,

[0012] The doping concentration of the second device region is lower than that of the first device region, and / or,

[0013] The gate dielectric layer thickness of the transistor in the second device unit is smaller than that of the transistor in the first device unit, and / or,

[0014] The difference between the work functions of the gate and the second active region of the transistor in the second device unit is smaller than that of the first device unit.

[0015] In one of the embodiments, the second device unit comprises a base device and an additional device, and the additional device is connected in parallel with the base device.

[0016] In one of the embodiments, the semiconductor structure comprises a detection amplification circuit and a switch control circuit, the detection amplification circuit comprises the first device unit, the switch control circuit connects the detection amplification circuit through a data signal line, and the switch control circuit comprises the second device unit.

[0017] In one of the embodiments,

[0018] The first device unit comprises a transistor unit P01 and a transistor unit P02;

[0019] The detection amplification circuit further comprises a third device unit, and the third device unit comprises a transistor unit N03 and a transistor unit N04;

[0020] The transistor unit N03 and the transistor unit P01 constitute an inverter, the transistor unit N04 and the transistor unit P02 constitute an inverter, and the gate of the transistor unit N04 and the transistor unit P02 is connected to the drain of the transistor unit N03 and the transistor unit P01, and the drain of the transistor unit N04 and the transistor unit P02 is connected to the gate of the transistor unit N03 and the transistor unit P01.

[0021] In one of the embodiments,

[0022] The second device unit comprises a transistor unit P1, a transistor unit P2 and a transistor unit P3;

[0023] The data signal line comprises a first data line and a second data line;

[0024] The drain of transistor unit P1 is connected to the first data line, the drain of transistor unit P2 is connected to the second data line, and the source and drain of transistor unit P3 are respectively connected to the first data line and the second data line.

[0025] In one embodiment,

[0026] The switch control circuit further includes a fourth device unit, which includes transistor unit N1, transistor unit N2 and transistor unit N3.

[0027] The drain of transistor unit N1 is connected to the first data line, the drain of transistor unit N2 is connected to the second data line, and the source and drain of transistor unit N3 are respectively connected to the first data line and the second data line.

[0028] In one embodiment, the switch control circuit further includes a P-type switch unit and an N-type switch unit, wherein the P-type switch unit is used to turn on the fourth device unit, and the N-type switch unit is used to turn on the second device unit.

[0029] This application also provides a method for fabricating a semiconductor structure, including:

[0030] Provide substrate;

[0031] A first conductivity type well region is formed on the substrate; the first conductivity type well region includes a first device region and a second device region with the same width.

[0032] A first active region is formed in the first device region, and a second active region is formed in the second device region;

[0033] A first device unit is formed on the first active region, and a second device unit is formed on the second active region. The first device unit has a first type of drive current, and the second device unit has a second type of drive current. The current value of the second type of drive current is higher than the current value of the first type of drive current.

[0034] In one embodiment, the length direction of the first conductivity type well region is the row direction, the transistors in the first device unit and the transistors in the second device unit are arranged in rows and columns, and the width of the first active region is the same as the width of the second active region.

[0035] In one embodiment, the threshold voltage of the transistor in the second device unit is lower than the threshold voltage of the transistor in the first device unit.

[0036] In one embodiment, the doping concentration of the second device region is lower than that of the first device region.

[0037] In one embodiment,

[0038] The step of forming a first device unit on the first active region and forming a second device unit on the second active region includes:

[0039] A first gate dielectric layer is formed on the first active region, and a second gate dielectric layer is formed on the second active region;

[0040] A first gate is formed on the first gate dielectric layer, and a second gate is formed on the second gate dielectric layer.

[0041] In one embodiment,

[0042] The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and / or,

[0043] The difference in work function between the second gate and the second active region is less than the difference in work function between the first gate and the first active region.

[0044] In one embodiment, the second device unit includes a base device and an additional device, wherein the additional device and the base device are connected in parallel coupling.

[0045] In the aforementioned semiconductor structure and its fabrication method, the first device region A1 and the second device region A2, which are connected along the length of the first conductivity type well region, have the same well region width. This prevents the formation of a step between the first device region A1 and the second device region A2, thereby effectively reducing the total side length of the well edge and thus effectively reducing the impact of the well proximity effect on device performance. Therefore, this application can effectively improve the performance and yield of semiconductor structures. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0048] Figure 2 This is a schematic diagram of the semiconductor structure provided in another embodiment;

[0049] Figure 3 This is a circuit diagram of a semiconductor structure provided in one embodiment;

[0050] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to one embodiment.

[0051] Explanation of reference numerals in the attached figures:

[0052] Explanation of reference numerals in the attached figures: 100 - First device unit, 200 - Second device unit, 210 - Basic device, 220 - Additional device, 300 - Third device unit, 400 - Fourth device unit. Detailed Implementation

[0053] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0057] In one embodiment, see Figure 1 A semiconductor structure is provided, including a well region of a first conductivity type.

[0058] The first conductivity type can be either N-type or P-type. That is, the well region of the first conductivity type can be either an N-type well region or a P-type well region.

[0059] The first conductivity type well region includes a first device region A1 and a second device region A2. The second device region A2 is connected to the first device region A1 along the length of the first conductivity type well region.

[0060] A first active region AA1 is formed within the first device region A1. A second active region AA2 is formed within the second device region A2.

[0061] Specifically, after the formation of a first conductivity type well region including a first device region A1 and a second device region A2, a shallow trench isolation structure can be formed within the first conductivity type well region. The shallow trench isolation structure separates the first device region A1 of the first conductivity type well region to form a first active region AA1, and simultaneously separates the second device region A2 of the first conductivity type well region to form a second active region AA2.

[0062] It is understandable that the first active region AA1 can include one or more regions. Similarly, the second active region AA1 can also include one or more regions.

[0063] A first active region AA1 has a first device unit 100. The first device unit 100 is used to provide a first type of drive current. A second active region AA1 has a second device unit 200. The second device unit 200 provides a second type of drive current. The current value of the second type of drive current is higher than the current value of the first type of drive current.

[0064] Both the first device unit 100 and the second device unit 200 may include multiple transistors, which work together to achieve the same function. For example, please refer to... Figure 1In this configuration, transistor units P01 and P02 are both first device units 100, and both include two transistors arranged horizontally. Transistor units P1, P2, and P3 are all second device units 200. Transistor unit P3 includes two transistors arranged vertically. Transistor units P1 and P2 each include four transistors arranged in two rows and two columns.

[0065] Of course, the first device unit 100 and / or the second device unit 200 may also include only one transistor, and this embodiment does not limit this.

[0066] Meanwhile, in this embodiment, the well widths of the first device region A1 and the second device region A2 are set to be the same, which can effectively improve the performance and yield of the semiconductor structure.

[0067] Specifically, in the semiconductor structure fabrication process, a substrate is first provided. Then, ion implantation is performed on the substrate to form a well region of the first conductivity type. During the ion implantation process, ions diffuse from the edge of the mask used for implantation, becoming denser near the well edge. This causes the doping concentration on the well surface to vary with distance from the mask edge, resulting in a non-uniform doping concentration throughout the well. This non-uniformity causes the device performance to differ with distance from the well edge, thus forming the well proximity effect (WPE).

[0068] In this embodiment, the first device region A1 and the second device region A2, which are connected along the length of the first conductivity type well region, have the same well region width. This prevents the formation of a step between the first device region A1 and the second device region A2, effectively reducing the total side length of the well edge. This, in turn, effectively reduces the impact of the well proximity effect on device performance. Therefore, this embodiment can effectively improve the semiconductor structure performance and yield.

[0069] In one embodiment, the transistors in the first device unit 100 and the transistors in the second device unit 200 are arranged in a row and column configuration, with the length direction of the well region of the first conductivity type as the row direction. Simultaneously, the width of the first active region AA1 is the same as the width of the second active region AA2, thereby ensuring that the channel widths of the transistors in the first device unit 100 and the second device unit 200 located in the same row are the same, which facilitates device design and fabrication.

[0070] It is understandable that the source and drain currents of a transistor are directed along the channel length, while the direction perpendicular to the channel length is the channel width. That is, the channel width direction is consistent with the width direction of the well region of the first conductivity type.

[0071] For example, please refer to Figure 1The first device unit 100 can be configured to include multiple transistors, and the second device unit 200 can also include multiple transistors. Furthermore, the multiple transistors in the first device unit 100 and the multiple transistors in the second device unit 200 are arranged in multiple rows and columns.

[0072] At this time, the channel width of the transistors in each row of the first device unit 100 and the second device unit 200 can be set to be the same.

[0073] Of course, both the first device unit 100 and the second device unit 200 may each contain only one transistor. In this case, the transistor in the first device unit 100 and the transistor in the second device unit 200 may be located in the same row and have the same width of conductivity.

[0074] In one embodiment, the threshold voltage of the transistor in the second device unit 200 is set to be lower than the threshold voltage of the transistor in the first device unit 100.

[0075] For transistor devices, the lower the threshold voltage, the larger the corresponding drain current, meaning the device can provide a larger drive current. Therefore, in this embodiment, by setting the threshold voltage, the second device unit 200 can provide a second type of drive current with a larger current value.

[0076] In one embodiment, the doping concentration of the second device region A2 is set to be lower than that of the first device region A1, so that the doping concentration of the second active region AA2 formed in the second device region A2 is lower than that of the first active region AA1 formed in the first device region A1.

[0077] Meanwhile, the second device unit 200 is formed in the second active region AA2, while the first device unit 100 is formed in the first active region AA1. Therefore, the doping concentration of the conductive channel of the transistor in the second device unit 200 can be lower than the doping concentration of the conductive channel of the transistor in the first device unit 100.

[0078] The lower the doping concentration of the conductive channel of a transistor device, the lower the device threshold voltage.

[0079] Therefore, by designing the doping concentration of the second device region A2 and the first device region A1, this embodiment can conveniently and effectively achieve a threshold voltage of the transistor in the second device unit 200 that is lower than the threshold voltage of the transistor in the first device unit 100.

[0080] Specifically, as an example, during ion implantation, the implantation dose to the second device region A2 can be lower than the implantation dose to the first device region A1, thereby making the doping concentration of the second device region A2 lower than the doping concentration of the first device region A1.

[0081] In one embodiment, the gate dielectric layer thickness of the transistor in the second device unit 200 is less than the gate dielectric layer thickness of the transistor in the first device unit 100.

[0082] The greater the thickness of the gate dielectric layer of a transistor device, the higher the device threshold voltage. Therefore, this embodiment can effectively achieve a lower threshold voltage of the transistor in the second device unit 200 than that of the transistor in the first device unit 100 by adjusting the gate dielectric layer thickness.

[0083] Specifically, as an example, a thinner gate dielectric layer can be deposited in the second device region A2, while a thicker gate dielectric layer can be deposited in the first device region A1.

[0084] In one embodiment, the difference in work function between the gate of the transistor in the second device unit 200 and the second active region AA2 is less than the difference in work function between the gate of the transistor in the first device unit 100 and the first active region AA1.

[0085] The difference in work function between the gate and the active region results in different threshold voltages for the device. Generally, the smaller the difference in work function, the lower the threshold voltage.

[0086] Therefore, this embodiment can effectively achieve a lower threshold voltage of the transistor in the second device unit 200 than that of the transistor in the first device unit 100 by using the difference in work functions.

[0087] Specifically, as an example, the first active region AA1 and the second active region AA2 can have the same work function, while the gate of the transistor in the second device unit 200 and the gate of the transistor in the first device unit 100 can be made of materials with different work functions.

[0088] In one embodiment, see Figure 2 The second device unit 200 includes a base device 210 and an additional device 220. The additional device 220 is a device added to form a second device region A2 with the same well width as the first device region A1 where the first device unit 100 is located, which can improve the driving current.

[0089] Specifically, as an example, please refer to Figure 2 One or more transistors can be added as additional devices 220 to transistor units P1 and P3 within the second device region A2. The added transistors have the same structural size as transistor units P1 and the transistors within transistor unit P1, and the added transistors share a source or drain with the original transistors.

[0090] In conventional processes, if the drive current required by the second device unit 200 is large, it may be necessary to increase the channel width of the transistor in the second device unit 200 accordingly, resulting in a larger width of the well region where the second device unit 200 is located, and a step is formed between the first device region A1 and the second device region A2.

[0091] In this embodiment, by adding an additional device 220, the second device unit 200 is made to have a larger drive current. At the same time, the well width of the second device region A2 where the second device unit 200 is located is set to be the same as the well width of the first device region A1 where the first device unit 100 is located. This ensures sufficient drive current requirements and effectively reduces the impact of well proximity effect on device performance.

[0092] In one embodiment, the semiconductor structure includes a sense amplifier circuit and a switch control circuit (SWC). The sense amplifier circuit includes a first device unit 100, and the switch control circuit includes a second device unit 200.

[0093] Meanwhile, the switch control circuit SWC is connected to the detection amplifier circuit Sense Amplifier via a data signal line, thereby providing a signal to the detection amplifier circuit Sense Amplifier.

[0094] In one embodiment, see Figure 3 The first device unit 100 includes transistor unit P01 and transistor unit P02, which together constitute two first device units 100. Simultaneously, the detection amplification circuit also includes a third device unit 300. The third device unit 300 includes transistor unit N03 and transistor unit N04, which together constitute two third device units 300.

[0095] Transistor unit N03 and transistor unit P01 form an inverter. Their gates are connected together, and their drains are connected together. Simultaneously, the source of transistor unit N03 is connected to a low-level signal terminal, thus inputting a low-level signal when it is turned on. The source of transistor unit P01 is connected to a high-level signal terminal, thus inputting a high-level signal when it is turned on.

[0096] Transistor unit N04 and transistor unit P02 form an inverter. Their gates are connected together, and their drains are connected together. Simultaneously, the source of transistor unit N04 is connected to a low-level signal terminal, thus inputting a low-level signal when it is turned on. The source of transistor unit P02 is connected to a high-level signal terminal, thus inputting a high-level signal when it is turned on.

[0097] Simultaneously, the gates of transistor units N04 and P02 are connected to the drains of transistor units N03 and P01, and the drains of transistor units N04 and P02 are connected to the gates of transistor units N03 and P01. Therefore, when a low-level detection signal is received at the gates of transistor units N04 and P02, transistor unit P02 turns on, thereby outputting a high-level signal to the drain of transistor unit P02 (i.e., the gates of transistor units N03 and P01) to turn on transistor unit N03. Transistor unit N03 outputs a low-level signal to its drain (i.e., the gate of transistor unit N04 and transistor unit P02) and turns P02 back on, repeating this cycle. This causes the voltage on the gate side of transistor unit N04 and transistor unit P02 (i.e., the drain of transistor unit N03 and transistor unit P01) to decrease, while the voltage on the gate side of transistor unit N03 and transistor unit P01 (i.e., the drain of transistor unit N04 and transistor unit P02) to increase, thereby effectively amplifying the detection signal.

[0098] In one embodiment, see Figure 3 The data signal lines include a first data line Ldat# and a second data line Ldat. The second device unit 200 includes transistor unit P1, transistor unit P2, and transistor unit P3, which together constitute three second device units 200.

[0099] The side of the gate of transistor unit N04 and transistor unit P02 (i.e. the drain of transistor unit N03 and transistor unit P01) is denoted as side A, and the voltage on the side of the gate of transistor unit N03 and transistor unit P01 (i.e. the drain of transistor unit N04 and transistor unit P02) is denoted as side B.

[0100] The drain of transistor unit P1 is connected to the first data line Ldat#, while the drain of transistor unit P2 is connected to the second data line Ldat. This allows the switching control circuit to be connected to the A and B sides of the detection amplification channel respectively via the first data line Ldat# and the second data line Ldat. The sources of transistor units P1 and P2 are connected to the same voltage, thus pre-charging the A and B sides of the detection amplification channel with an equipotential voltage through the first data line Ldat# and the second data line Ldat, thereby ensuring detection accuracy.

[0101] The source and drain terminals of transistor unit P3 are connected to the first data line Ldat# and the second data line Ldat, respectively, so that the precharge voltage can be balanced, thereby further ensuring the detection accuracy.

[0102] In one embodiment, seeFigure 3 The switching control circuit may also include a fourth device unit 400, which includes transistor unit N1, transistor unit N2 and transistor unit N3. Transistor unit N1, transistor unit N2 and transistor unit N3 constitute three fourth device units 400.

[0103] The drain of transistor unit N1 is connected to the first data line Ldat#, while the drain of transistor unit N2 is connected to the second data line Ldat. This allows the switching control circuit to be connected to the A and B sides of the detection amplification channel respectively via the first data line Ldat# and the second data line Ldat. The sources of transistor units N1 and N2 are connected to the same voltage, thus pre-charging the A and B sides of the detection amplification channel with an equipotential voltage through the first data line Ldat# and the second data line Ldat, thereby ensuring detection accuracy.

[0104] The source and drain terminals of transistor unit N3 are connected to the first data line Ldat# and the second data line Ldat, respectively, so that the precharge voltage can be balanced, thereby further ensuring the detection accuracy.

[0105] As an example, the detection amplification circuit may further include transistor units N01 and N02. The two ends of transistor unit N01 can be connected to the first data line Ldat# and the A side (i.e., the gate of transistor unit P02, i.e., the drain of transistor units N03 and P01) of transistor unit N04, respectively. Simultaneously, the two ends of transistor unit N02 can be connected to the second data line Ldat and the B side (i.e., the gate of transistor units N03 and P01, i.e., the drain of transistor units N04 and P02) of transistor unit N02. This allows transistor units N01 and N02 to control the precharge signal to be input to the A and B sides of the detection amplification circuit before the detection signal. After precharging is complete, transistor units N01 and N02 can be turned off before the detection signal is input.

[0106] In one embodiment, see Figure 3 The switch control circuit also includes a P-type switch unit 500 and an N-type switch unit 600.

[0107] P-type switch unit 500 is used to turn on the fourth device unit 400, and N-type switch unit 600 is used to turn on the second device unit 400.

[0108] Specifically, please refer to Figure 3The P-type switching unit 500 may include a transistor unit Ppre, and the N-type switching unit 600 may include a transistor unit Npre. The drains of both units can be connected together and connected to the gates of the transistors in the second device unit 200, and also to the gates of the transistors in the fourth device unit 400. Simultaneously, their gates can be connected together, thereby being controlled by the same gate voltage signal. The source of the P-type switching unit 500 is connected to a high-level signal terminal. The source of the N-type switching unit 600 is connected to a low-level signal terminal.

[0109] When a low-level gate voltage signal is input, the P-type switch unit 500 turns on, thereby allowing a high-level source signal to be input to the fourth device unit 400, thus turning on the fourth device unit 400. When a high-level gate voltage signal is input, the N-type switch unit 600 turns on, thereby allowing a low-level source signal to be input to the second device unit 200, thus turning on the second device unit 200.

[0110] In one embodiment, see Figure 4 The invention also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0111] Step S100: Provide a substrate;

[0112] Step S200: A first conductivity type well region is formed on the substrate; the first conductivity type well region includes a first device region and a second device region with the same width.

[0113] Step S300: A first active region is formed in the first device region, and a second active region is formed in the second device region;

[0114] In step S400, a first device unit is formed on the first active region, and a second device unit is formed on the second active region. The first device unit is used to provide a first type of drive current, and the second device unit is used to provide a second type of drive current. The current value of the second type of drive current is higher than the current value of the first type of drive current.

[0115] In one embodiment, the length direction of the first conductivity type well region is the row direction, the transistors in the first device unit and the transistors in the second device unit are arranged in rows and columns, and the channel widths of the transistors in the first device unit and the second device unit located in the same row are the same.

[0116] In one embodiment, the threshold voltage of the transistor in the second device unit is lower than the threshold voltage of the transistor in the first device unit.

[0117] In one embodiment, the doping concentration of the second device region is lower than that of the first device region.

[0118] In one embodiment, step S400 includes:

[0119] Step S410: A first gate dielectric layer is formed on the first active region, and a second gate dielectric layer is formed on the second active region;

[0120] In step S420, a first gate is formed on the first gate dielectric layer, and a second gate is formed on the second gate dielectric layer.

[0121] In one embodiment, the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer.

[0122] In one embodiment, the difference in work function between the second gate and the second active region is less than the difference in work function between the first gate and the first active region.

[0123] In one embodiment, the second device unit includes a base device and an additional device, which are connected in parallel coupling to the base device.

[0124] For specific limitations on the fabrication methods of semiconductor structures, please refer to the limitations on semiconductor structures mentioned above, which will not be repeated here.

[0125] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0126] In the description of this specification, references to terms such as "an embodiment," "ideal embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Includes a first conductivity type well region, the first conductivity type well region comprising: A first device region, wherein a first active region is formed within the first device region, and a first device unit is formed within the first active region, the first device unit being used to provide a first type of drive current; The second device region is connected to the first device region along the length of the first conductivity type well region. A second active region is formed in the second device region, and a second device unit is formed in the second active region. The second device unit is used to provide a second type of drive current, and the current value of the second type of drive current is higher than the current value of the first type of drive current. The well region widths of the first device region and the second device region are the same. The first device unit includes multiple transistors, and the second device unit includes multiple transistors; the length direction of the first conductivity type well region is the row direction, and the multiple transistors in the first device unit and the multiple transistors in the second device unit are arranged in multiple rows and columns; The width of the first active region is the same as the width of the second active region; the threshold voltage of the transistor in the second device unit is lower than the threshold voltage of the transistor in the first device unit.

2. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the second device region is lower than that of the first device region, and / or, The gate dielectric layer thickness of the transistor in the second device unit is less than the gate dielectric layer thickness of the transistor in the first device unit, and / or, The difference in work function between the gate of the transistor in the second device unit and the second active region is less than the difference in work function between the gate of the transistor in the first device unit and the first active region.

3. The semiconductor structure according to claim 1, characterized in that, The second device unit includes a basic device and an additional device, wherein the additional device and the basic device are connected in parallel coupling.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a detection amplification circuit and a switch control circuit. The detection amplification circuit includes the first device unit. The switch control circuit is connected to the detection amplification circuit via a data signal line and includes the second device unit.

5. The semiconductor structure according to claim 4, characterized in that, The first device unit includes transistor unit P01 and transistor unit P02; The detection amplification circuit further includes a third device unit, which includes transistor unit N03 and transistor unit N04; The transistor unit N03 and the transistor unit P01 form an inverter, and the transistor unit N04 and the transistor unit P02 form an inverter. The gates of the transistor units N04 and P02 are connected to the drains of the transistor units N03 and P01, and the drains of the transistor units N04 and P02 are connected to the gates of the transistor units N03 and P01.

6. The semiconductor structure according to claim 4, characterized in that, The second device unit includes transistor unit P1, transistor unit P2, and transistor unit P3; The data signal line includes a first data line and a second data line; The drain of transistor unit P1 is connected to the first data line, the drain of transistor unit P2 is connected to the second data line, and the source and drain of transistor unit P3 are respectively connected to the first data line and the second data line.

7. The semiconductor structure according to claim 6, characterized in that, The switch control circuit further includes a fourth device unit, which includes transistor unit N1, transistor unit N2 and transistor unit N3. The drain of transistor unit N1 is connected to the first data line, the drain of transistor unit N2 is connected to the second data line, and the source and drain of transistor unit N3 are respectively connected to the first data line and the second data line.

8. The semiconductor structure according to claim 7, characterized in that, The switch control circuit further includes a P-type switch unit and an N-type switch unit. The P-type switch unit is used to turn on the fourth device unit, and the N-type switch unit is used to turn on the second device unit.

9. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first conductivity type well region is formed on the substrate; the first conductivity type well region includes a first device region and a second device region with the same width. A first active region is formed in the first device region, and a second active region is formed in the second device region; A first device unit is formed on the first active region, and a second device unit is formed on the second active region. The first device unit has a first type of drive current, and the second device unit has a second type of drive current. The current value of the second type of drive current is higher than the current value of the first type of drive current. The first device unit includes multiple transistors, and the second device unit includes multiple transistors; the length direction of the first conductivity type well region is the row direction, and the multiple transistors in the first device unit and the multiple transistors in the second device unit are arranged in multiple rows and columns; The width of the first active region is the same as the width of the second active region; the threshold voltage of the transistor in the second device unit is lower than the threshold voltage of the transistor in the first device unit.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The doping concentration of the second device region is lower than that of the first device region.

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The step of forming a first device unit on the first active region and forming a second device unit on the second active region includes: A first gate dielectric layer is formed on the first active region, and a second gate dielectric layer is formed on the second active region; A first gate is formed on the first gate dielectric layer, and a second gate is formed on the second gate dielectric layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and / or, The difference in work function between the second gate and the second active region is less than the difference in work function between the first gate and the first active region.

13. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The second device unit includes a basic device and an additional device, wherein the additional device and the basic device are connected in parallel coupling.

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