Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a display panel including pixels, and a panel driver driving the display panel. Each of the pixels includes a first light emitting element, a second light emitting element, a first transistor generating a driving current, a first mode transistor providing the driving current to the first light emitting element in response to a first signal, a second mode transistor providing the driving current to the second light emitting element in response to a second signal, and an emission transistor connecting the first transistor to the first mode transistor and the second mode transistor in response to an emission signal having a plurality of emission periods. The panel driver changes a duty ratio of each of the first signal and the second signal step by step during a plurality of frame periods. A number of steps of the duty ratio change is determined based on a number of the emission periods of the emission signal in one frame period.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including display devices. Background Technology

[0002] Typically, display devices can display images with a wide viewing angle, allowing the image to be seen not only by users in front of the device but also by users to the side. Recently, for the purpose of protecting personal information or for the security of in-vehicle displays installed in automobiles, display devices that operate in a private mode (or privacy mode) that displays images only to users in front of the device have been developed. For example, an in-vehicle display positioned to correspond to the passenger seats of a car can operate in a public mode that displays images with a wide viewing angle to show both the driver and passengers, or in a private mode that displays images with a narrow viewing angle to show images only to passengers.

[0003] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0004] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including display devices. For example, some aspects of embodiments of this disclosure relate to display devices and electronic devices that can support public and private modes.

[0005] Some embodiments include a display device that has relatively improved image quality when switching between a public mode and a private mode, and an electronic device that includes the display device.

[0006] A display device according to some embodiments includes: a display panel including a plurality of pixels; and a panel driver configured to drive the display panel. According to some embodiments, at least one of the plurality of pixels includes: a first light-emitting element having a first viewing angle; a second light-emitting element having a second viewing angle different from the first viewing angle; a first transistor configured to generate a drive current; a first mode transistor configured to provide the drive current to the first light-emitting element in response to a first signal; a second mode transistor configured to provide the drive current to the second light-emitting element in response to a second signal; and an emission transistor configured to connect the first transistor to the first mode transistor and the second mode transistor in response to a transmission signal having a plurality of transmission cycles in a frame period, each of the plurality of transmission cycles including a transmission off period and a transmission on period. According to some embodiments, the panel driver progressively changes the duty cycle of each of the first signal and the second signal during the plurality of frame periods in response to a mode switching signal indicating switching between a first mode and a second mode. According to some embodiments, the number of steps of duty cycle change is determined based on the number of transmission cycles of the transmission signal in a frame period.

[0007] According to some embodiments, the duty cycle can be changed on a frame period basis, and the number of steps in which the duty cycle is changed can be equal to the number of transmission cycles of the transmitted signal in a frame period.

[0008] According to some embodiments, the duty cycle can be changed based on N frame periods, where N is a natural number greater than or equal to 2, and the number of steps in which the duty cycle is changed can be equal to the value obtained by multiplying N by the number of transmission cycles of the transmitted signal in one frame period.

[0009] According to some embodiments, the duty cycle can be changed uniformly in the duty cycle change step.

[0010] According to some embodiments, the first viewpoint can be a wide viewpoint, and the second viewpoint can be a narrow viewpoint that is narrower than the first viewpoint.

[0011] According to some embodiments, the first light-emitting element may be a common light-emitting element in which light emitted from the first light-emitting element is provided to both a first user located in front of the display device and a second user located on the side of the display device, and the second light-emitting element may be a private light-emitting element in which light emitted from the second light-emitting element is provided to the first user but not to the second user.

[0012] According to some embodiments, the first mode can be a public mode, and the second mode can be a private mode. According to some embodiments, when the mode switching signal indicates a switch from public mode to private mode, the panel driver can gradually decrease the duty cycle of the first signal and gradually increase the duty cycle of the second signal during multiple first frame periods, and when the mode switching signal indicates a switch from private mode to public mode, the panel driver can gradually increase the duty cycle of the first signal and gradually decrease the duty cycle of the second signal during multiple second frame periods.

[0013] According to some embodiments, each of the first signal and the second signal may be a global signal provided simultaneously (or concurrently) to multiple pixels.

[0014] According to some embodiments, the first transistor may include a gate, a first terminal connected to a power line configured to transmit a first power supply voltage, and a second terminal, and the aforementioned at least one pixel may further include: a second transistor configured to transmit a data signal to a first node in response to a first gate signal; a third transistor configured to connect the gate of the first transistor and a second terminal of the first transistor in response to a second gate signal; a fourth transistor configured to transmit a first initialization voltage to the gate of the first transistor in response to a third gate signal; a fifth transistor configured to transmit a reference voltage to the first node in response to a second gate signal; a sixth transistor configured to transmit a second initialization voltage to a first terminal of a first light-emitting element in response to a fourth gate signal; a seventh transistor configured to transmit a second initialization voltage to a first terminal of a second light-emitting element in response to a fourth gate signal; a first capacitor connected between the power line and the first node; and a second capacitor connected between the first node and the gate of the first transistor.

[0015] According to some embodiments, the first transistor may include a gate, a first terminal, and a second terminal, and the aforementioned at least one pixel may further include: a second transistor configured to transmit a data signal to the first terminal of the first transistor in response to a first gate signal; a third transistor configured to connect the gate of the first transistor and the second terminal of the first transistor in response to a second gate signal; a fourth transistor configured to transmit a first initialization voltage to the gate of the first transistor in response to a third gate signal; a fifth transistor configured to transmit a first power supply voltage to the first terminal of the first transistor in response to a transmit signal; a sixth transistor configured to transmit a second initialization voltage to the first terminal of the first light-emitting element in response to a fourth gate signal; a seventh transistor configured to transmit a second initialization voltage to the first terminal of the second light-emitting element in response to a fourth gate signal; and a first capacitor connected between a power supply line configured to transmit the first power supply voltage and the gate of the first transistor.

[0016] An electronic device according to some embodiments includes: a processor; and a display device configured to receive input image data and a mode switching signal indicating switching between a first mode and a second mode, and to display an image corresponding to the input image data. According to some embodiments, the display device includes: a display panel including a plurality of pixels; and a panel driver configured to drive the display panel. According to some embodiments, at least one of the plurality of pixels includes: a first light-emitting element having a first viewing angle; a second light-emitting element having a second viewing angle different from the first viewing angle; a first transistor configured to generate a drive current; a first mode transistor configured to provide drive current to the first light-emitting element in response to a first signal; a second mode transistor configured to provide drive current to the second light-emitting element in response to a second signal; and an emitting transistor configured to connect the first transistor to the first mode transistor and the second mode transistor in response to a transmission signal having a plurality of transmission cycles in a frame period, each of the plurality of transmission cycles including a transmission off period and a transmission on period. The panel driver gradually changes the duty cycle of each of the first signal and the second signal during the plurality of frame periods in response to the mode switching signal. The number of steps of duty cycle change is determined based on the number of transmission cycles of the transmission signal in a frame period.

[0017] According to some embodiments, the duty cycle can be changed on a frame period basis, and the number of steps in which the duty cycle is changed can be equal to the number of transmission cycles of the transmitted signal in a frame period.

[0018] According to some embodiments, the duty cycle can be changed based on N frame periods, where N is a natural number greater than or equal to 2, and the number of steps in which the duty cycle is changed can be equal to the value obtained by multiplying N by the number of transmission cycles of the transmitted signal in one frame period.

[0019] According to some embodiments, the duty cycle can be changed uniformly in the duty cycle change step.

[0020] According to some embodiments, the first mode can be a public mode, and the second mode can be a private mode. According to some embodiments, the electronic device can be an automotive electronic device installed in a vehicle, and when the vehicle changes from a stationary state to a moving state, the processor can transmit a mode switching signal indicating a switch from public mode to private mode to the panel driver. In public mode, the image displayed on the display device is seen by both a first user located in front of the display device and a second user located to the side of the display device, while in private mode, the image displayed on the display device is seen by the first user but not by the second user.

[0021] According to some embodiments, when the vehicle changes from a moving state to a stationary state, the processor can transmit a mode switching signal indicating a switch from private mode to public mode to the panel driver.

[0022] According to some embodiments, the first viewpoint can be a wide viewpoint, and the second viewpoint can be a narrow viewpoint that is narrower than the first viewpoint.

[0023] According to some embodiments, the first light-emitting element may be a common light-emitting element in which light emitted from the first light-emitting element is provided to both a first user located in front of the display device and a second user located on the side of the display device, and the second light-emitting element may be a private light-emitting element in which light emitted from the second light-emitting element is provided to the first user but not to the second user.

[0024] According to some embodiments, the first mode can be a public mode, and the second mode can be a private mode. According to some embodiments, when the mode switching signal indicates a switch from public mode to private mode, the panel driver can gradually decrease the duty cycle of the first signal and gradually increase the duty cycle of the second signal during multiple first frame periods, and when the mode switching signal indicates a switch from private mode to public mode, the panel driver can gradually increase the duty cycle of the first signal and gradually decrease the duty cycle of the second signal during multiple second frame periods.

[0025] According to some embodiments, each of the first signal and the second signal may be a global signal provided simultaneously (or concurrently) to multiple pixels.

[0026] In display devices and electronic devices according to some embodiments, when switching between a public mode and a private mode, the number of transmission off periods of the transmitted signal is the same during the conduction period of the global signal, so that brightness differences between image blocks do not occur. Accordingly, when switching between a public mode and a private mode, the horizontal line of the image may not be recognized, and the image quality may be relatively improved. Attached Figure Description

[0027] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a display device according to some embodiments.

[0029] Figure 2 It is shown Figure 1 The image is composed of pixels.

[0030] Figure 3 It is shown Figure 2 A circuit diagram of an example pixel.

[0031] Figure 4 It is shown Figure 2 A circuit diagram of an example pixel.

[0032] Figure 5 It shows when Figure 1 Timing diagram of the first and second signals when the display device switches from public mode to private mode.

[0033] Figure 6 This is a diagram illustrating an example of brightness differences between blocks of an image, depending on whether the conduction period of a first signal overlaps with the transmission off period of a transmit signal having one transmission cycle.

[0034] Figure 7 This is a diagram illustrating an example of brightness differences between blocks of an image, depending on whether the conduction period of the first signal overlaps with the transmission off period of the transmission signal, which has two transmission cycles.

[0035] Figure 8 This is a timing diagram illustrating an example where the duty cycle of the first signal gradually changes when the transmitted signal has two transmission cycles.

[0036] Figure 9 This is a timing diagram illustrating an example where the duty cycle of the first signal gradually changes as the transmitted signal has four transmission cycles.

[0037] Figure 10 This is a timing diagram illustrating an example where the duty cycle of the first signal gradually changes as the transmitted signal has four transmission cycles.

[0038] Figure 11 This is a block diagram illustrating an electronic device according to some embodiments.

[0039] Figure 12 This is a diagram illustrating an electronic device according to some embodiments. Detailed Implementation

[0040] In the following, display devices and electronic devices according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals will be used for the same elements.

[0041] Figure 1 This is a block diagram illustrating a display device 100 according to some embodiments.

[0042] refer to Figure 1 The display device 100 may include a display panel 110 and a panel driver 120. The display panel 110 may include a plurality of pixels (PX).

[0043] Panel driver 120 can drive display panel 110. According to some embodiments, panel driver 120 may include data driver 130, gate driver 140, transmit driver 150, and controller 160.

[0044] Data driver 130 can provide a data signal DS to pixel PX. Data driver 130 can generate the data signal DS based on output image data ODAT received from controller 160 and a data control signal DCTRL. According to some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. According to some embodiments, data driver 130 and controller 160 can be implemented as a single integrated circuit, which may be referred to as a timing controller embedded data driver (TED). According to some embodiments, data driver 130 and controller 160 can be implemented as separate integrated circuits.

[0045] Gate driver 140 can provide gate signals to pixel PX. Gate driver 140 can generate gate signals based on gate control signals GCTRL received from controller 160. According to some embodiments, gate control signals GCTRL may include, but are not limited to, gate start signals and gate clock signals. According to some embodiments, gate signals may be scan signals that are sequentially provided to pixel PX on a pixel-row basis. According to some embodiments, gate signals may include a first gate signal GW, a second gate signal GC, a third gate signal GI, and a fourth gate signal GB. According to some embodiments, gate driver 140 may be integrated or formed in display panel 110. According to some embodiments, gate driver 140 may be implemented as an integrated circuit.

[0046] The transmit driver 150 can provide a transmit signal EM to the pixel PX. The transmit driver 150 can generate the transmit signal EMCTRL based on a transmit control signal EMCTRL received from the controller 160. According to some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. According to some embodiments, the transmit signal EM can be a scan signal that is sequentially provided to the pixel PX on a pixel-row basis. According to some embodiments, the transmit driver 150 can be integrated or formed in the display panel 110. According to some embodiments, the transmit driver 150 can be implemented as an integrated circuit.

[0047] Controller 160 (e.g., a timing controller) can receive input image data IDAT and control signal CTRL from an external processor (e.g., an application processor (AP), a graphics processing unit (GPU), a graphics card, etc.). According to some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 160 can generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. It can control data driver 130 by providing the output image data ODAT and the data control signal DCTRL to data driver 130, control gate driver 140 by providing the gate control signal GCTRL to gate driver 140, and control transmit driver 150 by providing the transmit control signal EMCTRL to transmit driver 150.

[0048] The control signal CTRL may include a mode switching signal SMODE indicating a switch between a first mode (e.g., public mode) and a second mode (e.g., private mode). The controller 160 may generate a first signal GS1 and a second signal GS2 based on the mode switching signal SMODE. According to some embodiments, each of the first signal GS1 and the second signal GS2 may be a global signal provided to the pixel PX simultaneously (or concurrently) (or substantially simultaneously or concurrently).

[0049] According to some embodiments, the first signal GS1 and the second signal GS2 can be directly provided to the pixel PX from the controller 160. According to some embodiments, the display device 100 may further include a level shifter (or level shifter integrated circuit) that converts the voltage levels of the first signal GS1 and the second signal GS2 to a voltage level suitable for the pixel PX, and the first signal GS1 and the second signal GS2 can be provided to the pixel PX from the controller 160 via the level shifter. According to some embodiments, the display device 100 may further include a power management circuit (or power management integrated circuit), and the first signal GS1 and the second signal GS2 can be provided to the pixel PX from the controller 160 via the power management circuit. According to some embodiments, the first signal GS1 and the second signal GS2 can be provided to the pixel PX from the controller 160 via a level shifter and a power management circuit.

[0050] Figure 2 It is shown Figure 1 The image is a pixel PX. Figure 3 It is shown Figure 2 A circuit diagram of an example pixel PX. Although Figure 3Various components are shown in the circuit diagram, but the embodiments of this disclosure are not limited thereto, and the circuit may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0051] refer to Figures 1 to 3 A pixel PX may include a first light-emitting element EL1, a second light-emitting element EL2, and a pixel circuit PC.

[0052] The first light-emitting element EL1 may include a first terminal (e.g., anode) connected to the pixel circuit PC and a second terminal (e.g., cathode) receiving a second power supply voltage ELVSS. The second light-emitting element EL2 may include a first terminal (e.g., anode) connected to the pixel circuit PC and a second terminal (e.g., cathode) receiving a second power supply voltage ELVSS.

[0053] The first light-emitting element EL1 may have a first viewing angle. The second light-emitting element EL2 may have a second viewing angle different from the first viewing angle. According to some embodiments, the first viewing angle may be a wide viewing angle, and the second viewing angle may be a narrow viewing angle smaller than the first viewing angle.

[0054] According to some embodiments, the first light-emitting element EL1 may be a common light-emitting element in which light emitted from the first light-emitting element EL1 is provided to both a first user USER1 located in front of the display device 100 and a second user USER2 located on the side of the display device 100. The mode in which an image displayed on the display device 100 is visible to both the first user USER1 located in front of the display device 100 and the second user USER2 located on the side of the display device 100 may be referred to as the common mode.

[0055] According to some embodiments, the second light-emitting element EL2 may be a privacy light-emitting element in which light emitted from the second light-emitting element EL2 is provided to a first user USER1 located in front of the display device 100 but not to a second user USER2 located on the side of the display device 100. A mode in which the image displayed on the display device 100 is visible to the first user USER1 located in front of the display device 100 but not visible to the second user USER2 located on the side of the display device 100 may be referred to as a privacy mode.

[0056] According to some embodiments, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be an organic light-emitting diode (OLED), but is not limited thereto. According to some embodiments, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be any suitable light-emitting element. For example, each of the first light-emitting element EL1 and the second light-emitting element EL2 may be a micron-sized light-emitting diode, a nano-sized light-emitting diode (NED), a quantum dot (QD) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0057] The pixel circuit PC can generate a drive current based on the first gate signal GW, the second gate signal GC, the third gate signal GI, the fourth gate signal GB, the transmit signal EM, and the data signal DS. The pixel circuit PC can provide the drive current to the first light-emitting element EL1 or the second light-emitting element EL2.

[0058] According to some embodiments, such as Figure 3 As shown, pixel PXa may include a first light-emitting element EL1, a second light-emitting element EL2, and a pixel circuit PCa, and the pixel circuit PCa may include a first transistor T1a, a first mode transistor TM1, a second mode transistor TM2, an emitting transistor TE, a second transistor T2a, a third transistor T3a, a fourth transistor T4a, a fifth transistor T5a, a sixth transistor T6a, a seventh transistor T7a, a first capacitor C1a, and a second capacitor C2a.

[0059] The first transistor T1a may be a drive transistor that generates drive current. According to some embodiments, the first transistor T1a may include a gate, a first terminal (e.g., a source) connected to a power line PL that transmits a first power supply voltage ELVDD, and a second terminal (e.g., a drain).

[0060] The first-mode transistor TM1 can provide drive current to the first light-emitting element EL1 in response to a first signal GS1. According to some embodiments, the first-mode transistor TM1 may include a gate for receiving the first signal GS1, a first terminal (e.g., a source), and a second terminal (e.g., a drain) connected to the first terminal of the first light-emitting element EL1.

[0061] The second-mode transistor TM2 can provide drive current to the second light-emitting element EL2 in response to the second signal GS2. According to some embodiments, the second-mode transistor TM2 may include a gate for receiving the second signal GS2, a first terminal (e.g., a source), and a second terminal (e.g., a drain) connected to the first terminal of the second light-emitting element EL2.

[0062] The emitter transistor TE can connect the first transistor T1a to the first mode transistor TM1 and the second mode transistor TM2 in response to the emitter signal EM. According to some embodiments, the emitter transistor TE may include a gate for receiving the emitter signal EM, a first terminal (e.g., source) connected to the second terminal of the first transistor T1a, and a second terminal (e.g., drain) connected to the first terminal of the first mode transistor TM1 and the first terminal of the second mode transistor TM2.

[0063] The second transistor T2a can transmit the data signal DS to the first node N1 in response to the first gate signal GW. According to some embodiments, the second transistor T2a may include a gate for receiving the first gate signal GW, a first terminal (e.g., a source) connected to the data line DL for transmitting the data signal DS, and a second terminal (e.g., a drain) connected to the first node N1.

[0064] The third transistor T3a can connect the gate of the first transistor T1a and the second terminal of the first transistor T1a in response to the second gate signal GC. According to some embodiments, the third transistor T3a may include a gate that receives the second gate signal GC, a first terminal (e.g., a source) connected to the second terminal of the first transistor T1a, and a second terminal (e.g., a drain) connected to the gate of the first transistor T1a.

[0065] The fourth transistor T4a can transmit a first initialization voltage VINT to the gate of the first transistor T1a in response to a third gate signal GI. According to some embodiments, the fourth transistor T4a may include a gate that receives the third gate signal GI, a first terminal (e.g., a source) that receives the first initialization voltage VINT, and a second terminal (e.g., a drain) connected to the gate of the first transistor T1a.

[0066] The fifth transistor T5a can transmit the reference voltage VREF to the first node N1 in response to the second gate signal GC. According to some embodiments, the fifth transistor T5a may include a gate that receives the second gate signal GC, a first terminal (e.g., a source) that receives the reference voltage VREF, and a second terminal (e.g., a drain) connected to the first node N1.

[0067] The sixth transistor T6a can transmit the second initialization voltage VAINT to the first terminal of the first light-emitting element EL1 in response to the fourth gate signal GB. According to some embodiments, the sixth transistor T6a may include a gate that receives the fourth gate signal GB, a first terminal (e.g., a source) that receives the second initialization voltage VAINT, and a second terminal (e.g., a drain) connected to the first terminal of the first light-emitting element EL1.

[0068] The seventh transistor T7a can transmit the second initialization voltage VAINT to the first terminal of the second light-emitting element EL2 in response to the fourth gate signal GB. According to some embodiments, the seventh transistor T7a may include a gate that receives the fourth gate signal GB, a first terminal (e.g., a source) that receives the second initialization voltage VAINT, and a second terminal (e.g., a drain) connected to the first terminal of the second light-emitting element EL2.

[0069] According to some embodiments, such as Figure 3 As shown, the first-mode transistor TM1, the second-mode transistor TM2, the emitter transistor TE, and the first transistor T1a to the seventh transistor T7a can be P-type metal-oxide-semiconductor (PMOS) transistors. According to some embodiments, at least one of the first-mode transistor TM1, the second-mode transistor TM2, the emitter transistor TE, and the first transistor T1a to the seventh transistor T7a can be an N-type metal-oxide-semiconductor (NMOS) transistor.

[0070] According to some embodiments, at least one of the first-mode transistor TM1, the second-mode transistor TM2, the emitter transistor TE, and the first transistor T1a to the seventh transistor T7a may include a plurality of sub-transistors connected in series. For example, as Figure 3 As shown, each of the second transistor T2a, the third transistor T3a, and the fifth transistor T5a may include two sub-transistors connected in series, and the fourth transistor T4a may include three sub-transistors connected in series.

[0071] The first capacitor C1a can be connected between the power supply line PL and the first node N1. For example, the first capacitor C1a can be a storage capacitor. The first capacitor C1a can store the data signal DS transmitted to the first node N1 via the second transistor T2a.

[0072] The second capacitor C2a can be connected between the first node N1 and the gate of the first transistor T1a. For example, the second capacitor C2a can be a holding capacitor. When the voltage of the first node N1 changes from the reference voltage VREF to the data signal DS, the voltage of the gate of the first transistor T1a can change to a voltage corresponding to the voltage difference between the reference voltage VREF and the data signal DS.

[0073] When the first signal GS1 has an on level (e.g., low level) and the second signal GS2 has an off level (e.g., high level), the first mode transistor TM1 can be turned on, and the second mode transistor TM2 can be turned off. When the first mode transistor TM1 is turned on and the second mode transistor TM2 is turned off, the drive current generated in the pixel circuit PCa can be provided to the first light-emitting element EL1, and the first light-emitting element EL1, which has a wide viewing angle, can emit light based on the drive current. When the first signal GS1 has an on level and the second signal GS2 has an off level, the display device 100 can operate in a common mode.

[0074] When the first signal GS1 is at a cutoff level and the second signal GS2 is at a conduction level, the first mode transistor TM1 can be turned off and the second mode transistor TM2 can be turned on. When the first mode transistor TM1 is turned off and the second mode transistor TM2 is turned on, the driving current generated in the pixel circuit PCa can be provided to the second light-emitting element EL2, and the second light-emitting element EL2 with a narrow viewing angle can emit light based on the driving current. When the first signal GS1 is at a cutoff level and the second signal GS2 is at a conduction level, the display device 100 can operate in a privacy mode.

[0075] Figure 4 It is shown Figure 2 A circuit diagram of an example pixel PX. Although Figure 4 Various components are shown in the circuit diagram, but the embodiments of this disclosure are not limited thereto, and the circuit may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0076] refer to Figure 1 , Figure 2 and Figure 4 According to some embodiments, such as Figure 4 As shown, pixel PXb may include a first light-emitting element EL1, a second light-emitting element EL2, and a pixel circuit PCb. The pixel circuit PCb may include a first transistor T1b, a first mode transistor TM1, a second mode transistor TM2, an emitting transistor TE, a second transistor T2b, a third transistor T3b, a fourth transistor T4b, a fifth transistor T5b, a sixth transistor T6b, a seventh transistor T7b, and a first capacitor C1b.

[0077] refer to Figure 4 The description of pixel PXb and reference Figure 3 Some descriptions of parts that are the same (or substantially the same) or similar to the parts described for pixel PXa may be omitted.

[0078] The first transistor T1b may be a driving transistor that generates a driving current. According to some embodiments, the first transistor T1b may include a gate, a first terminal (e.g., a source) and a second terminal (e.g., a drain).

[0079] The emitter transistor TE can connect the first transistor T1b to the first mode transistor TM1 and the second mode transistor TM2 in response to the emitter signal EM. According to some embodiments, the emitter transistor TE may include a gate for receiving the emitter signal EM, a first terminal (e.g., source) connected to the second terminal of the first transistor T1b, and a second terminal (e.g., drain) connected to the first terminal of the first mode transistor TM1 and the first terminal of the second mode transistor TM2.

[0080] The second transistor T2b can transmit the data signal DS to a first terminal of the first transistor T1b in response to the first gate signal GW. According to some embodiments, the second transistor T2b may include a gate for receiving the first gate signal GW, a first terminal (e.g., a source) connected to a data line DL for transmitting the data signal DS, and a second terminal (e.g., a drain) connected to the first terminal of the first transistor T1b.

[0081] The third transistor T3b can connect the gate of the first transistor T1b and the second terminal of the first transistor T1b in response to the second gate signal GC. According to some embodiments, the third transistor T3b may include a gate that receives the second gate signal GC, a first terminal (e.g., a source) connected to the second terminal of the first transistor T1b, and a second terminal (e.g., a drain) connected to the gate of the first transistor T1b.

[0082] The fourth transistor T4b can transmit a first initialization voltage VINT to the gate of the first transistor T1b in response to a third gate signal GI. According to some embodiments, the fourth transistor T4b may include a gate that receives the third gate signal GI, a first terminal (e.g., a source) that receives the first initialization voltage VINT, and a second terminal (e.g., a drain) connected to the gate of the first transistor T1b.

[0083] The fifth transistor T5b can transmit the first power supply voltage ELVDD to the first terminal of the first transistor T1b in response to the transmit signal EM. According to some embodiments, the fifth transistor T5b may include a gate for receiving the transmit signal EM, a first terminal (e.g., a source) for receiving the first power supply voltage ELVDD, and a second terminal (e.g., a drain) connected to the first terminal of the first transistor T1b.

[0084] The sixth transistor T6b can transmit the second initialization voltage VAINT to the first terminal of the first light-emitting element EL1 in response to the fourth gate signal GB. According to some embodiments, the sixth transistor T6b may include a gate for receiving the fourth gate signal GB, a first terminal (e.g., a source) for receiving the second initialization voltage VAINT, and a second terminal (e.g., a drain) connected to the first terminal of the first light-emitting element EL1.

[0085] The seventh transistor T7b can transmit the second initialization voltage VAINT to the first terminal of the second light-emitting element EL2 in response to the fourth gate signal GB. According to some embodiments, the seventh transistor T7b may include a gate that receives the fourth gate signal GB, a first terminal (e.g., a source) that receives the second initialization voltage VAINT, and a second terminal (e.g., a drain) connected to the first terminal of the second light-emitting element EL2.

[0086] According to some embodiments, such as Figure 4 As shown, the first-mode transistor TM1, the second-mode transistor TM2, the emitter transistor TE, and the first transistors T1b to the seventh transistor T7b can be PMOS transistors. According to some embodiments, at least one of the first-mode transistor TM1, the second-mode transistor TM2, the emitter transistor TE, and the first transistors T1b to the seventh transistor T7b can be an NMOS transistor.

[0087] According to some embodiments, at least one of the first mode transistor TM1, the second mode transistor TM2, the emitter transistor TE, and the first transistor T1b to the seventh transistor T7b may include a plurality of sub-transistors connected in series.

[0088] Figure 5 It shows when Figure 1 Timing diagram of the first signal GS1 and the second signal GS2 when the display device 100 switches from public mode to private mode.

[0089] refer to Figure 1 and Figure 5The panel driver 120 (or controller 160) can gradually or progressively change the duty cycle of each of the first signal GS1 and the second signal GS2 during multiple frame periods in response to a mode switching signal SMODE indicating a switch between a first mode and a second mode. Here, the duty cycle of the first signal GS1 can represent the ratio of the duration of the on-time (e.g., low-level period) of the first signal GS1 to the duration of the frame period, and the duty cycle of the second signal GS2 can represent the ratio of the duration of the on-time of the second signal GS2 to the duration of the frame period. Accordingly, when the mode of the display device 100 switches between the first mode and the second mode, the mode switching of the display device 100 can be performed smoothly.

[0090] For example, such as Figure 5 As shown, when the mode switching signal SMODE indicates a switch from public mode to private mode, the panel driver 120 (or controller 160) can gradually decrease the duty cycle of the first signal GS1 and gradually increase the duty cycle of the second signal GS2 during multiple frame periods FP1, FP2, ..., FPN.

[0091] exist Figure 5 In the example, the first signal GS1 may have a first conduction period OP1_1 shorter than the first frame period FP1 in the first frame period FP1, a second conduction period OP1_2 shorter than the first conduction period OP1_1 in the second frame period FP2, and an Nth conduction period OP1_N shorter than the (N-1)th conduction period in the Nth frame period FPN. Furthermore, in Figure 5 In the example, the second signal GS2 may have a first conduction period OP2_1 shorter than the first frame period FP1 in the first frame period FP1, a second conduction period OP2_2 longer than the first conduction period OP2_1 in the second frame period FP2, and a Nth conduction period OP2_N longer than the (N-1)th conduction period in the Nth frame period FPN. Because the conduction periods OP1_1, OP1_2, ..., OP1_N of the first signal GS1 gradually decrease in multiple frame periods FP1, FP2, ..., FPN, the time period during which the first light-emitting element EL1 of pixel PX emits light can also gradually decrease in multiple frame periods FP1, FP2, ..., FPN. Furthermore, because the conduction periods OP2_1, OP2_2, ..., OP2_N of the second signal GS2 gradually increase in multiple frame periods FP1, FP2, ..., FPN, the time period during which the second light-emitting element EL2 of pixel PX emits light can also gradually increase in multiple frame periods FP1, FP2, ..., FPN.

[0092] For example, when the mode switching signal SMODE indicates a switch from private mode to public mode, the panel driver 120 (or controller 160) can gradually increase the duty cycle of the first signal GS1 and gradually decrease the duty cycle of the second signal GS2 during multiple frame periods FP1, FP2, ..., FPN.

[0093] Figure 6 This is a diagram illustrating an example of the brightness difference between blocks BL1 and BL2 of image IMG1, depending on whether the ON period of the first signal GS1 overlaps with the off periods of the transmission signals EM[1], ..., EM[M] having a transmission cycle EM_CYC. Figure 7 This is a diagram illustrating an example of the brightness differences between blocks BL3, BL4, BL5, and BL6 of image IMG2, depending on whether the ON period of the first signal GS1 overlaps with the off periods of the transmission signals EM[1], ..., EM[M] which have two transmission cycles EM_CYC.

[0094] refer to Figure 3 , Figure 4 , Figure 6 and Figure 7 Each of the transmit signals EM[1], ..., EM[M] may have at least one transmit period EM_CYC within a frame period. The transmit period EM_CYC may include a transmit off period and a transmit on period following the transmit off period. The transmit off period may be a period in which the transmit signal EM has a cutoff level (e.g., a high level), and the transmit on period may be a period in which the transmit signal EM has a conduction level (e.g., a low level).

[0095] When the ON period of the first signal GS1 and the ON period of the transmit signal EM do not overlap (when the ON period of the first signal GS1 and the ON period of the transmit signal EM overlap), both the emitter transistor TE and the first mode transistor TM1 are turned on. This allows the drive current generated in the first transistors T1a and T1b to be supplied to the first light-emitting element EL1 through the emitter transistor TE and the first mode transistor TM1, and the first light-emitting element EL1 can emit light based on the drive current. When the ON period of the first signal GS1 and the ON period of the transmit signal EM overlap, even if the first mode transistor TM1 is turned on, the emitter transistor TE is turned off. Therefore, the drive current generated in the first transistors T1a and T1b may not be supplied to the first light-emitting element EL1, and the first light-emitting element EL1 may not emit light.

[0096] For example, such as Figure 6As shown, when each of the transmission signals EM[1], ..., EM[M] has a transmission period EM_CYC, the first light-emitting element EL1 of pixels PXa and PXb in the first block BL1, where the transmission off period of the transmission signals EM[1], ... overlaps with the conduction period ON of the first signal GS1, may emit light with relatively low brightness, and the first light-emitting element EL1 of pixels PXa and PXb in the second block BL2, where the transmission off period of the transmission signals ..., EM[M] overlaps with the cutoff period OFF of the first signal GS1, may emit light with relatively high brightness. Accordingly, the brightness of the first block BL1 of image IMG1 may be lower than the brightness of the second block BL2 of image IMG1, and the brightness difference may occur between blocks BL1 and BL2 of image IMG1. For example, as Figure 6 As shown, during the switching process between public and private modes, the horizontal line may be identified in image IMG1, and the image quality may degrade.

[0097] For example, such as Figure 7 As shown, when each of the transmission signals EM[1], ..., EM[M] has two transmission cycles EM_CYC, the first light-emitting element EL1 of pixels PXa and PXb in the third block BL3 and the fifth block BL5, where the transmission off period of the transmission signals EM[1], ... overlaps with the conduction period ON of the first signal GS1, can emit light with relatively low brightness, and the first light-emitting element EL1 of pixels PXa and PXb in the fourth block BL4 and the sixth block BL6, where the transmission off period of the transmission signals ..., EM[M] overlaps with the cutoff period OFF of the first signal GS1, can emit light with relatively high brightness. Accordingly, the brightness of the third block BL3 and the fifth block BL5 of image IMG2 may be lower than the brightness of the fourth block BL4 and the sixth block BL6 of image IMG2, and brightness differences may occur between blocks BL3, BL4, BL5 and BL6 of image IMG2. For example, as Figure 7 As shown, during the switching process between public and private modes, the three horizontal lines may be identified in image IMG2, and the image quality may degrade.

[0098] Figure 8 This is a timing diagram showing an example of how the duty cycle of the first signal GS1 changes gradually when the transmitted signals EM[1], ..., EM[M] have two transmission cycles EM_CYC. Figure 9 This is a timing diagram showing an example of how the duty cycle of the first signal GS1 changes gradually when the transmitted signals EM[1], ..., EM[M] have four transmission cycles EM_CYC.

[0099] refer to Figure 1, Figure 8 and Figure 9 The panel driver 120 (or controller 160) can determine the number of steps in which the duty cycle of each of the first signal GS1 and the second signal GS2 changes based on the number of transmission cycles EM_CYC in a frame period of the transmitted signal EM.

[0100] According to some embodiments, the duty cycle of each of the first signal GS1 and the second signal GS2 can be changed on a frame period basis, and the number of steps in which the duty cycle of each of the first signal GS1 and the second signal GS2 is changed can be equal to the number of transmission cycles EM_CYC of the transmitted signal EM in a frame period.

[0101] For example, such as Figure 8 As shown, when the duty cycle of the first signal GS1 is changed based on a frame period and the number of transmission cycles EM_CYC of the transmitted signal EM in a frame period is 2, the number of steps in which the duty cycle of the first signal GS1 is changed can be 2. For example, when the mode of the display device 100 switches from public mode to private mode, the duty cycle of the first signal GS1 can be reduced from 100% to 50% in the first step ST1 corresponding to the first frame period FP1, and the duty cycle of the first signal GS1 can be reduced from 50% to 0% in the second step ST2 corresponding to the second frame period FP2. The number of transmission off periods of each of the transmitted signals EM[1], ..., EM[M] in the ON period of the first signal GS1 can generally be 1 in the first frame period FP1. Accordingly, in the first frame period FP1, brightness differences may not appear between blocks of the image.

[0102] exist Figure 8 In the example, the number of steps in which the duty cycle of the second signal GS2 changes can be 2. For example, when the mode of the display device 100 switches from public mode to private mode, in the first step ST1 corresponding to the first frame period FP1, the duty cycle of the second signal GS2 can be increased from 0% to 50%, and in the second step ST2 corresponding to the second frame period FP2, the duty cycle of the second signal GS2 can be increased from 50% to 100%.

[0103] For example, such as Figure 9As shown, when the duty cycle of the first signal GS1 is changed based on a frame period and the number of transmission cycles EM_CYC of the transmitted signal EM in a frame period is 4, the number of steps in which the duty cycle of the first signal GS1 is changed can be 4. For example, when the mode of the display device 100 switches from public mode to private mode, the duty cycle of the first signal GS1 can be reduced from 100% to 75% in the first step ST1 corresponding to the first frame period FP1, the duty cycle of the first signal GS1 can be reduced from 75% to 50% in the second step ST2 corresponding to the second frame period FP2, the duty cycle of the first signal GS1 can be reduced from 50% to 25% in the third step ST3 corresponding to the third frame period FP3, and the duty cycle of the first signal GS1 can be reduced from 25% to 0% in the fourth step ST4 corresponding to the fourth frame period FP4. The number of transmission off periods of each of the transmitted signals EM[1], ..., EM[M] during the ON period of the first signal GS1 is typically 3 in the first frame period FP1; the number of transmission off periods of each of the transmitted signals EM[1], ..., EM[M] during the ON period of the first signal GS1 is typically 2 in the second frame period FP2; and the number of transmission off periods of each of the transmitted signals EM[1], ..., EM[M] during the ON period of the first signal GS1 is typically 1 in the third frame period FP3. Accordingly, in each of the first frame period FP1 to the third frame period FP3, brightness differences may not appear between blocks of the image.

[0104] exist Figure 9 In the example, the number of steps in which the duty cycle of the second signal GS2 changes can be 4. For example, when the mode of the display device 100 switches from public mode to private mode, the duty cycle of the second signal GS2 can be increased from 0% to 25% in the first step ST1 corresponding to the first frame period FP1, the duty cycle of the second signal GS2 can be increased from 25% to 50% in the second step ST2 corresponding to the second frame period FP2, the duty cycle of the second signal GS2 can be increased from 50% to 75% in the third step ST3 corresponding to the third frame period FP3, and the duty cycle of the second signal GS2 can be increased from 75% to 100% in the fourth step ST4 corresponding to the fourth frame period FP4.

[0105] According to some embodiments, during the process of switching the mode of the display device 100 between a public mode and a private mode, brightness differences do not appear between blocks of the image in each frame period, thereby improving the image quality of the display device 100. Furthermore, according to some embodiments, the number of steps in which the duty cycle of each of the first signal GS1 and the second signal GS2 changes is equal to the number of transmission cycles EM_CYC of the transmitted signal EM in one frame period, allowing the mode switching of the display device 100 to be performed quickly.

[0106] According to some embodiments, the duty cycle of each of the first signal GS1 and the second signal GS2 can be changed uniformly in the duty cycle changing step. Figure 8 In the example, the duty cycle of the first signal GS1 can be reduced by 50% for each frame period, and the duty cycle of the second signal GS2 can be increased by 50% for each frame period. Figure 9 In the example, the duty cycle of the first signal GS1 can be reduced by 25% for each frame period, and the duty cycle of the second signal GS2 can be increased by 25% for each frame period.

[0107] Figure 10 This is a timing diagram showing an example of how the duty cycle of the first signal GS1 changes gradually when the transmitted signals EM[1], ..., EM[M] have four transmission cycles EM_CYC.

[0108] refer to Figure 1 and Figure 10 According to some embodiments, the duty cycle of each of the first signal GS1 and the second signal GS2 can be changed on a basis of N frame periods, where N is a natural number greater than or equal to 2, and the number of steps in which the duty cycle of each of the first signal GS1 and the second signal GS2 is changed can be equal to the value obtained by multiplying N by the number of transmission cycles EM_CYC of the transmitted signal EM in one frame period.

[0109] For example, such as Figure 10As shown, when the duty cycle of the first signal GS1 is changed based on two frame periods and the number of transmission cycles EM_CYC of the transmitted signal EM in one frame period is 4, the number of steps in which the duty cycle of the first signal GS1 is changed can be 8. For example, when the mode of the display device 100 switches from public mode to private mode, the duty cycle of the first signal GS1 can be reduced from 100% to 87.5% in the first step ST1 corresponding to the first frame period FP1 and the second frame period FP2; the duty cycle of the first signal GS1 can be reduced from 87.5% to 75% in the second step ST2 corresponding to the third frame period FP3 and the fourth frame period FP4; the duty cycle of the first signal GS1 can be reduced from 75% to 62.5% in the third step ST3 corresponding to the fifth frame period FP5 and the sixth frame period FP6; and the duty cycle of the first signal GS1 can be reduced from 62.5% to 62.5% in the fourth step ST4 corresponding to the seventh frame period FP7 and the eighth frame period FP8. The duty cycle of the first signal GS1 can be reduced from 50% to 37.5% in step ST5, corresponding to the ninth frame period FP9 and the tenth frame period FP10; the duty cycle of the first signal GS1 can be reduced from 37.5% to 25% in step ST6, corresponding to the eleventh frame period FP11 and the twelfth frame period FP12; the duty cycle of the first signal GS1 can be reduced from 25% to 12.5% ​​in step ST7, corresponding to the thirteenth frame period FP13 and the fourteenth frame period FP14; and the duty cycle of the first signal GS1 can be reduced from 12.5% ​​to 0% in step ST8, corresponding to the fifteenth frame period FP15 and the sixteenth frame period FP16. The number of transmission shutdown periods of each of the transmitted signals EM[1], ..., EM[M] during the ON period of the first signal GS1 is typically 4 in the first frame period FP1, the third frame period FP3, the fifth frame period FP5, and the seventh frame period FP7. The number of transmission shutdown periods of each of the transmitted signals EM[1], ..., EM[M] during the ON period of the first signal GS1 is typically 3 in the second frame period FP2 and the ninth frame period FP9. The number of transmit off periods in the ON period of the first signal GS1 can typically be 2 in the fourth frame period FP4 and the eleventh frame period FP11. The number of transmit off periods in the ON period of the first signal GS1 for each of the transmit signals EM[1], ..., EM[M] can typically be 1 in the sixth frame period FP6 and the thirteenth frame period FP13. Furthermore, the first signal GS1 can have only an off period OFF in the eighth frame period FP8, the tenth frame period FP10, the twelfth frame period FP12, and the fourteenth frame period FP14.Accordingly, in the first frame period FP1 to the fourteenth frame period FP14, brightness differences may not appear between blocks of the image.

[0110] exist Figure 10 In the example, the number of steps in which the duty cycle of the second signal GS2 changes can be 8. For example, when the mode of the display device 100 switches from public mode to private mode, the duty cycle of the second signal GS2 can increase from 0% to 12.5% ​​in the first step ST1 corresponding to the first frame period FP1 and the second frame period FP2; the duty cycle of the second signal GS2 can increase from 12.5% ​​to 25% in the second step ST2 corresponding to the third frame period FP3 and the fourth frame period FP4; the duty cycle of the second signal GS2 can increase from 25% to 37.5% in the third step ST3 corresponding to the fifth frame period FP5 and the sixth frame period FP6; and the duty cycle of the second signal GS2 can increase from 37.5% to 37.5% in the fourth step ST4 corresponding to the seventh frame period FP7 and the eighth frame period FP8. The duty cycle of the second signal GS2 can be increased from 50% to 62.5% in the fifth step ST5, corresponding to the ninth frame period FP9 and the tenth frame period FP10; the duty cycle of the second signal GS2 can be increased from 62.5% to 75% in the sixth step ST6, corresponding to the eleventh frame period FP11 and the twelfth frame period FP12; the duty cycle of the second signal GS2 can be increased from 75% to 87.5% in the seventh step ST7, corresponding to the thirteenth frame period FP13 and the fourteenth frame period FP14; and the duty cycle of the second signal GS2 can be increased from 87.5% to 100% in the eighth step ST8, corresponding to the fifteenth frame period FP15 and the sixteenth frame period FP16.

[0111] According to some embodiments, the number of steps in which the duty cycle of each of the first signal GS1 and the second signal GS2 changes is equal to a multiple of the number of transmission cycles EM_CYC of the transmitted signal EM in one frame period, so that the duty cycle can be gradually reduced in the steps of duty cycle change. For example, when the number of transmission cycles EM_CYC of the transmitted signal EM in one frame period is 4, in Figure 9 In the example, the duty cycle of the first signal GS1 can be decreased by 25% for each step of the duty cycle change, and the duty cycle of the second signal GS2 can be increased by 25% for each step of the duty cycle change. Figure 10In the example, the duty cycle of the first signal GS1 can be reduced by 12.5% ​​for each step of the duty cycle change, and the duty cycle of the second signal GS2 can be increased by 12.5% ​​for each step of the duty cycle change. Therefore, according to some embodiments, during the process of switching between public mode and private mode of the display device 100, the brightness difference between images corresponding to frame periods can be reduced, and the image quality of the display device 100 can be further improved.

[0112] Figure 11 This is a block diagram illustrating an electronic device 10 according to some embodiments.

[0113] refer to Figure 1 and Figure 11 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0114] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor 12 can control the display module 11.

[0115] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, the input image data IDAT and the control signal CTRL can be transmitted to the display module 11, and the display module 11 can output image information based on the input image data IDAT and the control signal CTRL.

[0116] The power module 14 may include a power supply module such as a power adapter and a battery device, as well as a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0117] At least one of the components of the electronic device 10 described above may be included according to some of the embodiments described above. Figure 1 The display device 100 is included in the display device 100. Furthermore, in terms of functionality, some of the modules described above may be included in the display device 100, while others may be provided separately from the display device 100. For example, the display device 100 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 besides the display device 100.

[0118] According to some embodiments, the electronic device 10 may be an automotive electronic device installed in a vehicle. When the vehicle changes from a stationary state to a moving state (e.g., when the vehicle's gear changes from parking mode or neutral mode to driving mode or reverse mode), the processor 12 may transmit a mode switching signal SMODE indicating a switch from public mode to private mode to the panel driver 120 (or controller 160). Furthermore, when the vehicle changes from a moving state to a stationary state (e.g., when the vehicle's gear changes from driving mode or reverse mode to parking mode or neutral mode), the processor 12 may transmit a mode switching signal SMODE indicating a switch from private mode to public mode to the panel driver 120 (or controller 160).

[0119] Figure 12 This is a diagram illustrating an electronic device according to some embodiments.

[0120] refer to Figure 12 The electronic devices that utilize the display devices according to some embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as car dashboards, center consoles, central information displays (CIDs) arranged on dashboards, and interior mirror displays.

[0121] The display device according to some embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, or MP3 players.

[0122] Although aspects of some embodiments of the display device and electronic device according to the present disclosure have been described with reference to the accompanying drawings, the illustrated embodiments are merely examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes multiple pixels; as well as A panel driver is configured to drive the display panel. At least one pixel among the plurality of pixels includes: The first light-emitting element has a first viewing angle; The second light-emitting element has a second viewing angle different from the first viewing angle; The first transistor is configured to generate drive current; A first-mode transistor is configured to provide the drive current to the first light-emitting element in response to a first signal; A second-mode transistor is configured to provide the drive current to the second light-emitting element in response to a second signal; and The emitter transistor is configured to connect the first transistor to the first mode transistor and the second mode transistor in response to a transmit signal having multiple transmit cycles within a frame period, each of the multiple transmit cycles including a transmit off period and a transmit on period. The panel driver is configured to progressively change the duty cycle of each of the first and second signals over a plurality of frame periods in response to a mode switching signal indicating a switch between a first mode and a second mode. The number of steps in which the duty cycle is changed is determined based on the number of transmission cycles of the transmitted signal in one frame period.

2. The display device according to claim 1, wherein, The duty cycle changes based on a frame period, and The number of steps in which the duty cycle is changed is equal to the number of transmission cycles of the transmitted signal in one frame period.

3. The display device according to claim 1, wherein, The duty cycle is varied based on N frame time intervals, where N is a natural number greater than or equal to 2. The number of steps in which the duty cycle is changed is equal to the value obtained by multiplying N by the number of transmission cycles of the transmitted signal in one frame period.

4. The display device according to claim 1, wherein, The duty cycle is changed uniformly in the step in which the duty cycle is changed.

5. The display device according to claim 1, wherein, The first perspective is a wide-angle view, and The second viewpoint is a narrower viewpoint than the first viewpoint.

6. The display device according to claim 1, wherein, The first light-emitting element is a common light-emitting element in which light emitted from the first light-emitting element is provided to both the front of the display device and the sides of the display device, and The second light-emitting element is a privacy light-emitting element in which light emitted from the second light-emitting element is provided to the front of the display device and not to the sides of the display device.

7. The display device according to claim 1, wherein, The first mode is a public mode, and the second mode is a private mode. Specifically, based on the mode switching signal indicating a switch from the public mode to the private mode, the panel driver is configured to progressively decrease the duty cycle of the first signal and progressively increase the duty cycle of the second signal during a plurality of first frame time periods. Based on the mode switching signal indicating a switch from the private mode to the public mode, the panel driver is configured to gradually increase the duty cycle of the first signal and gradually decrease the duty cycle of the second signal during a plurality of second frame periods.

8. The display device according to claim 1, wherein, Each of the first signal and the second signal is a global signal provided concurrently to the plurality of pixels.

9. The display device according to claim 1, wherein, The first transistor includes a gate, a first terminal connected to a power line configured to transmit a first power supply voltage, and a second terminal. Wherein, the at least one pixel further includes: The second transistor is configured to transmit a data signal to the first node in response to the first gate signal; The third transistor is configured to connect the gate of the first transistor and the second terminal of the first transistor in response to the second gate signal; A fourth transistor is configured to transfer a first initialization voltage to the gate of the first transistor in response to a third gate signal; The fifth transistor is configured to transmit a reference voltage to the first node in response to the second gate signal; The sixth transistor is configured to transmit a second initialization voltage to the first terminal of the first light-emitting element in response to a fourth gate signal; The seventh transistor is configured to transmit the second initialization voltage to the first terminal of the second light-emitting element in response to the fourth gate signal; A first capacitor is connected between the power line and the first node; and A second capacitor is connected between the first node and the gate of the first transistor.

10. The display device according to claim 1, wherein, The first transistor includes a gate, a first terminal, and a second terminal, and Wherein, the at least one pixel further includes: The second transistor is configured to transmit a data signal to the first terminal of the first transistor in response to the first gate signal; The third transistor is configured to connect the gate of the first transistor and the second terminal of the first transistor in response to the second gate signal; A fourth transistor is configured to transfer a first initialization voltage to the gate of the first transistor in response to a third gate signal; The fifth transistor is configured to transmit a first power supply voltage to the first terminal of the first transistor in response to the transmitted signal; The sixth transistor is configured to transmit a second initialization voltage to the first terminal of the first light-emitting element in response to a fourth gate signal; A seventh transistor is configured to transmit the second initialization voltage to a first terminal of the second light-emitting element in response to the fourth gate signal; and A first capacitor is connected between a power line configured to transmit the first power supply voltage and the gate of the first transistor.

11. An electronic device comprising: processor; as well as The display device according to any one of claims 1 to 6 and 8 to 10 is configured to receive input image data and the mode switching signal and display an image corresponding to the input image data.

12. The electronic device according to claim 11, wherein, The first mode is a public mode, and the second mode is a private mode. The electronic device in question is an automotive electronic device installed in a car, and Wherein, based on the vehicle changing from a stationary state to a moving state, the processor is configured to transmit the mode switching signal indicating a switch from the public mode to the private mode to the panel driver, in which the image displayed from the display device in the public mode is seen by both a first user located in front of the display device and a second user located to the side of the display device, and in which the image displayed from the display device in the private mode is seen by the first user but not by the second user.

13. The electronic device according to claim 12, wherein, Based on the vehicle changing from the moving state to the stationary state, the processor is configured to transmit the mode switching signal indicating a switch from the private mode to the public mode to the panel driver.

14. The electronic device according to claim 11, wherein, The first mode is a public mode, and the second mode is a private mode. Specifically, based on the mode switching signal indicating a switch from the public mode to the private mode, the panel driver is configured to progressively decrease the duty cycle of the first signal and progressively increase the duty cycle of the second signal during a plurality of first frame time periods. Based on the mode switching signal indicating a switch from the private mode to the public mode, the panel driver is configured to gradually increase the duty cycle of the first signal and gradually decrease the duty cycle of the second signal during a plurality of second frame periods.

Images