Memory cell, memory array, and processing method
By incorporating isolation trenches and field oxide regions with different conductivity types in the 2D1R memory structure, the problems of isolation and limited drive current are solved, achieving a high-efficiency memory array performance improvement and a compact resistive random access memory array.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INNOSTAR SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2022-03-16
- Publication Date
- 2026-07-21
AI Technical Summary
The existing 2D1R memory structure has poor isolation, limited drive current, resulting in large voltage drop, which affects SET and RESET operations and leads to poor overall performance.
By using a first diode and a second diode spaced apart from each other, and by setting a deep isolation trench between the n-well and the p-well, and a shallow isolation trench between the doped regions, combined with the difference in conductivity type of the field oxide region, isolated memory cells are formed. The resistive memory is connected to the bit line to achieve efficient driving.
The increased drive current and reduced resistance enhance the isolation and overall performance of the memory array, resulting in a compact 12F^2 resistive random access memory array.
Smart Images
Figure CN116156900B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory technology, and more specifically, to a memory cell, a memory array, and a method for processing the same. Background Technology
[0002] For resistive random access memory (RRAM) or phase-change RAM (PCRAM), the 1T1R (one transistor and one RRAM) array architecture is commonly used. Compared to the 1T1R array architecture, the 2D1R (two diodes and one PCRAM) array architecture can achieve higher operating current, lower leakage current, and higher array density.
[0003] The main drawbacks of the existing 2D1R structure are: the drive current needs to flow through a relatively high-resistance well resistor, which generates a voltage drop. This results in a large voltage drop when the selected resistor, which is far from the well lead, is not conducive to SET and RESET operations, and thus results in a smaller drive current. In addition, if all diodes use the same type of well, the isolation performance between wells will be poor, making it difficult to achieve complete isolation through deep isolation trenches, which affects the overall performance of the circuit. Summary of the Invention
[0004] In view of the above problems, the purpose of this invention is to provide a storage unit, storage array and processing method to solve the problems of poor isolation, limited drive current and poor overall performance of existing storage methods.
[0005] The memory cell provided by the present invention includes a first diode and a second diode arranged at intervals between each other; wherein, the first diode includes an n-well and a first N-type doped region and a first P-type doped region connected to the n-well, and the second diode includes a p-well and a second N-type doped region and a second P-type doped region connected to the p-well; the first N-type doped region is connected to the word line, and the second P-type doped region is connected to the RESET line; the first P-type doped region and the second N-type doped region are respectively connected to the bit line through a resistive memory.
[0006] Alternatively, an optional technical solution is to provide a first contact hole on the first P-type doped region and a second contact hole on the second N-type doped region; the first contact hole and the second contact hole are respectively connected to the first electrode; and the resistive memory is disposed between the first motor and the bit line.
[0007] Alternatively, an alternative technical solution is that the resistive memory is connected to the bit line via a second electrode; the resistive memory is positioned between the first electrode and the second electrode.
[0008] In addition, an alternative technical solution is that the resistive memory includes a phase change material layer and a resistive switching material layer; and the states of the electronic memory include a high-resistivity state and a low-resistivity state.
[0009] In addition, an optional technical solution is to provide a first isolation trench between the first N-type doped region and the first P-type doped region, as well as between two adjacent first P-type doped regions; and to provide a second isolation trench between the second N-type doped region and the second P-type doped region, as well as between two adjacent second N-type doped regions.
[0010] Alternatively, an alternative technical solution is to provide a third isolation trench between the n-well and the p-well.
[0011] In addition, an alternative technical solution is that the depth of the first isolation trench and the second isolation trench is less than the depth of the third isolation trench.
[0012] In addition, an optional technical solution is to include a field oxidation region disposed below the n-well and p-well; wherein the conductivity type of the n-well and p-well is different from that of the field oxidation region.
[0013] According to another aspect of the present invention, a storage array is provided, comprising m n of the above storage units; where m n≥2, and both n and m are positive integers.
[0014] According to another aspect of the present invention, a method for fabricating a memory array is provided, comprising forming an n-well and a p-well on a predetermined substrate by ion implantation; providing a third isolation trench at the junction or edge of the n-well and the p-well, the third isolation trench being used to isolate the n-well and the p-well; providing a first isolation trench and a second isolation trench perpendicular to the extending direction of the third isolation trench on the n-well and the p-well, the first isolation trench being used to isolate the PN junction of a first diode located in the n-well, and the second isolation trench being used to isolate the PN junction of a second diode located in the p-well; and forming N+ and P+ active regions in the n-well and the p-well based on the ion implantation method.
[0015] Using the aforementioned memory cell, memory array, and processing method, a first diode and a second diode are arranged at intervals. The first diode includes an n-well and a first N-type doped region and a first P-type doped region connected to the n-well. The second diode includes a p-well and a second N-type doped region and a second P-type doped region connected to the p-well. The first N-type doped region is connected to the word line, and the second P-type doped region is connected to the RESET line. The first P-type doped region and the second N-type doped region are respectively connected to the bit line through a resistive memory. This not only reduces the overall size but also improves the drive current and overall performance.
[0016] To achieve the foregoing and related objectives, one or more aspects of the invention include the features that will be described in detail below. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to encompass all such aspects and their equivalents. Attached Figure Description
[0017] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings:
[0018] Figure 1 This is a schematic diagram of a storage array circuit according to an embodiment of the present invention;
[0019] Figure 2 This is a flowchart of a storage array fabrication method according to an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of the structure of a storage array processing method according to an embodiment of the present invention. Figure 1 ;
[0021] Figure 4 This is a top view of a storage array according to an embodiment of the present invention;
[0022] Figure 5 for Figure 4 Cross-sectional view at point x1 along the middle edge;
[0023] Figure 6 for Figure 4 Cross-sectional view at x2 along the middle edge;
[0024] Figure 7 for Figure 4 Cross-sectional view at point y1 along the middle edge;
[0025] Figure 8 for Figure 4 Cross-sectional view at point y2 along the middle edge.
[0026] The reference numerals in the figures include: first diode 1, second diode 2, resistor memory 3, first contact hole 4, and first electrode 5.
[0027] In all the accompanying drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed Implementation
[0028] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.
[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0030] To provide a detailed description of the storage unit, storage array, and processing method of the present invention, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0031] Figure 1 A schematic current structure of a memory array according to an embodiment of the present invention is shown; Figure 4 A top view of the storage array according to an embodiment of the present invention is shown; Figure 5 and Figure 6 It shows Figure 4 The cross-sectional structure at x1 and x2 along the middle, Figure 7 and Figure 8 They are shown respectively Figure 4 The cross-sectional structure at points y1 and y2 along the middle.
[0032] like Figures 1 to 8 As shown in the diagram, in the storage section of this embodiment, the structure indicated by the dashed box is the structure of a single storage cell. It can be seen that each storage cell further includes a first diode 1 and a second diode 2 spaced apart from each other. The first diode 1 includes an n-well and a first N-type doped region and a first P-type doped region connected to the n-well. The second diode 2 includes a p-well and a second N-type doped region and a second P-type doped region connected to the p-well. The first N-type doped region is connected to the word line, and the second P-type doped region is connected to the RESET line. The first P-type doped region and the second N-type doped region are respectively connected to the bit line via a resistive memory 3.
[0033] It can be seen that the memory cell in this embodiment of the invention has a 2D1R structure, and a first contact hole 4 can be provided on the first P-type doped region (e.g., Figure 5As shown in the cross-sectional structure of the storage array (hereinafter the same), a second contact hole is provided on the second N-type doped region. The first contact hole 4 and the second contact hole are isolated from each other, and the first contact hole 4 and the second contact hole are respectively connected to the first electrode 5 (e.g., Figure 5 (As shown in the cross-sectional structure of the storage array, the same below) The resistive memory 3 is located between the first motor and the bit line. That is, the first P-type doped region and the second N-type doped region are connected to each other through the first electrode 5 and then connected to the resistive memory 3.
[0034] The other side of the resistive memory 3 can be connected to the bit line through the second electrode. The resistive memory 3 is limited by the first motor and the second electrode, and the first diode 1 and the second diode 2 are led to the bit line through the resistive memory 3.
[0035] As a specific example, the resistive memory 3 may include a phase change material layer and a resistive switching material layer; and the states of the electronic memory include a high-resistivity state and a low-resistivity state. The phase change material layer can switch between amorphous and crystalline states, thereby realizing the switching between high-resistivity and low-resistivity states. The resistive switching material layer can switch between high-resistivity and low-resistivity states under different applied voltages. The phase change material layer may be a doped or undoped chalcogenide, such as Ge₂Sb₂Te₅ or Sb₂Te₃. Furthermore, the resistive switching material layer may include one or more of SiO₂, NiO, CuXO, and TiO₂.
[0036] In one specific embodiment of the present invention, in order to isolate the first diode 1 and the second diode 2, a first isolation trench is provided between the first N-type doped region and the first P-type doped region, and between two adjacent first P-type doped regions; a second isolation trench is provided between the second N-type doped region and the second P-type doped region, and between two adjacent second N-type doped regions. The first isolation trench and the second isolation trench can be understood as shallow isolation trenches distributed in a strip shape.
[0037] In addition, a third isolation trench is provided at the edge of the n-well and the p-well or at the junction of the two. This isolation trench can be understood as a deep isolation trench with a direction perpendicular to the first isolation trench and the second isolation trench. The depth of the third isolation trench is greater than the depth of the first isolation trench and the second isolation trench. That is, the third isolation trench is used to isolate the n-well and the p-well, while the first isolation trench is used to isolate the adjacent first N-type doped region and / or first P-type doped region in the n-well, and the second isolation trench is used to isolate the second N-type doped region and / or second P-type doped region in the p-well.
[0038] In another specific embodiment of the present invention, the storage unit further includes a field oxide region disposed below the n-well and p-well; wherein the conductivity type of the n-well and p-well is different from the conductivity type of the field oxide region; wherein the conductivity type of the n-well is the same as that of the p-well, both being N-type or P-type, but the conductivity type of the field oxide region is different from both of them. When the conductivity type of the n-well and p-well is N-type, the conductivity type of the field oxide region is P-type, and correspondingly, when the conductivity type of the n-well and p-well is P-type, the conductivity type of the field oxide region is N-type.
[0039] As can be seen, for the aforementioned memory cells, the n-wells and p-wells are isolated by deep isolation trenches. Each n-well forms a pn junction through a p-type active region (i.e., the first P-type doped region), and each p-well forms a pn junction through an n-type active region (the second N-type doped region). For each p-type active region in an n-well, there is an adjacent n-type n-well lead-out terminal; similarly, for each n-type active region in a p-well, there is an adjacent p-type p-well lead-out terminal. This effectively reduces the well resistance in the pn junction array, enabling a compact 12F^2 resistive random access memory array while effectively increasing the drive current.
[0040] Corresponding to the aforementioned storage unit, the present invention also provides a storage array, including m n storage units as described in the above embodiment; wherein, m n≥2, and both n and m are positive integers.
[0041] In this configuration, the resistive memory in the memory cell of the j-th column is connected to the bit line of the j-th column, 1≤j≤n; the first N-type doped region of the memory cell of the i-th row is connected to the word line of the i-th row; and the second P-type doped region of the memory cell of the i-th row is connected to the RESET line of the i-th row, 1≤i≤m.
[0042] Specifically, resistive memory can perform READ, SET, and RESET operations on the memory array. Furthermore, Figure 1 In the diagram, BL represents the bit line, WL represents the word line, and R / L represents the RESET line. The voltages for the above operations of the memory array are shown in the table below.
[0043]
[0044] During the reading process, for selected memory cells in the memory array, BL is Vrd voltage and WL is 0V. R / L is set to 0V regardless of whether it is selected or not, which can suppress leakage through R / L. For unselected BL, 0V is added and for unselected WL, Vrd voltage is added to suppress leakage from selected BL to unselected WL.
[0045] During the write process, for selected memory cells, BL is set to Vset voltage and WL is 0V. R / L is always set to 0V regardless of whether a cell is selected, to suppress leakage current through R / L. For unselected cells, BL is set to 0V, and WL is set to Vset voltage to suppress leakage current between selected cells (BL and WL). During both the read and write processes, the RESET line needs to suppress leakage current, so it is always set to 0V.
[0046] During the RESET process, taking RRAM as a resistive memory as an example, a RESET voltage is applied to the RESET line of the selected RRAM cell, and 0V is applied to BL. For unselected BL cells, a RESET voltage is applied to suppress leakage current, thereby preventing RRAM cells with selected RESET lines but unselected BL cells from being reset. At this time, a RESET voltage is applied to all WL cells to suppress leakage current paths. In this invention, the Vrd voltage is generally 0.3V to 1V, the Vset voltage is generally 2.0V to 3.5V, and the Vreset voltage is generally 1.5V to 3.5V. The specific values can be flexibly set according to the application scenario or requirements.
[0047] During the read operation, the current flows from BL to WL. Since the diode on the RESET line is reverse biased and the diode can achieve a leakage current of <1e-12A, it can be seen from the table above that the Vwl voltage is greater than or equal to Vrl under any circumstances. The reverse bias effect of the n-well and p-well can be used to maintain a good process window while achieving isolation.
[0048] Correspondingly, the present invention also provides a method for processing a storage array, specifically, Figure 2 A flowchart of a storage array processing method according to an embodiment of the present invention is shown.
[0049] like Figure 2 As shown, the storage array processing method of this invention includes:
[0050] S110: An n-well and a p-well are formed on a pre-defined substrate by ion implantation;
[0051] S120: A third isolation groove is provided at the junction or edge of the n-well and the p-well, the third isolation groove is used to isolate the n-well and the p-well;
[0052] S130: A first isolation trench and a second isolation trench perpendicular to the extension direction of the third isolation trench are provided on the n-well and the p-well. The first isolation trench is used to isolate the PN junction of the first diode located in the n-well, and the second isolation trench is used to isolate the PN junction of the second diode located in the p-well.
[0053] S140: Based on ion implantation, active regions of N+ and P+ are formed in the n-well and p-well.
[0054] Specifically, Figure 3 A schematic structure of an n-well and a p-well according to an embodiment of the present invention is shown.
[0055] like Figure 3 refer to Figure 8 As shown in the diagram, during the fabrication of the memory array, n-wells and p-wells are first formed on the substrate via ion implantation, and then a third isolation trench, namely the deep trench (DTI), is formed by etching. The top view of the process at this stage is shown below. Figure 3 As shown, the n-well (NW) and p-well (PW) are represented semi-transparently to indicate their correspondence with the DTI. The diagram shows that the opening size of the n-well and p-well is 2F, the center-to-center distance is 4F, and the shape is a regular strip. Deep trenches are located at the junction of the n-well and p-well, as well as on the sides of the first n-well and the last p-well. The width of a single deep trench is 2F.
[0056] Furthermore, after the deep trench region is formed, a shallow trench region (STI) is formed through an etching process. Subsequent filling and polishing processes then create separate n-well and p-well regions, along with a separate active region. Specifically, deep trench isolation (DTI) effectively isolates the n-well and p-well, while STI isolates the PN junction inside the diode.
[0057] Then, N+ and P+ active regions are formed separately through ion implantation, resulting in a top-view structure as shown below. Figure 4 As shown, the area marked by the dashed line represents a single 2D1R cell with a size of 12F^2. The RRAM storage array is then formed by connecting the CT and Metal lines to the RRAM resistor array. (See top view of the structure.) Figure 4 The cross-sectional view of the middle x1 section is as follows Figure 5 The p+ active region in the n-well is connected to the n+ active region in the p-well and is also connected to the bottom of the RRAM, while the top of the RRAM is connected to the BL. (View from top) Figure 4 Cross-sectional view of the middle x2 section as shown Figure 6 The n-well and p-well are connected to the WL and RESET LINE respectively via the n+ and p+ leads. (View from top) Figure 4 The cross-sectional view of Y1 is as follows Figure 7 Each n+ will draw out an n-well to form a WL. (See top view) Figure 4 The cross-sectional view of the middle y2 section is as follows Figure 8 Each p+ leads out a p-well to form a RESET line. The 2D1R method of this invention can form a relatively small 12F^2 RRAM memory array while providing a large drive current.
[0058] It should be noted that the above-mentioned memory array is not only applicable to RRAM, but also to various types of new memories such as MRAM, PCRAM, and FERAM. In addition, the formation order of DTI, STI and n-well and p-well during the formation process is not limited to the specific order mentioned above. For example, ATI can be formed first, then n-well and p-well can be formed, and finally DTI can be formed.
[0059] Furthermore, the embodiments of the above-mentioned storage units, storage arrays, and processing methods can be referenced and learned from each other, and will not be described in detail here.
[0060] According to the memory cell, memory array and processing method provided by the present invention, a memory array with a size of 12F^2 can be formed. Each pn junction formed will have a well end, which reduces resistance and increases drive current. This not only reduces the overall size, but also improves drive current and overall performance.
[0061] The storage cell, storage array, and processing method according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various modifications can be made to the storage cell, storage array, and processing method proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.
Claims
1. A storage unit, characterized in that, It includes a first diode and a second diode arranged at intervals from each other; wherein, The first diode includes an n-well and a first N-type doped region and a first P-type doped region connected to the n-well; the second diode includes a p-well and a second N-type doped region and a second P-type doped region connected to the p-well. The first N-type doped region is connected to the word line, and the second P-type doped region is connected to the RESET line; The first P-type doped region and the second N-type doped region are respectively connected to the bit line via a resistive memory; wherein... The first P-type doped region in the n-well is connected to the second N-type doped region in the p-well and is connected to the bottom of the resistive memory. The top of the resistive memory is connected to the bit line; For the first P-type doped region in each n-well, there is an adjacent n-well lead-out; for the second N-type doped region in each p-well, there is an adjacent p-well lead-out, in order to reduce the well resistance in the pn junction array.
2. The storage unit as claimed in claim 1, characterized in that, A first contact hole is provided on the first P-type doped region, and a second contact hole is provided on the second N-type doped region; The first contact hole and the second contact hole are respectively connected to the first electrode; The resistive memory is disposed between the first electrode and the bit line.
3. The storage unit as described in claim 2, characterized in that, The resistive memory is connected to the bit line via a second electrode; The resistive memory is positioned between the first electrode and the second electrode.
4. The storage unit as claimed in claim 1, characterized in that, The resistive memory includes a phase change material layer and a resistive switching material layer; and... The states of the resistive memory include a high-resistance state and a low-resistance state.
5. The storage unit as claimed in claim 1, characterized in that, A first isolation trench is provided between the first N-type doped region and the first P-type doped region, as well as between two adjacent first P-type doped regions. A second isolation trench is provided between the second N-type doped region and the second P-type doped region, as well as between two adjacent second N-type doped regions.
6. The storage unit as claimed in claim 5, characterized in that, A third isolation groove is provided between the n-well and the p-well.
7. The storage unit as claimed in claim 6, characterized in that, The depths of the first isolation groove and the second isolation groove are less than the depth of the third isolation groove.
8. The storage unit as claimed in claim 1, characterized in that, It also includes a field oxidation region disposed below the n-well and the p-well; wherein, The conductivity type of the n-well and the p-well is different from that of the field oxidation region.
9. A storage array, characterized in that, Including m n storage units as described in any one of claims 1 to 8; wherein, m n≥2, and both n and m are positive integers.
10. A method for fabricating a storage array, characterized in that, include: n-wells and p-wells are formed on a pre-defined substrate by ion implantation; A third isolation groove is provided at the junction or edge of the n-well and the p-well, the third isolation groove being used to isolate the n-well and the p-well; A first isolation trench and a second isolation trench perpendicular to the extension direction of the third isolation trench are provided on the n-well and the p-well. The first isolation trench is used to isolate the PN junction of the first diode located in the n-well, and the second isolation trench is used to isolate the PN junction of the second diode located in the p-well. Based on ion implantation, active regions of N+ and P+ are formed in the n-well and the p-well.