Scan chain design and circuit testing method

Abstract

The application provides a scan chain design method, comprising: obtaining a plurality of test points according to a gate level netlist; determining positive integers M and N, wherein M and N are not greater than the number X of the test points; taking out M and N test points as first and second groups of test points respectively from the test points according to a priority condition; obtaining a first test coverage and a first test pattern number according to the first group of test points, and obtaining a second test coverage and a second test pattern number according to the second group of test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimized number O according to the predicted test coverage curve, the first and second test pattern numbers, wherein O is not greater than the number X; and selecting O test points from the test points according to the priority condition and the optimized number O, and configuring a scan chain in this way.

Description

Technical Field

[0001] This invention relates to a testing method, and more particularly to a method for designing and testing a scan chain circuit. Background Technology

[0002] In circuit testing using scan chains, the placement of test points within the scan chain is crucial to test efficiency. Inefficient test points in the scan chain waste circuit area. Insufficient test points result in inadequate test coverage. Therefore, proper scan chain design has become a key concern in this technical field. Summary of the Invention

[0003] This invention provides a scan chain design method, comprising: obtaining multiple test points of a target circuit based on a gate-level netlist of the target circuit; determining a first value M and a second value N, wherein M and N are positive integers not greater than the number of these test points, and N is not equal to M; selecting M test points from these test points as a first group of test points according to a priority condition, and selecting N test points from these test points as a second group of test points; obtaining a first test coverage and a first number of test modes based on the first group of test points, and obtaining a second test coverage and a second number of test modes based on the second group of test points; obtaining a predicted test coverage curve based on the first test coverage and the second test coverage; determining an optimization quantity O based on the predicted test coverage curve, the first number of test modes, and the second number of test modes, wherein O is a positive integer not greater than the number of these test points; and selecting O test points from these test points according to the priority condition and the optimization quantity O, and configuring the scan chain of the gate-level netlist accordingly.

[0004] The present invention also provides a circuit testing method, comprising: determining X test points of the target circuit based on the gate-level netlist of the target circuit, wherein X is a positive integer; obtaining a sorting order based on priority conditions of the X test points; obtaining the predicted test coverage curves corresponding to the X test points; determining an optimized number of O test points based on the predicted test coverage curves, wherein the slope of the optimized number of O test points in the predicted test coverage curves is not greater than a threshold, and O is a positive integer not greater than X; inserting the first to the Oth test points in the sorting order into the initial scan chain of the gate-level netlist to generate a scan chain; and testing the target circuit based on the scan chain.

[0005] The scan chain design method and circuit testing method of this invention sort all test points in the target circuit, obtain a corresponding test coverage curve according to the sorting priority, and then determine the optimal number of test points from the test coverage curve to set the scan chain. The optimal number of test points obtained by this invention ensures sufficient test coverage, reasonable circuit area, and test time when using scan chain testing. Attached Figure Description

[0006] The various embodiments of this application can be best understood by reading the detailed description and the accompanying drawings below. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1 This is a schematic diagram of the scan chain and target circuit in some embodiments of the present invention.

[0008] Figure 2 This is a flowchart illustrating a method for designing a scan chain and testing a target circuit based on the designed scan chain in some embodiments of the present invention.

[0009] Figure 3 This is a schematic diagram of the predicted test coverage curve and the test mode number curve in some embodiments of the present invention.

[0010] Figure 4 and Figure 5 This is a schematic diagram of the predicted test coverage curve and the test mode number curve in other embodiments of the present invention.

[0011] Explanation of reference numerals in the attached figures:

[0012] 10-Scan Chain 20-Target Circuit SI-Scan Input Terminal

[0013] SO - Scan output terminal; ST - Test signal; SC - Control signal

[0014] SDFF-Trigger TP-Test Point 200-Method

[0015] 201-Step 202-Step 203-Step

[0016] 204-Step 205-Step 206-Step

[0017] 207-Step 208-Step 209-Step

[0018] 210 - Step 30 - Predict Test Coverage 31 - First Part Curve

[0019] 32-Part Two 40-Test Pattern Count Curve C0-Test Coverage

[0020] C1 - Test Coverage; C2 - Test Coverage; Copt - Optimal Test Coverage

[0021] P0 - Number of test modes P1 - Number of test modes P2 - Number of test modes

[0022] Popt - Optimal number of test modes OS - Points M - Number of test points

[0023] N - Number of test points A - Number of test points X - Number of test points

[0024] O - Optimization quantity TN - Turning point Detailed Implementation

[0025] Figure 1 This is a schematic diagram of the scan chain 10 and the target circuit 20 in some embodiments of the present invention. In some embodiments, the target circuit 20 represents a logically functional part of a chip, and the scan chain 10 is the part of the chip used to test the target circuit 20 during a scan phase.

[0026] In some embodiments, the scan chain 10 includes a portion of the nodes in the target circuit 20. Specifically, the scan chain 10 includes a plurality of flip-flops SDFFs, wherein these flip-flops SDFFs are nodes in the target circuit 20. The scan chain 10 uses these flip-flops SDFFs to set the target circuit 20 and scans the state of these flip-flops SDFFs to detect the state of the target circuit 20. In some embodiments, the flip-flops SDFFs are also referred to as sequential element scan flip-flops. The scan chain 10 also includes a test point TP. The test point TP does not belong to the target circuit 20 and is used to input and / or receive signals from a node in the target circuit 20. The flip-flops SDFFs and the test point TP are connected in series to form the scan chain 10. In some embodiments, the test point TP can be set at any position in the scan chain 10, and the invention is not limited to this. Figure 1 The sorting method of scan chain 10 is shown.

[0027] During the scanning phase, the scan input terminal SI of scan chain 10 is used to receive the test signal ST and transmits the test signal into scan chain 10 according to the clock signal. The flip-flop SDFF and test point TP are respectively connected to the target circuit 20 and are used to transmit the received test signal ST into the target circuit 20. The scan output terminal SO of scan chain 10 is used to output the test result. In some embodiments, the test signal ST is generated by an automatic test pattern generation (ATPG) system.

[0028] In some embodiments, the test point TP is divided into a control point and an observation point. The control point is used to control the signal input to the target circuit 20, while the observation point is used to receive the signal output by the target circuit 20. Specifically, the control point may receive a control signal SC independently of the test signal ST, and use this control signal to input the control signal into the target circuit 20. The observation point is used to output at least a portion of the test result from the signal output by the target circuit 20 at the scan output terminal SO.

[0029] A higher number of test points (TPs) in scan chain 10 indicates a greater number of testable and observable nodes in the target circuit 20, meaning higher test coverage. Higher test coverage provides greater testability for the chip. Generally, scan testing is required before a chip is taped out, and scan testing has a minimum coverage requirement to ensure proper chip functionality. Therefore, higher test coverage not only provides more reliable test results but also makes it easier to meet the minimum test coverage requirement.

[0030] However, the more test points TP there are in the scan chain 10, the larger the circuit area occupied by the test points TP becomes. Furthermore, the number of samples of the test signal ST (also known as the test mode) increases with the complexity of the target circuit 20. As the number of test modes (hereinafter referred to as the number of test modes) increases, the test time required by the chip during the scanning phase also increases. Therefore, this invention provides a method 200 (such as...) Figure 2 (As shown) This method aims to achieve a balance between test coverage, circuit area occupied by test points TP, and the number of test modes, ensuring that the scan chain 10 of the chip meets the minimum test coverage requirements without consuming excessive circuit area for test points TP or using too many test modes. Method 200 is used to design the scan chain 10 and test the target circuit 20 based on the designed scan chain 10. In some embodiments, at least a portion of method 200 is performed by an electronic design automation (EDA) tool. Method 200 includes steps 201 to 210. For ease of understanding, method 200 follows... Figure 1 The symbols in the text are used to illustrate this.

[0031] In step 201, the register transfer level (RTL) of the target circuit 20 is obtained. In step 202, the RTL is converted into a gate-level netlist of the target circuit 20. In some embodiments, an initial scan chain is obtained based on the gate-level netlist, wherein when the target circuit 20 is scanned using the initial scan chain, the test coverage is C0 (hereinafter referred to as C0). Figure 3 (Details) and the required number of test modes is P0 (later discussed) Figure 3 (Detailed explanation).

[0032] In step 203, X test points TP of the target circuit 20 are obtained based on the gate-level netlist of the target circuit 20, where X is a positive integer greater than 1. All nodes in the gate-level netlist of the target circuit 20 are evaluated, and a subset of nodes are selected as test points TP. In some embodiments, the selected nodes are those in the target circuit 20 that have a certain degree of influence on the computational results (and / or test results) generated in the target circuit 20. Specifically, when these selected nodes are input with different values, the computational results of the target circuit 20 will differ. Or, when the signals received by the target circuit 20 are different, these selected nodes will receive different computational results from the target circuit 20. In some embodiments, these test points TP are also sorted according to a priority condition, where the priority condition is the degree of influence of these nodes on the computational results of the target circuit 20. When a node is the most influential node among multiple nodes, that node is ranked as the first node in the sorting of these test points TP.

[0033] In step 204, values ​​M and N are determined, where M and N are positive integers not greater than X, and M and N are not equal. In some embodiments, M and N are approximately determined to be around 1 / 3 or 1 / 4 of X. In step 205, M test points are selected from the X test points TP according to priority conditions as a first group of test points, and N test points are selected from the X test points TP as a second group of test points. Specifically, since the test points TP form a sort according to priority conditions, the first group of test points includes the first to the Mth test points TP in the sorted order of the X test points TP. Similarly, the second group of test points includes the first to the Nth test points TP in the sorted order of the X test points TP.

[0034] In step 206, a first test coverage rate C1 and a first test mode number P1 are obtained based on the first set of test points, and a second test coverage rate C2 and a second test mode number P2 are obtained based on the second set of test points. In step 207, a predicted test coverage curve 30 is obtained based on the first test coverage rate C1 and the second test coverage rate C2. Figure 3This is a schematic diagram of the predicted test coverage curve 30 and the test pattern number curve 40 in some embodiments of the present invention. The predicted test coverage curve 30 and the test pattern number curve 40 are curves showing the predicted test coverage and the number of test patterns corresponding to the number of test points (TPs), respectively. Figure 3 It can be seen that when the number of test points (TPs) increases, the test coverage increases and the number of test modes decreases.

[0035] The first and second sets of test points are inserted into the initial scan chains to generate the first and second scan chains, respectively. In some embodiments, the ATPG system calculates the required number of test patterns based on the scan chain configuration. Then, the ATPG system generates P1 and P2 test patterns respectively and inputs them into the first and second scan chains to obtain the first test coverage C1 and the second test coverage C2. Next, the first test coverage C1 and the second test coverage C2 are fitted to obtain the predicted test coverage curve 30, and the corresponding test pattern count curve 40 is obtained based on the predicted test coverage curve 30.

[0036] In some embodiments, the predicted test coverage curve 30 is obtained by fitting a polynomial equation and an exponential equation. Specifically, when the number of test points is no greater than A, the EDA tool fits the first part 31 of the predicted test coverage curve 30 with a polynomial equation, and when the number of test points is greater than A and less than X, the EDA tool fits the second part 32 of the predicted test coverage curve 30 with an exponential equation. For example, the predicted test coverage curve 30 can be represented by equations (1) and (2):

[0037] y = a1x 2 +b1x+c1;ifX≤A (1);

[0038]

[0039] Where x is the number of test points; y is the test coverage; and a1, a2, b1, b2, c1, and c2 are fitting constants. However, the present invention is not limited thereto, and various suitable fitting methods are within the scope of protection of the present invention.

[0040] In step 208, an optimal number O of test points TP is determined based on the predicted test coverage curve 30, the first number of test modes P1, and the second number of test modes P2, where O is a positive integer not greater than X. As shown by the predicted test coverage curve 30, the test coverage does not change significantly when the number of test points TP is close to X. Although continuously increasing the number of test points TP can continuously increase the test coverage, the rate of increase gradually decreases. Furthermore, although continuously increasing the number of test points TP can continuously decrease the number of test modes, the rate of decrease gradually decreases. Therefore, within the range above the minimum test coverage limit, the optimal number O is selected by evaluating the rate of increase in test coverage, the rate of decrease in the number of test modes, and the circuit area occupied by increasing the number of test points TP, to achieve a balance that avoids excessive circuit area or excessively long test times in order to obtain a larger test coverage. It should be noted that in this embodiment, the number of test modes and test time are positively correlated, and test time is positively correlated with test cost; therefore, reducing the number of test modes means reducing test time and test cost. For example, reducing the number of test patterns by 20% can roughly reduce testing time by 20%, which in turn reduces testing costs by approximately 20%. With 0 test points (TPs), the optimal test coverage (Copt) and optimal number of test patterns (Popt) can be obtained.

[0041] In some embodiments, the predicted test coverage curve 30 is a monotonically increasing function, and the rate of increase decreases as the number of test points (TPs) increases. Therefore, the slope of the predicted test coverage curve 30 also decreases as the number of test points (TPs) increases. The optimal number O can be determined based on the slope of the predicted test coverage curve 30. For example, the optimal number O can be determined by finding the number of test points where the slope of the predicted test coverage curve 30 is no greater than a threshold.

[0042] In other embodiments, the correspondence between the predicted test coverage curve 30 and the test pattern number curve 40 is as follows: Figure 3 Different. For example... Figure 4 and Figure 5 As shown. With Figure 3 In comparison, Figure 4 The test pattern count curve 40 shows a clear inflection point when the predicted test coverage curve 30 has entered the saturation stage (Part 2, 32). Because the change in the test pattern count after TN at this inflection point approaches saturation, in order to efficiently reduce the test pattern count, the number of test points TP corresponding to TN at this inflection point is determined to be the optimal number O. Figure 3 compared to, Figure 5 The number of test modes curve 40 decreases smoothly with the number of test points TP, so the optimal number O is determined only based on the change of the predicted test coverage curve 30.

[0043] In some existing technologies, in order to obtain higher test coverage, too many test points are inserted into the scan chain, for example... Figures 3-5 The point OS is shown in the figure. According to the method of the present invention, the scan chain 10 can be set in a better balance state, which not only reduces the number of test points TP and test modes, but also maintains the test coverage at a minimum.

[0044] In step 209, O test points TP from X test points TP are selected according to priority conditions, and the scan chain of the gate-level netlist is configured accordingly. The selected O test points TP are inserted into the initial scan chain, and the O test points TP are substantially set in the scan chain 10 on the chip. In step 210, the ATPG system generates a test pattern of Potp and transmits it to the scan chain 10 with O test points TP to perform scan testing on the target circuit 20.

[0045] The foregoing description briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to more fully understand the various implementations of this application. Those skilled in the art should understand that other programs and structures can be easily designed or modified based on this application to achieve the same purpose and / or the same effect as these embodiments. Those skilled in the art should understand that these equivalent implementations still fall within the spirit and scope of this application and can be modified, substituted, and altered in various ways without departing from the spirit and scope of this application.

Claims

1. A scan chain design method, comprising: Multiple test points of the target circuit are obtained based on a gate-level netlist of the target circuit; Determine a first value M and a second value N, where M and N are positive integers not greater than the number of the plurality of test points, and N is not equal to M; Based on a priority condition, M test points are selected from the plurality of test points as a first group of test points, and N test points are selected from the plurality of test points as a second group of test points. The priority condition is the degree of influence of each test point on the operation result of the target circuit. A first test coverage and a first number of test modes are obtained based on the first set of test points, and a second test coverage and a second number of test modes are obtained based on the second set of test points; A predicted test coverage curve is obtained based on the first test coverage and the second test coverage; An optimal number O is determined based on the predicted test coverage curve, the number of the first test modes, and the number of the second test modes, where O is a positive integer not greater than the number of the plurality of test points; and Based on the aforementioned priority conditions and the aforementioned optimization quantity O, O test points are selected from the plurality of test points, and a scan chain of the gate-level netlist is configured accordingly.

2. The scan chain design method according to claim 1, characterized in that, Also includes: Obtain a register transfer stage of the target circuit; and The register transfer level is converted into the gate-level netlist.

3. The scan chain design method according to claim 1, characterized in that, Also includes: Multiple test modes generated by an automatic test mode generation system are fed into the scan chain to test the target circuit.

4. The scan chain design method according to claim 1, characterized in that, The gate-level netlist corresponds to an initial scan chain. In the step of selecting O test points from the plurality of test points according to the priority conditions and the optimization quantity, and configuring the scan chain of the gate-level netlist accordingly, the O test points are inserted into the initial scan chain to configure the scan chain.

5. The scan chain design method according to claim 4, characterized in that, The steps for obtaining the predicted test coverage curve based on the first test coverage and the second test coverage include: Insert the first to the Nth test point from the priority conditions into the initial scan chain to generate a first scan chain; Insert the first to the Mth test points from the aforementioned priority conditions into the initial scan chain to generate a second scan chain; and Multiple test patterns generated by an automatic test pattern generation system are loaded into the first scan chain and the second scan chain to generate a first test coverage and a second test coverage, respectively.

6. The scan chain design method according to claim 5, characterized in that, The step of obtaining the predicted test coverage curve based on the first test coverage and the second test coverage further includes: The predicted test coverage curve is fitted based on the first test coverage and the second test coverage.

7. A circuit testing method, comprising: X test points of the target circuit are determined based on a gate-level netlist of the target circuit, where X is a positive integer; A ranking is obtained based on the X test points and a priority condition, wherein the priority condition is the degree of influence of each test point on the operation result of the target circuit; Obtain a predicted test coverage curve corresponding to the X test points; Based on the predicted test coverage curve, an optimal number of O test points is determined. The slope of the predicted test coverage curve corresponding to the optimal number of O test points is not greater than a threshold, and O is a positive integer not greater than X. Insert the first to the 0th test points in the sorted sequence into an initial scan chain of the gate-level netlist to generate a scan chain; and The target circuit is tested according to the scan chain.

8. The circuit testing method according to claim 7, characterized in that, The steps for obtaining the predicted test coverage curves corresponding to the X test points include: Insert the first to the Nth test points in the sorted sequence into the initial scan chain to generate a first scan chain; Insert the first to the Mth test points from the sorted sequence into the initial scan chain to generate a second scan chain; and Multiple test patterns generated by an automatic test pattern generation system are loaded into the first scan chain and the second scan chain to generate a first test coverage and a second test coverage, respectively.

9. The circuit testing method according to claim 8, characterized in that, The step of obtaining the predicted test coverage curves corresponding to the X test points further includes: The predicted test coverage curve is fitted based on the first test coverage and the second test coverage.

10. The circuit testing method according to claim 9, characterized in that, The step of fitting the predicted test coverage curve based on the first test coverage and the second test coverage includes: A first portion of the predicted test coverage curve is fitted according to a polynomial equation; and The second part of the predicted test coverage curve is fitted according to an exponential equation.

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