An adjustable voltage charge pump circuit and device

Abstract

This invention provides an adjustable voltage charge pump circuit and device. The circuit includes a voltage multiplier module, a voltage booster module, and a voltage output module. The voltage multiplier module, the voltage booster module, and the voltage output module are all connected to a clock module. The voltage multiplier module is connected to the voltage booster module. The voltage multiplier module generates a voltage multiplier signal based on the clock signal and outputs the voltage multiplier signal to the voltage booster module. The voltage booster module generates a boost signal based on the clock signal and the voltage multiplier signal and outputs the boost signal to the voltage output module. The voltage output module generates an output signal based on the clock signal and the boost signal. This application has the advantages of a wider voltage range for the circuit output signal and greater flexibility in adjusting the circuit output signal.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number 202310254947.4, application date March 16, 2023, invention title: A charge pump circuit and device with adjustable voltage). Technical Field

[0002] This invention belongs to the field of charge pump technology, specifically relating to an adjustable voltage charge pump circuit and device. Background Technology

[0003] As technology advances, system applications are increasingly moving towards lower supply voltages, and circuit and system designs are migrating to deeper submicron levels. Typically, in such processes, the supply voltage is reduced to 1.5V or less. Because many low-supply-voltage and switched-capacitor systems require high voltage to drive analog switches, a charge pump circuit is needed to obtain a DC voltage higher than the supply voltage.

[0004] In related technologies, a traditional multiplier charge pump is typically used to obtain a DC voltage higher than the power supply voltage. A traditional multiplier charge pump includes a clock circuit that generates an alternating clock signal, two capacitors for filtering, and two NMOS transistors. Because the operating principle of the charge pump circuit is limited by the precision of the components, the output voltage range is restricted based on the clock signal voltage range. Furthermore, since the charge pump circuit is an active circuit, its output is affected by input parameters (such as capacitors and resistors) and the input voltage. Since these parameters are fixed, the adjustable range of the charge pump circuit's output voltage is also limited. Summary of the Invention

[0005] This invention provides a charge pump circuit and device with adjustable voltage.

[0006] In a first aspect, the present invention provides an adjustable voltage charge pump circuit, the circuit including a clock module for providing a clock signal, the circuit further including a voltage multiplier module, a voltage boosting module, and a voltage output module, the voltage multiplier module, the voltage boosting module, and the voltage output module all being connected to the clock module, the voltage multiplier module being connected to the voltage boosting module, the voltage multiplier module generating a voltage multiplier signal based on the clock signal and outputting the voltage multiplier signal to the voltage boosting module, the voltage boosting module generating a boosting signal based on the clock signal and the voltage multiplier signal and outputting the boosting signal to the voltage output module, the voltage output module generating an output signal based on the clock signal and the boosting signal, the voltage range of the output signal being greater than twice the voltage range of the clock signal.

[0007] Optionally, the voltage multiplier module includes a first voltage multiplier charge pump unit and a voltage multiplier auxiliary unit. The first voltage multiplier charge pump unit is connected to the voltage multiplier auxiliary unit, and the voltage multiplier auxiliary unit is connected to the boost module. The first voltage multiplier charge pump unit and the voltage multiplier auxiliary unit generate the voltage multiplier signal based on the clock signal, and the voltage multiplier auxiliary unit outputs the voltage multiplier signal to the boost module.

[0008] Optionally, the first voltage doubler charge pump unit includes capacitors C1, C2, C3, and C4, NMOS transistors M1, M2, M3, and M4. One end of each of capacitors C1 and C4 is connected to one end of the clock module, and one end of each of capacitors C2 and C3 is connected to the other end of the clock module. The other end of capacitor C1 is connected to the source of NMOS transistor M1 and the gate of NMOS transistor M2. The other end of the capacitor is connected to the gate of the NMOS transistor M1 and the source of the NMOS transistor M2. The other end of the capacitor C3 is connected to the source of the NMOS transistor M3 and the gate of the NMOS transistor M4. The other end of the capacitor C4 is connected to the gate of the NMOS transistor M3 and the source of the NMOS transistor M4. The drain of the NMOS transistor M1, the drain and gate of the NMOS transistor M2, the drain of the NMOS transistor M3, and the drain and gate of the NMOS transistor M4 are all connected to the voltage multiplier auxiliary unit.

[0009] Optionally, the voltage multiplier auxiliary unit includes capacitor C5, capacitor C6, NMOS transistor M5, and NMOS transistor M6. The gate of NMOS transistor M5 is connected to the gate of NMOS transistor M4, and the gate of NMOS transistor M6 is connected to the gate of NMOS transistor M2. The drains of NMOS transistors M1, M2, M3, M4, M5, and M6 are connected in series. The source of NMOS transistor M5 is connected to one end of capacitor C5 and the voltage boosting module. The source of NMOS transistor M6 is connected to one end of capacitor C6 and the voltage boosting module. The other end of capacitor C5 is connected to one end of the clock module, and the other end of capacitor C6 is connected to the other end of the clock module and the voltage boosting module.

[0010] Optionally, the voltage multiplier module includes a second voltage multiplier charge pump unit and an inverting unit. The second voltage multiplier charge pump unit is connected to the inverting unit, and the inverting unit is connected to the boosting module. The second voltage multiplier charge pump unit generates the voltage multiplier signal based on the clock signal. The inverting unit inverts the voltage multiplier signal and outputs the inverted voltage multiplier signal to the boosting module.

[0011] Optionally, the second voltage doubler charge pump unit includes capacitor C1, capacitor C2, PMOS transistor M1, and PMOS transistor M2. Capacitor C1 is connected to one end of the clock module, capacitor C2 is connected to the other end of the clock module, the other end of capacitor C1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2, the other end of capacitor C2 is connected to the gate of PMOS transistor M1 and the drain of PMOS transistor M2, and the drain and source of PMOS transistor M2, as well as the source of PMOS transistor M1, are all connected to the inverting unit.

[0012] Optionally, the inverting unit includes PMOS transistors M3, M4, M5, M6, M7, and M8. The sources of PMOS transistors M1, M2, M3, M5, and M7 are connected in series. The drain of PMOS transistor M2 is connected to the gates of PMOS transistors M3 and M4. The drains of PMOS transistors M3 and M4 are connected to the gates of PMOS transistors M5 and M6. The drains of PMOS transistors M5 and M6 are connected to the gates of PMOS transistors M7 and M8. The drains of PMOS transistors M7 and M8, and the sources of NMOS transistors M4, M6, and M8 are all connected to the boost module.

[0013] Optionally, the boost module includes a PMOS transistor m1 and an NMOS transistor m2. The gate input of the PMOS transistor m1 has a first reference voltage, and the gate input of the NMOS transistor m2 has a second reference voltage. The drains of the PMOS transistor M7 and the NMOS transistor M8 are both connected to the source of the PMOS transistor m1. The sources of the NMOS transistors M4, M6, and M8 are all connected to the source of the NMOS transistor m2. The source of the NMOS transistor m2 is also connected to one end of the clock module. The drains of the PMOS transistor m1 and the NMOS transistor m2 are both connected to the voltage output module.

[0014] Optionally, the voltage output module includes capacitor C1, capacitor C2, NMOS transistor M3, and NMOS transistor M4. The drains of both PMOS transistor M1 and NMOS transistor M2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to the source of NMOS transistor M3 and the gate of NMOS transistor M4. One end of capacitor C2 is connected to one end of the clock module. The other end of capacitor C2 is connected to the gate of NMOS transistor M3 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is used to output the output signal.

[0015] In a second aspect, the present invention also provides an apparatus comprising a voltage-adjustable charge pump circuit as described in the first aspect.

[0016] The beneficial effects of this invention are as follows: The circuit of this invention includes a voltage multiplier module, a voltage boosting module, and a voltage output module. All three modules are connected to the clock module. The voltage multiplier module is connected to the voltage boosting module. The voltage multiplier module generates a multiplied voltage signal based on the clock signal and outputs the multiplied voltage signal to the voltage boosting module. The voltage boosting module generates a boosted voltage signal based on the clock signal and the multiplied voltage signal and outputs the boosted voltage signal to the voltage output module. The voltage output module generates an output signal based on the clock signal and the boosted voltage signal. Through the voltage multiplication of the signal by the voltage multiplier module and the voltage boosting of the signal by the voltage boosting module, the output signal has a larger voltage range, which is more than twice the voltage range of the clock signal. Due to the increased number of modules in the circuit, the number of adjustable parameters increases, thus making the adjustment range of the circuit output signal more flexible. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of an adjustable voltage charge pump circuit in one embodiment of this application. Figure 1 .

[0018] Figure 2 This is a signal timing diagram of the clock signal provided by the clock module in one embodiment of this application.

[0019] Figure 3 This is a voltage timing diagram of capacitors C5 and C6 in one embodiment of this application.

[0020] Figure 4 This is a circuit diagram of an adjustable voltage charge pump circuit in one embodiment of this application. Figure 2 .

[0021] Explanation of reference numerals in the attached figures:

[0022] 1. Voltage multiplier module; 11. First voltage multiplier charge pump unit; 12. Voltage multiplier auxiliary unit; 13. Second voltage multiplier charge pump unit; 14. Reverse unit; 3. Voltage boosting module; 4. Voltage output module. Detailed Implementation

[0023] This invention discloses a charge pump circuit with adjustable voltage.

[0024] In one embodiment, reference is made to Figure 1 The adjustable voltage charge pump circuit includes a clock module for providing a clock signal, as described in this embodiment, referencing... Figure 2 The clock module can provide two-phase non-overlapping clock signals, namely CLKP and CLKN, with a voltage range of 0 to AVDD. The circuit also includes a voltage multiplier module 1, a voltage booster module 3, and a voltage output module 4. All three modules are connected to the clock module. The voltage multiplier module 1 is connected to the voltage booster module 3. The voltage multiplier module 1 generates a multiplied voltage signal based on the clock signal and outputs the multiplied voltage signal to the voltage booster module 3. The voltage booster module 3 generates a boosted voltage signal based on the clock signal and the multiplied voltage signal and outputs the boosted voltage signal to the voltage output module 4. The voltage output module 4 generates an output signal based on the clock signal and the boosted voltage signal.

[0025] In this embodiment, refer to Figure 1 The voltage multiplier module 1 includes a first voltage multiplier charge pump unit 11 and a voltage multiplier auxiliary unit 12. The first voltage multiplier charge pump unit 11 includes two sets of multiplying charge pump units, specifically including capacitors C1, C2, C3, and C4, and NMOS transistors M1, M2, M3, and M4. One end of capacitors C1 and C4 is connected to the CLKP terminal of the clock module, and one end of capacitors C2 and C3 is connected to the CLKN terminal of the clock module. The other end of capacitor C1 is connected to the NMOS transistor. The source of transistor M1 and the gate of NMOS transistor M2 are connected. The other end of capacitor C2 is connected to the gate of NMOS transistor M1 and the source of NMOS transistor M2. The other end of capacitor C3 is connected to the source of NMOS transistor M3 and the gate of NMOS transistor M4. The other end of capacitor C4 is connected to the gate of NMOS transistor M3 and the source of NMOS transistor M4. The drain of NMOS transistor M1, the drain and gate of NMOS transistor M2, the drain of NMOS transistor M3, and the drain and gate of NMOS transistor M4 are all connected to voltage multiplier auxiliary unit 12.

[0026] In the first voltage doubler charge pump unit 11, when clock signals CLKP and CLKN pass through capacitors C1 and C2 respectively, capacitor C1 charges while capacitor C2 discharges, thus generating a positive voltage difference; when clock signals CLKP and CLKN pass through capacitors C3 and C4 respectively, capacitor C3 charges while capacitor C4 discharges, thus generating a negative voltage difference. Therefore, the first voltage doubler charge pump unit 11 can generate an initial voltage doubled signal of VB1 and output it to the voltage doubler auxiliary unit 12.

[0027] In this embodiment, refer to Figure 1 The voltage multiplier auxiliary unit 12 specifically includes capacitor C5, capacitor C6, NMOS transistors M5 and M6. The gate of NMOS transistor M5 is connected to the gate of NMOS transistor M4, and the gate of NMOS transistor M6 is connected to the gate of NMOS transistor M2. The drains of NMOS transistors M1, M2, M3, M4, M5, and M6 are connected in series. The source of NMOS transistor M5 is connected to one end of capacitor C5 and the voltage boosting module 3, and the source of NMOS transistor M6 is connected to one end of capacitor C6 and the voltage boosting module 3. The other end of capacitor C5 is connected to the CLKP terminal of the clock module, and the other end of capacitor C6 is connected to the CLKN terminal of the clock module and the voltage boosting module 3. (Refer to...) Figure 3 In the voltage multiplier auxiliary unit 12, the voltage of the upper plates of capacitors C5 and C6 can be charged to VB1 to AVDD+VB1 by the initial voltage multiplier signal and clock signal output by the first voltage multiplier charge pump unit 11.

[0028] In this embodiment, refer to Figure 1 The boost module 3 includes a PMOS transistor m1 and an NMOS transistor m2. The gate input of the PMOS transistor m1 has a first reference voltage, which is output by the voltage multiplier auxiliary unit 12 in this embodiment. The gate of the PMOS transistor m1 is connected to the source of the NMOS transistor M5, and the source of the PMOS transistor m1 is connected to the source of the NMOS transistor M6. One end of the capacitor C6 connected to the clock module is also connected to the source of the NMOS transistor m2. Therefore, the voltage range of the first reference voltage in this embodiment is VB1 to AVDD+VB1. The gate input of NMOS transistor m2 has a second reference voltage. In this embodiment, the second reference voltage is input through a power supply, and the input voltage is the maximum voltage of the signal output by the clock module. The drains of PMOS transistors M7 and M8 are connected to the source of PMOS transistor m1. The sources of NMOS transistors M4, M6, and M8 are connected to the source of NMOS transistor m2. The source of NMOS transistor m2 is also connected to one end of the clock module. The drains of PMOS transistors m1 and M2 are connected to the voltage output module 4.

[0029] Therefore, in this embodiment, when the CLKN signal in the clock module is high, the voltage of the upper plate of capacitor C5, i.e., the gate voltage of PMOS transistor m1, is AVDD+VB1, and the voltage of the upper plate of capacitor C6, i.e., the source voltage of PMOS transistor m1, is VB1. The voltage difference between the gate and source of PMOS transistor m1 is AVDD, which is greater than the threshold voltage of PMOS transistor m1. Therefore, PMOS transistor m1 is turned on. However, the voltage difference between the gate and source of NMOS transistor m2 is less than the threshold voltage of NMOS transistor m2. Therefore, NMOS transistor m2 is not turned on. At this time, the voltage of the upper plate of capacitor C6, AVDD+VB1, will be output as a boost signal to the voltage output module 4 through PMOS transistor m1.

[0030] Similarly, when the CLKN signal is low, the threshold voltage of PMOS transistor m1 is greater than the voltage difference between the gate and source of PMOS transistor m1, so PMOS transistor m1 is not turned on, but NMOS transistor m2 is turned on. Since the threshold voltage of NMOS transistor m2 is 0, the voltage difference in the circuit is canceled out, thereby making the voltage of the boost signal output to voltage output module 4 0. In addition, since PMOS transistor m1 is not turned on in this case, it will not affect the voltage in the circuit. Therefore, the voltage of the boost signal output to voltage output module 4 is 0 at this time. So in this embodiment, the voltage range of the boost signal output by boost module 3 is 0 to AVDD+VB1.

[0031] In this embodiment, refer to Figure 1 The voltage output module 4 includes capacitors C1 and C2, NMOS transistors M3 and M4. The drains of both PMOS transistors M1 and M2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to the source of NMOS transistor M3 and the gate of NMOS transistor M4. One end of capacitor C2 is connected to the CLKP terminal of the clock module. The other end of capacitor C2 is connected to the gate of NMOS transistor M3 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is used to output the output signal.

[0032] As described above, in this embodiment, the timing of the boost signal received by capacitor c1 is the same as the timing of the clock signal CLKN. Therefore, the boost signal received by capacitor c1 and the CLKP terminal at capacitor c2 form a two-phase non-overlapping clock. Thus, when the boost signal, i.e., the voltage of the lower plate of capacitor c1, is 0, the magnitude of the CLKP signal is AVDD, causing NMOS transistor m4 to not conduct and NMOS transistor m3 to conduct. Assuming the voltage between the drains of NMOS transistors m3 and m4 is VB, the voltage on capacitor c1 will charge to VB, and the voltage on the upper plate of capacitor c2 will become AVDD+VB. At this time, the output signal OUT at the gate of NMOS transistor m4 will remain at VB.

[0033] Similarly, when the boost signal, i.e., the voltage at the lower plate of capacitor c1, is AVDD + VB1, NMOS transistor m3 is not conducting, NMOS transistor m4 is conducting, the voltage at the upper plate of capacitor c1 is VB + VB1 + AVD, and the voltage at the upper plate of capacitor c2 becomes VB. At this time, the output signal OUT at the gate of NMOS transistor m4 will remain at VB + VB1 + AVD. Therefore, the voltage range of the output signal OUT is VB - VB + VB1 + AVDD, and the voltage range of the upper plate of capacitor c2 is VB - AVDD + VB. In the circuit structure of this embodiment, since VB and VB1 are both adjustable voltages, the final output voltage OUT can be changed within a fixed range from 0 to AVDD, resulting in a larger voltage range for the output signal. Furthermore, the increased number of adjustable parameters makes the adjustment range of the circuit output signal more flexible.

[0034] In another embodiment of the invention, reference is made to Figure 4 The voltage multiplier module 1 includes a second voltage multiplier charge pump unit 13 and an inverting unit. The second voltage multiplier charge pump unit 13 is connected to the inverting unit, and the inverting unit is connected to the boosting module 3. The second voltage multiplier charge pump unit 13 generates a voltage multiplier signal based on a clock signal. The inverting unit performs inversion processing on the voltage multiplier signal and outputs the inverted voltage multiplier signal to the boosting module 3.

[0035] In this embodiment, refer to Figure 4 The second voltage multiplier charge pump unit 13 is mainly a multiplier charge pump unit, specifically including capacitor C1, capacitor C2, PMOS transistor M1 and PMOS transistor M2. Capacitor C1 is connected to the CLKP terminal of the clock module, capacitor C2 is connected to the CLKN terminal of the clock module, the other end of capacitor C1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2, the other end of capacitor C2 is connected to the gate of PMOS transistor M1 and the drain of PMOS transistor M2, and the drain and source of PMOS transistor M2, as well as the source of PMOS transistor M1, are all connected to the inverting unit.

[0036] Reference Figure 4 In this embodiment, the inverting unit specifically includes PMOS transistors M3, M4, M5, M6, M7, and M8. The sources of PMOS transistors M1, M2, M3, M5, and M7 are connected in series. The drain of PMOS transistor M2 is connected to the gates of PMOS transistors M3 and M4. The drains of PMOS transistors M3 and M4 are connected to the gates of PMOS transistors M5 and M6. The drains of PMOS transistors M5 and M6 are connected to the gates of PMOS transistors M7 and M8. The drains of PMOS transistors M7 and M8, as well as the sources of NMOS transistors M4, M6, and M8, are all connected to the boost module 3.

[0037] In this embodiment, refer to Figure 4 The boost module 3 includes a PMOS transistor m1 and an NMOS transistor m2. The gate input of the PMOS transistor m1 has a first reference voltage VB1. The source of the PMOS transistor m1 is connected to the drain of the PMOS transistor M7 and the NMOS transistor M8. The sources of the NMOS transistors M4, M6 and M8 are all connected to the source of the NMOS transistor m2. The source of the NMOS transistor m2 is connected to the CLKP terminal of the clock module. The gate input of the NMOS transistor m2 has a second reference voltage. In this embodiment, the second reference voltage is input through the power supply. The input voltage is the maximum voltage of the signal output by the clock module. The drains of both the PMOS transistor m1 and the NMOS transistor m2 are connected to the voltage output module 4.

[0038] In this embodiment, refer to Figure 4 The voltage output module 4 includes capacitors C1 and C2, NMOS transistors M3 and M4. The drains of both PMOS transistors M1 and M2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to the source of NMOS transistor M3 and the gate of NMOS transistor M4. One end of capacitor C2 is connected to the CLKP terminal of the clock module. The other end of capacitor C2 is connected to the gate of NMOS transistor M3 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is used to output the output signal.

[0039] In this embodiment, it is assumed that the voltage between the drains of PMOS transistors M1 and M2 is VB0, and the voltage between the drains of NMOS transistors M3 and M4 is VB2. Since CLKN and CLKP are two-phase non-overlapping clocks, it can be deduced that the voltage range at the upper plate of capacitor C2 is 0 to VB0. The high and low levels in the inverting unit are VB0 and VB1, respectively. When the gate inputs of PMOS transistors M3 and M4 are 0, the voltage difference between the gate and source of PMOS transistor M3 is VB0, which is greater than the threshold voltage of PMOS transistor M3. Therefore, PMOS transistor M3 is turned on, while NMOS transistor M4 is turned off. At this time, the drain outputs of PMOS transistors M3 and M4 are VB0.

[0040] Similarly, when the gate inputs of PMOS transistor M3 and NMOS transistor M4 are VB0, PMOS transistor M3 is off, and the voltage difference between the gate and source of NMOS transistor M4 is |VB0-VB1|, which is greater than the threshold voltage of NMOS transistor M4. Therefore, NMOS transistor M4 is on, and the drain outputs of PMOS transistors M3 and M4 are VB1. By analogy, the voltage range of the source of PMOS transistor M1 is VB1 to VB0. Further derivation shows that the voltage range of the lower plate of capacitor C1 is 0 to VB0, and finally, the output voltage range of the gate of NMOS transistor M4 is VB2-VB1+VB0. Compared to the traditional multiplier charge pump circuit, the output signal of the circuit in this embodiment has a larger voltage range and more adjustable parameters, making the adjustment range of the circuit output signal more flexible. Compared to the charge pump circuit in the first embodiment, the output voltage adjustment range of the charge pump circuit in this embodiment is finer; the voltage can be finely adjusted within 1 times AVDD, but VB0 must be greater than VB1 when setting the voltage.

[0041] The present invention also discloses an apparatus comprising: Figure 1 or Figure 4 The adjustable voltage charge pump circuit shown includes a voltage multiplier module 1, a voltage booster module 3, and a voltage output module 4. All three modules are connected to a clock module. Voltage multiplier module 1 is connected to voltage booster module 3. Voltage multiplier module 1 generates a voltage multiplier signal based on the clock signal and outputs it to voltage booster module 3. Voltage booster module 3 generates a boosted signal based on the clock signal and the voltage multiplier signal and outputs it to voltage output module 4. Voltage output module 4 generates an output signal based on the clock signal and the boosted signal. Through the voltage multiplication of the signal by voltage multiplier module 1 and the voltage boosting of the signal by voltage booster module 3, the output signal has a wider voltage range, exceeding twice the voltage range of the clock signal. Due to the increased number of modules and adjustable parameters, the adjustment range of the circuit's output signal is more flexible.

[0042] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0043] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A charge pump circuit with adjustable voltage, the circuit including a clock module for providing a clock signal, characterized in that, The circuit further includes a voltage multiplier module, a voltage boosting module, and a voltage output module. The voltage multiplier module, the voltage boosting module, and the voltage output module are all connected to the clock module. The voltage multiplier module is connected to the voltage boosting module. The voltage multiplier module generates a voltage multiplier signal based on the clock signal and outputs the voltage multiplier signal to the voltage boosting module. The voltage boosting module generates a boosted signal based on the clock signal and the voltage multiplier signal and outputs the boosted signal to the voltage output module. The voltage output module generates an output signal based on the clock signal and the boosted signal. The voltage range of the output signal is greater than twice the voltage range of the clock signal. The voltage multiplier module includes a second voltage multiplier charge pump unit and an inverting unit. The second voltage multiplier charge pump unit is connected to the inverting unit, and the inverting unit is connected to the boosting module. The second voltage multiplier charge pump unit generates the voltage multiplier signal based on the clock signal. The inverting unit inverts the voltage multiplier signal and outputs the inverted voltage multiplier signal to the boosting module. The second voltage doubler charge pump unit includes capacitor C1, capacitor C2, PMOS transistor M1, and PMOS transistor M2. Capacitor C1 is connected to one end of the clock module, capacitor C2 is connected to the other end of the clock module, the other end of capacitor C1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2, the other end of capacitor C2 is connected to the gate of PMOS transistor M1 and the drain of PMOS transistor M2, and the drain and source of PMOS transistor M2, as well as the source of PMOS transistor M1, are all connected to the inverting unit. The inverting unit includes PMOS transistors M3, M4, M5, M6, M7, and M8. The sources of PMOS transistors M1, M2, M3, M5, and M7 are connected in series. The drain of PMOS transistor M2 is connected to the gates of PMOS transistors M3 and M4. The drains of PMOS transistors M3 and M4 are connected to the gates of PMOS transistors M5 and M6. The drains of PMOS transistors M5 and M6 are connected to the gates of PMOS transistors M7 and M8. The drains of PMOS transistors M7 and M8, and the sources of NMOS transistors M4, M6, and M8 are all connected to the boost module. The boost module includes a PMOS transistor m1 and an NMOS transistor m2. The gate of the PMOS transistor m1 is connected to a first reference voltage, and the gate of the NMOS transistor m2 is connected to a second reference voltage. The drains of the PMOS transistor M7 and the NMOS transistor M8 are both connected to the source of the PMOS transistor m1. The sources of the NMOS transistors M4, M6, and M8 are all connected to the source of the NMOS transistor m2. The source of the NMOS transistor m2 is also connected to one end of the clock module. The drains of the PMOS transistor m1 and the NMOS transistor m2 are both connected to the voltage output module. The voltage output module includes capacitors C1 and C2, NMOS transistors M3 and M4. The drains of both PMOS transistors M1 and M2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to the source of NMOS transistor M3 and the gate of NMOS transistor M4. One end of capacitor C2 is connected to one end of the clock module. The other end of capacitor C2 is connected to the gate of NMOS transistor M3 and the source of NMOS transistor M4. The drain of NMOS transistor M3 is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is used to output the output signal.

2. A device, characterized in that, The device includes an adjustable voltage charge pump circuit as described in claim 1.

Images