Electronic device with stacked structure duplexer

Abstract

Electronic devices according to various embodiments may include: an antenna; a wireless communication circuit; and a duplexer connected to the antenna and the wireless communication circuit. The duplexer may include: a first port connected to the antenna; a second port connected to the wireless communication circuit; a third port connected to the wireless communication circuit; a low-pass filter (LPF) configured to filter low-frequency RF signals from a signal received from one of the first and second ports and output it to the other of the first and second ports; and a high-pass filter (HPF) configured to filter high-frequency RF signals from a signal received from one of the first and third ports and output it to the other of the first and third ports. The LPF may include a capacitor disposed on the surface of a printed circuit board (PCB) and an inductor patterned on the PCB. The HPF may include an inductor disposed on the surface of the PCB and a capacitor patterned on the PCB; various other embodiments are also possible.

Description

Technical Field

[0001] Various embodiments relate to an electronic device configured to transmit and receive RF signals in multiple frequency bands via a single antenna using a duplexer. Background Technology

[0002] A duplexer can be configured to separate an RF signal received from an antenna into an RF signal in a first frequency band and an RF signal in a second frequency band, and output the RF signal to a wireless communication circuit (e.g., a transceiver) via different signal paths, and can also be configured to output the RF signal received from the wireless communication circuit to the antenna. Summary of the Invention

[0003] Technical issues

[0004] A duplexer can be mounted on one side of a board. For example, an externally mounted component (e.g., a lumped component) can be mounted on the PCB surface using surface mount technology. Since the duplexer is implemented as an externally mounted component, material costs can increase. Because the duplexer is mounted on one side of the board, it occupies a portion of the internal space of the electronic device. Therefore, it may be difficult to secure internal space in the electronic device (e.g., a smartphone) where component elements will be housed. When the duplexer is mounted on one side of a board included in the electronic device, it may be damaged or detached from the board when subjected to external impacts or during assembly.

[0005] According to various embodiments, an electronic device can be provided that reduces the internal space used for a duplexer and includes a duplexer implemented at a relatively low material cost. The technical subject matter of this disclosure is not limited to the above-described technical subject matter, and other technical subject matter not mentioned will be understood by those skilled in the art based on the following description.

[0006] Technical solution

[0007] An electronic device according to various embodiments may include an antenna, a wireless communication circuit, and a duplexer connected to the antenna and the wireless communication circuit. The duplexer may include a first port connected to the antenna; a second port connected to the wireless communication circuit; a third port connected to the wireless communication circuit; a low-pass filter (LPF) configured to filter a signal received from one of the first and second ports to obtain a low-frequency RF signal and output it to another port between the first and second ports; and a high-pass filter (HPF) configured to filter a signal received from one of the first and third ports to obtain a high-frequency RF signal and output the RF signal to another port between the first and third ports. The LPF may include a capacitor disposed on the surface of a printed circuit board (PCB) and an inductor formed in a pattern on the PCB. The HPF may include an inductor disposed on the surface of the PCB and a capacitor formed in a pattern on the PCB.

[0008] Beneficial effects

[0009] According to various embodiments, a low-cost and easily handled duplexer can be provided in electronic devices. Electronic devices can transmit or receive RF signals in multiple frequency bands via a single antenna using such a duplexer. Furthermore, various effects directly or indirectly acknowledged in the document can be provided. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an electronic device in a network environment according to various embodiments;

[0011] Figure 2 This is a block diagram of an electronic device configured to transmit and receive RF signals in multiple frequency bands via a single antenna, according to an embodiment.

[0012] Figure 3a yes Figure 2 The circuit diagram of the LPF. Figure 3b and Figure 3c This is a diagram illustrating the layer structure of an LPF according to various embodiments, and Figure 3d This is a graph illustrating the filtering performance of the LPF;

[0013] Figure 4a yes Figure 2 The circuit diagram of the HPF, Figure 4b and Figure 4c This is a diagram illustrating the layer structure of the HPF according to various embodiments, and Figure 4d This is a graph illustrating the filtering performance of the HPF;

[0014] Figure 5a This is a diagram showing the surface of the PCB including the duplexer. Figure 5b This is a diagram showing the layer structure of a duplexer in a PCB, and Figure 5c This is a diagram illustrating the grounding layer structure in a PCB according to an embodiment;

[0015] Figure 6a This is a cross-sectional view of a PCB including a duplexer. Figure 6b This is a diagram illustrating the layer structure of a duplexer in a PCB according to an embodiment. Detailed Implementation

[0016] Figure 1 This is a block diagram illustrating an electronic device 101 in a network environment 100 according to various embodiments. (Refer to...) Figure 1 In network environment 100, electronic device 101 can communicate with electronic device 102 via a first network 198 (e.g., a short-range wireless communication network), or with at least one of electronic device 104 or server 108 via a second network 199 (e.g., a long-range wireless communication network). According to one embodiment, electronic device 101 can communicate with electronic device 104 via server 108. According to embodiments, electronic device 101 may include a processor 120, memory 130, input module 150, sound output module 155, display module 160, audio module 170, sensor module 176, interface 177, connection terminal 178, haptic module 179, camera module 180, power management module 188, battery 189, communication module 190, user identification module (SIM) 196, or antenna module 197. In some embodiments, at least one component (e.g., connection terminal 178) may be omitted from electronic device 101, or one or more other components may be added to electronic device 101. In some embodiments, some components (e.g., sensor module 176, camera module 180, or antenna module 197) may be implemented as a single component (e.g., display module 160).

[0017] Processor 120 is capable of executing, for example, software (e.g., program 140) to control at least one other component (e.g., hardware or software component) of electronic device 101 coupled to processor 120, and is capable of performing various data processing or calculations. According to one embodiment, as at least part of data processing or calculation, processor 120 may store commands or data received from another component (e.g., sensor module 176 or communication module 190) in volatile memory 132, process the commands or data stored in volatile memory 132, and store the resulting data in non-volatile memory 134. According to one embodiment, processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or application processor (AP)) or an auxiliary processor 123 (e.g., a graphics processing unit (GPU), neural processing unit (NPU), image signal processor (ISP), sensor hub processor, or communication processor (CP)), which may operate independently or in conjunction with main processor 121. For example, when electronic device 101 includes a main processor 121 and an auxiliary processor 123, the auxiliary processor 123 can be tuned to consume less power than the main processor 121, or dedicated to a specific function. The auxiliary processor 123 can be implemented separately from the main processor 121, or as part of the main processor 121.

[0018] The auxiliary processor 123 can control at least some of the functions or states associated with at least one component of the electronic device 101 (e.g., display module 160, sensor module 176, or communication module 190), rather than the main processor 121 when it is inactive (e.g., in sleep) or active (e.g., executing an application). According to embodiments, the auxiliary processor 123 (e.g., an image signal processor or a communication processor) can be implemented as part of another component (e.g., camera module 180 or communication module 190) functionally associated with the auxiliary processor 123. According to one embodiment, the auxiliary processor 123 (e.g., a neural processing unit) can include hardware structures specified for processing artificial intelligence models. The artificial intelligence model can be generated through machine learning. This learning can be performed, for example, by the electronic device 101 performing artificial intelligence or via a separate server (e.g., server 108). The learning algorithm can include, but is not limited to, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The artificial intelligence model can include multiple layers of artificial neural networks. Artificial neural networks can be deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more thereof, but are not limited to these. Artificial intelligence models may additionally or alternatively include software structures in addition to hardware structures.

[0019] Memory 130 may store various data used by at least one component of electronic device 101 (e.g., processor 120 or sensor module 176). The various data may include, for example, software (e.g., program 140) and input or output data for commands associated therewith. Memory 130 may include volatile memory 132 or non-volatile memory 134.

[0020] Program 140 may be stored as software in memory 130 and may include, for example, an operating system (OS) 142, middleware 144, or application 146.

[0021] Input module 150 can receive commands or data from outside electronic device 101 (e.g., a user) to be used by another component of electronic device 101 (e.g., processor 120). Input module 150 may include, for example, a microphone, mouse, keyboard, keys (e.g., buttons), or digital pen (e.g., pointer pen).

[0022] The audio output module 155 can output audio signals to the outside of the electronic device 101. The audio output module 155 may include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or playing recordings. The receiver can be used to receive incoming calls. According to one embodiment, the receiver can be implemented independently of the speaker or as part of the speaker.

[0023] Display module 160 can visually provide information to the outside of electronic device 101 (e.g., to a user). Display module 160 may include, for example, a display, a holographic device, or a projector, and control circuitry for controlling a corresponding one of the display, holographic device, and projector. According to one embodiment, display module 160 may include a touch sensor adapted to detect touch, or a pressure sensor adapted to measure the intensity of the force caused by a touch.

[0024] Audio module 170 can convert sound into electrical signals and vice versa. According to an embodiment, audio module 170 can obtain sound via input module 150, or output sound via sound output module 155 or headphones of an external electronic device (e.g., electronic device 102) directly (e.g., wired) or wirelessly coupled to electronic device 101.

[0025] Sensor module 176 can detect the operating state of electronic device 101 (e.g., power or temperature) or the environmental state outside electronic device 101 (e.g., user state), and then generate an electrical signal or data value corresponding to the detected state. According to one embodiment, sensor module 176 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0026] Interface 177 may support one or more specified protocols for directly (e.g., wired) or wirelessly coupling electronic device 101 to external electronic device (e.g., electronic device 102). According to embodiments, interface 177 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) interface, or an audio interface.

[0027] Connection terminal 178 may include a connector through which electronic device 101 can be physically connected to an external electronic device (e.g., electronic device 102). According to one embodiment, connection terminal 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0028] The tactile module 179 can convert electrical signals into mechanical stimuli (e.g., vibration or motion) or electrical stimuli, which can be recognized by a user through his touch or kinesthesia. According to one embodiment, the tactile module 179 may include, for example, an electric motor, a piezoelectric element, or an electrical stimulator.

[0029] Camera module 180 can capture still or moving images. According to one embodiment, camera module 180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0030] The power management module 188 can manage the power supplied to the electronic device 101. According to one embodiment, the power management module 188 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0031] Battery 189 can supply power to at least one component of electronic device 101. According to one embodiment, battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0032] Communication module 190 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 101 and external electronic devices (e.g., electronic device 102, electronic device 104, or server 108), and perform communication via the established communication channel. Communication module 190 may include one or more communication processors that can operate independently of processor 120 (e.g., application processor (AP)) and support direct (e.g., wired) or wireless communication. According to embodiments, communication module 190 may include wireless communication module 192 (e.g., cellular communication module, short-range wireless communication module, or Global Navigation Satellite System (GNSS) communication module) or wired communication module 194 (e.g., local area network (LAN) communication module or power line communication (PLC) module). A corresponding one of these communication modules can communicate via a first network 198 (e.g., a short-range communication network, such as Bluetooth). TM The communication module 192 can communicate with external electronic devices via a second network 199 (e.g., a long-range communication network, such as a traditional cellular network, a 5G network, or a next-generation communication network, such as the Internet or a computer network, such as a LAN or a wide area network (WAN)). These various types of communication modules can be implemented as a single component (e.g., a single chip) or as multiple components that are separate from each other (e.g., multiple chips). The wireless communication module 192 can use subscriber information (e.g., International Mobile Subscriber Identity (IMSI)) stored in the subscriber identification module 196 to identify and authenticate electronic devices 101 in the communication network (e.g., a first network 198 or a second network 199).

[0033] Following 4G networks, wireless communication module 192 can support 5G networks and next-generation communication technologies, such as new radio (NR) access technologies. NR access technologies can support enhanced mobile broadband (eMBB), massive machine-type communications (mMTC), or ultra-reliable low latency communications (URLLC). Wireless communication module 192 can support high-frequency bands (e.g., millimeter-wave bands) to achieve, for example, high data transmission rates. Wireless communication module 192 can support various technologies used to ensure performance in high-frequency bands, such as beamforming, massive MIMO, full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, or massive MIMO. Wireless communication module 192 can support various requirements specified in electronic device 101, external electronic devices (e.g., electronic device 104), or network systems (e.g., second network 199). According to one embodiment, the wireless communication module 192 may support peak data rates (e.g., 20 Gbps or higher) for implementing eMBB, lost coverage (e.g., 164 dB or lower) for implementing mMTC, or U-plane latency (e.g., 0.5 ms or lower for each of the downlink (DL) and uplink (UL), or 1 ms or lower round trip) for implementing URLLC.

[0034] Antenna module 197 can transmit signals or power to or from the outside of electronic device 101 (e.g., external electronic device). According to one embodiment, antenna module 197 may include an antenna comprising a radiating element made of conductive material or conductive patterns formed in or on a substrate (e.g., a printed circuit board (PCB)). According to one embodiment, antenna module 197 may include multiple antennas (e.g., an array antenna). In this case, for example, at least one antenna suitable for a communication scheme used in a communication network (e.g., a first network 198 or a second network 199) can be selected from the multiple antennas by communication module 190 (e.g., wireless communication module 192). Signals or power can then be transmitted or received between communication module 190 and the external electronic device via the selected at least one antenna. According to one embodiment, another component besides the radiating element (e.g., a radio frequency integrated circuit (RFIC)) may be additionally incorporated into antenna module 197.

[0035] According to various embodiments, antenna module 197 can form a millimeter-wave antenna module. According to one embodiment, the millimeter-wave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., the bottom surface) of the printed circuit board and capable of supporting a specified high-frequency band (e.g., millimeter-wave band), and a plurality of antennas (e.g., an array antenna) disposed on a second surface (e.g., the top or side surface of the printed circuit board, or adjacent to the second surface), and capable of transmitting or receiving signals of the specified high-frequency band.

[0036] At least some of the aforementioned components may be coupled to each other and transmit signals (e.g., commands or data) between them via a peripheral communication scheme (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI) or mobile industrial processor interface (MIPI)).

[0037] According to one embodiment, commands or data can be sent or received between electronic device 101 and external electronic device 104 via server 108 coupled to a second network 199. Each of electronic devices 102 or 104 can be a device of the same or different type as electronic device 101. According to one embodiment, all or some of the operations to be performed on electronic device 101 can be performed at one or more external electronic devices 102, 104, or 108. For example, if electronic device 101 is required to automatically perform a function or service, or in response to a request from a user or another device, electronic device 101 may request one or more external electronic devices to perform at least a portion of a function or service, rather than performing a function or service, or may request one or more external electronic devices to perform at least a portion of a function or service in addition to performing a function or service. The one or more external electronic devices receiving the request may perform at least a portion of the function or the requested service, or additional functions or services associated with the request, and transmit the result of the performance to electronic device 101. Electronic device 101 may provide the result, with or without further processing of the result, as at least part of a response to the request. For this purpose, technologies such as cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing can be used. Electronic device 101 can use, for example, distributed computing or mobile edge computing to provide ultra-low latency services. In another embodiment, external electronic device 104 may include Internet of Things (IoT) devices. Server 108 may be an intelligent server using machine learning and / or neural networks. According to one embodiment, external electronic device 104 or server 108 may be included in a second network 199. Electronic device 101 can be applied to intelligent services based on 5G communication technology or IoT-related technologies (e.g., smart homes, smart cities, smart cars, or healthcare).

[0038] The electronic device according to various embodiments can be one of a variety of types of electronic devices. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer equipment, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. According to embodiments of this disclosure, the electronic device is not limited to those described above.

[0039] It should be understood that the various embodiments of this disclosure and the terminology used therein are not intended to limit the technical features described herein to specific embodiments, and include various changes, equivalents, or substitutions to the corresponding embodiments. Regarding the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that, unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to an item may include one or more things. As used herein, each of phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may include any or all possible combinations of the items listed together in the corresponding phrase. As used herein, terms such as “first” and “second,” or “first” and “second,” may be used simply to distinguish one component from another and do not limit the components in other respects (e.g., importance or order). It should be understood that if an element (e.g., the first element) is referred to as “coupled to another element (e.g., the second element),” “coupled to another element,” “connected to another element,” or “connected to another element,” regardless of whether the terms “operationally” or “communicatively” are used, it means that the element can be coupled to another element directly (e.g., wired), wirelessly, or through a third element.

[0040] As used in conjunction with various embodiments of the invention, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., "logic," "logic block," "part," or "circuit"). A module may be a single integral component adapted to perform one or more functions, or its smallest unit or portion thereof. For example, according to one embodiment, a module may be implemented as an application-specific integrated circuit (ASIC).

[0041] The various embodiments described herein can be implemented as software (e.g., program 140) comprising one or more instructions stored in a machine-readable storage medium (e.g., internal memory 136 or external memory 138). For example, a processor (e.g., processor 120) of the machine (e.g., electronic device 101) can invoke at least one of the one or more instructions stored in the storage medium and execute it with or without one or more other components under the control of the processor. This allows the machine to be operated to perform at least one function according to the invoked at least one instruction. The one or more instructions may include code generated by a compiler or code executed by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" means only that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but the term does not distinguish between locations where data is stored semi-permanently and locations where data is temporarily stored in the storage medium.

[0042] According to one embodiment, methods according to various embodiments of this disclosure can be included and provided in a computer program product. The computer program product can be traded as a product between a seller and a buyer. The computer program product can be distributed in the form of a machine-readable storage medium (e.g., an optical disc read-only memory (CD-ROM)) or via application storage (e.g., the Play Store). TM The computer program product may be distributed online (e.g., downloaded or uploaded) or directly between two user devices (e.g., smartphones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium, such as the memory of a manufacturer's server, an application storage server, or a relay server.

[0043] According to various embodiments, each component (e.g., a module or program) of the above-described components may include a single entity or multiple entities, and some of the multiple entities may be arranged separately in different components. According to various embodiments, one or more of the above-described components may be omitted, or one or more other components may be added. Optionally or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, according to various embodiments, the integrated component may still perform one or more functions of each of the multiple components in the same or similar manner as the multiple components performed by the corresponding one of the multiple components before integration. According to various embodiments, operations performed by a module, program, or other component may be performed sequentially, in parallel, repeatedly, or tentatively, or one or more operations may be performed in a different order or omitted, or one or more other operations may be added.

[0044] Figure 2 This is a block diagram of an electronic device 200 configured to transmit and receive RF signals in multiple frequency bands via a single antenna, according to an embodiment. (See also...) Figure 2 Electronic device 200 (e.g., Figure 1 The electronic device 101 may include an antenna 210, a duplexer 220, a first duplexer 230, a second duplexer 240, a first switching circuit 250, a second switching circuit 260 and / or a transceiver 270.

[0045] According to one embodiment, duplexer 220 may include a low-pass filter (LPF) 220a and a high-pass filter (HPF) 220b. For example, LPF 220a may filter the input RF signal to extract and output an RF signal with a low frequency band (e.g., approximately 3 GHz or lower). HPF 220b may filter the input RF signal to extract and output an RF signal with a high frequency band (e.g., approximately 3 GHz or higher). Duplexer 220 may include a first port 221 connected to antenna 210, a second port 222 connected to first coupler 291, and a third port 223 connected to second coupler 292. LPF 220a may be configured to filter a signal received via one of the first port 221 and the second port 222 to extract the low-frequency RF signal and output it to the other port between the first port 221 and the second port 222. The HPF 220b can be configured to filter a signal received via one of the first port 221 and the third port 223 to extract an RF signal with a high frequency band and output it to another port between the first port 221 and the third port 223.

[0046] According to one embodiment, the first duplexer 230 may include: a (1-1) bandpass filter (BPF) 230a, which is configured to direct the signal to a network (e.g., Figure 1The first network 198 outputs an RF signal designated for a first transmission frequency band for data transmission; the (1-2) BPF 230b is configured to output an RF signal designated for a first reception frequency band for data reception from the network. A (1-1) port 231 connected to the (1-1) BPF 230a and (1-2) BPF 230b and connected to the first switching circuit 250, a (1-2) port 232 connected to the first transmission port 271a of the transceiver 270 via a power amplifier 280, and a (1-3) port 233 connected to the first reception port 272a of the transceiver 270. The (1-1) BPF 230a can be configured to filter the signal received from the first transmission port 271a of the transceiver 270 via the (1-2) port 232 to extract the RF signal having the first transmission frequency band, and can output it to the (1-1) port 231. The (1-2) BPF 230b can be configured to filter the signal received via the (1-1) port 231 to extract the RF signal having a first receive frequency band, and output it via the (1-3) port 233 to the first receive port 272a of the transceiver 270.

[0047] According to one embodiment, the second duplexer 240 may include: a (2-1) BPF 240a, which is configured to transmit data to a network (e.g., Figure 1 The first network 198 outputs an RF signal in a second transmission band designated for data transmission; the (2-2) BPF 240b is configured to output an RF signal in a second reception band designated for data reception from the network. A (2-1) port 241 is connected to the (2-1) BPF 240a and (2-2) BPF 240b and to the second switching circuit 260, a (2-2) port 242 is connected to the second transmission port 271b of the transceiver 270 via a power amplifier 280, and a (2-3) port 243 is connected to the second reception port 272b of the transceiver 270. The (2-1) BPF 240a can be configured to filter the signal received from the second transmission port 271b of the transceiver 270 via the (2-2) port 242 to extract the RF signal with the second transmission band, and can output it to the (2-1) port 241. The (2-2) BPF 240b can be configured to filter the signal received via the (2-1) port 241 to extract the RF signal with the second receive frequency band, and output it via the (2-3) port 243 to the second receive port 272b of the transceiver 270.

[0048] According to various embodiments, the transmission band may include a band specified for 5G or legacy networks defined by 3GPP (e.g., Figure 1The uplink band is one of the frequency bands in the frequency division duplex (FDD) communication scheme of the second network 199. The receiving band may include the downlink band in the frequency band. The uplink band may be lower or higher than the downlink band. For example, a traditional network may include a second-generation (2G), 3G, 4G, or Long Term Evolution (LTE) network. According to various embodiments, BPF 230a, 230b, 240a, and 240b may include surface acoustic wave (SAW) filters.

[0049] According to various embodiments, a first switching circuit (or front-end circuit) 250 may be disposed in the transmission line connecting the second port 222 of the duplexer 220 and the (1-1) port 231 of the first duplexer 230. The first switching circuit 250 may output to the first duplexer 230 the RF signal received from the antenna 210 via the duplexer 220. The first switching circuit 250 may also output to the duplexer 220 the RF signal received from the transceiver 270 via the first duplexer 230.

[0050] According to various embodiments, the second switching circuit 260 can be disposed in the transmission line connecting the third port 223 of the duplexer 220 and the (2-1) port 241 of the second duplexer 240. The second switching circuit 260 can preprocess the RF signal received from the antenna 210 via the duplexer 220 and can output the RF signal to the transceiver 270 via the second duplexer 240. The second switching circuit 260 can preprocess the RF signal received from the transceiver 270 via the second duplexer 240 and can output the RF signal to the antenna 210 via the duplexer 220.

[0051] According to various embodiments, the electronic device 200 may also include a first amplifier circuit and / or a second amplifier circuit. For example, the first amplifier circuit (e.g., a low-noise amplifier or a variable gain amplifier) ​​may amplify the RF signal received from the antenna 210 via the (1-2) BPF 230b and may output it to the transceiver 270 via the first receive port 272a. The second amplifier circuit (e.g., a low-noise amplifier or a variable gain amplifier) ​​may amplify the RF signal received from the antenna 210 via the (2-2) BPF 240b and may output it to the transceiver 270 via the second receive port 272b.

[0052] According to various embodiments, transceiver 270 may be an element included in wireless communication module 192 (e.g., wireless communication circuitry supporting communication with a cellular network). In transmission mode, transceiver 270 can convert baseband signals received from the processor into RF signals and output them to antenna 210 via a first transmission port 271a or a second transmission port 271b. In reception mode, transceiver 270 can convert RF signals received from antenna 210 via a first reception port 272a or a second reception port 272b into baseband signals and output them to the processor.

[0053] According to various embodiments, the electronic device 200 may further include a power amplifier 280, a first coupler 291, and / or a second coupler 292. The power amplifier 280 may amplify the power of an RF signal received from a first transmission port 271a of the transceiver 270 and output the RF signal to a (1-2) port 232 of a first duplexer 230. The power amplifier 280 may amplify the power of an RF signal received from a second transmission port 271b of the transceiver 270 and output it to a (2-2) port 242 of a second duplexer 240. The first coupler 291 may be disposed in the transmission line connecting the second port 222 of the duplexer 220 and the first switching circuit 250, and may obtain the power of the RF signal output from the transceiver 270 to the antenna 210 and output it back to the transceiver 270. The second coupler 292 can be placed in the transmission line connecting the third port 223 of the duplexer 220 and the second switching circuit 260, and can obtain the power of the RF signal output from the transceiver 270 to the antenna 210, and can output it to the transceiver 270.

[0054] Figure 3a yes Figure 2 The circuit diagram of LPF 220a, Figure 3b and Figure 3c This is a diagram illustrating the layer structure of LPF 220a according to various embodiments, and Figure 3d This is a graph illustrating the filtering performance of the LPF 220a.

[0055] refer to Figure 3a The LPF 220a may include a first capacitor (LPF capacitor (LC) 1) 311, a second capacitor (LC2) 312, a third capacitor (LC3) 313, a first inductor (LPF inductor (LL) 1) 321 and / or a second inductor (LL2) 322.

[0056] According to various embodiments, one end (A) of LL1 321 can be connected to a first port 221, and the other end (B) of LL1 321 can be connected to one end (C) of LL2 322. The other end (D) of LL2 322 can be connected to a second port 222. One end (Q) of LC1311 can be connected to one end (A) of LL1 321, and the other end (R) of LC1 311 can be connected to the other end (B) of LL1321. One end (E) of LC2 312 can be connected to one end (C) of LL2 322, and the other end (F) of LC2 312 can be connected to the other end (D) of LL2 322. One end (G) of LC3313 can be connected between the other end (B) of LL1 321 and the other end (C) of LL2 322. The other end (H) of LC3 313 can be connected to ground formed on the PCB. According to one embodiment, LC1 311 is implemented as a parasitic capacitance between the two ends of LL1 321, and... Figure 3a It can be omitted in the circuit configuration.

[0057] exist Figure 3a In the circuit configuration shown, the combination of LL1 321, LL2 322 and LC3 313 can function as a filter that allows low-frequency RF signals to pass through, and the combination of LL1 321 and LC1 311 and the combination of LL2 322 and LC2 322 can function as a filter that blocks high-frequency RF signals from passing through.

[0058] According to various embodiments, LL1 321 and LL2 322 can be patterned (e.g., embedded) on a PCB, and LC2 312 and LC3 313 can be lumped elements disposed on the PCB surface. Reference Figure 3b and Figure 3c The PCB may include a first layer 391, a second layer 392, and a third layer 393.

[0059] According to various embodiments, the first layer 391 may include a PCB surface on which lumped components are disposed. For example, a (1-1) pad 312a, a (1-2) pad 312b, a (2-1) pad 313a, and / or a (2-2) pad 313b may be formed in the first layer 391. One end (E) of LC2 312 is connected to the (1-1) pad 312a, and the other end (F) of LC2 312 may be connected to the (1-2) pad 312b, which is separate from the (1-1) pad 312b. The (1-2) pad 312b may be connected to a second port 222. For example, although not shown, a first contact point 381 extending from the (1-2) pad 312b may be connected to the second port 222. The first contact point 381 may, for example, be the other end (D) of LL2 322. Pad 313a (2-1) can be connected to pad 312a (1-1), and one end (G) of LC3 313 can be connected to pad 313a (2-1). Pad 313b (2-2), which is separate from pad 313a (2-1), can be connected to ground, and the other end (H) of LC3 313 can be connected to pad 313b (2-2) and can also be connected to ground. According to one embodiment, pad 312a (1-1), pad 312b (1-2), pad 313a (2-1), and / or pad 313b (2-2) can be provided in the form of conductive patches.

[0060] According to various embodiments, the first portion 321a of LL1 321 and the first portion 322a of LL2 322 can be formed in the second layer 392. One end 321a_1 of the first portion 321a of LL1 321 can be connected to the (1-1) pad 312a using a first through-hole 371. For example, one end 321a_1 of the first portion 321a of LL1 321 can be the other end (B) of LL1 321. The first portion 322a of LL2 322 can be configured to be spaced apart from the first portion 321a of LL1 321, and one end 322a_1 of the first portion 322a of LL2 322 can be connected to the (1-2) pad 312b using a second through-hole 372. One end 321a_1 of the first portion 322a of LL2 322 can be, for example, the other end (D) of LL2 322.

[0061] According to various embodiments, the first portion 321a of LL1 321 may include a wire in the form of a coil extending from one end 321a_2 of the first portion 321a of LL1 321 to one end 321a_1 of the first portion 321a of LL1 321. According to another embodiment, the first portion 322a of LL2 322 may extend from one end 322a_1 of the first portion 322a of LL2 322 to the other end 322a_2 of the first portion 322a of LL1 322, and may be provided in the form of a wire with a curve.

[0062] According to various embodiments, the second portion 321b of LL1 321 and the second portion 322b of LL2 322 can be formed in the third layer 393. One end 321b_1 of the second portion 321b of LL1 321 can be connected to the other end 321a_2 of the first portion 321a of LL1 321 using a third through-hole 373. The other end 321b_2 of the second portion 321b of LL1 321 can be connected to the first port 221. The other end 321b_2 of the second portion 321b of LL1 321 can be, for example, one end (A) of LL1 321. One end 322b_1 of the second portion 322b of LL2 322 can be connected to one end 321a_1 of the first portion 321a of LL1 321 using a fourth through-hole 374. The other end 322b_2 of the second part 322b of LL2 322 can be connected to one end 322a_2 of the first part 322a of LL2 322 using the fifth through hole 375.

[0063] According to various embodiments, the second portion 321b of LL1 321 may extend from one end 321b_1 of the second portion 321b of LL1 321 to the other end 321b_2 of the second portion 321b of LL1 321, and may be provided in the form of a curved conductor. As another example, the second portion 322b of LL2 322 may extend from one end 322b_1 of the second portion 322b of LL2 322 to the other end 322b_2 of the second portion 322b of LL2 322, and may be provided in the form of a curved conductor.

[0064] According to various embodiments, when viewed in the z-axis direction, at least a portion of the first part 321a of LL1 321, the second part 321b of LL1 321, and the (2-1) pad 313a may overlap. As another example, when viewed in the z-axis direction, at least a portion of the first part 322a of LL2 322, the second part 322b of LL2 322, and the (1-2) pad 312b may overlap.

[0065] refer to Figure 3dWhen an RF signal is input to one of the first port 221 and the second port 222, for example, an RF signal of approximately 3 GHz or lower (e.g., a Long Term Evolution (LTE) band) can be output to the other port via LPF 220a without any loss. RF signals of approximately 3 GHz or higher (e.g., new radio (NR) bands 77 (n77), n79, n79) may substantially bypass LPF 220a. For example, the cutoff frequency of LPF 220a may be 3 GHz, and the cutoff band may be approximately 3 GHz or higher. According to one embodiment, the cutoff frequency can be changed when the capacitance of the capacitors (e.g., LC1 311, LC2 312, LC3 313) and / or the inductance of the inductors (e.g., LL1 321, LL2 322) is changed.

[0066] Figure 4a yes Figure 2 The circuit diagram of HPF 220b. Figure 4b and Figure 4c This is a diagram illustrating the layer structure of HPF 220b according to various embodiments. Figure 4d This is a graph showing the filtering performance of the HPF 220b.

[0067] Reference Figure 4a HPF 220b may include a first capacitor (HPF capacitor (HC) 1) 410, a second capacitor (HC2) 420, a third capacitor (HC3) 430 and an inductor (HL1) 440.

[0068] According to various implementation schemes, one end (I) of HC1 410 can be connected to the first port 221, and the other end (J) of HC1 410 can be connected to one end (K) of HC2 420. The other end (L) of HC2 420 can be connected to the third port 223. One end (M) of HC3 430 can be connected to one end (I) of HC1 410, while the other end (N) of HC3 430 can be connected to the other end (L) of HC2 420. One end (O) of HL1 440 can be connected between the other end (J) of HC1 410 and the other end (K) of HC2 420. The other end (P) of HL1 440 can be connected to ground formed on the PCB.

[0069] exist Figure 4a In the circuit configuration shown, the combination of HC1 410, HC2 420 and HC1 440 can function as a filter that allows high-frequency RF signals to pass through, and HC1 3430 can function as a filter that blocks low-frequency RF signals from passing through.

[0070] According to various embodiments, HC1 410 and HC2 420 can be patterned on a PCB, and HC3 430 and HC1 440 can be lumped elements disposed on the PCB surface. (See reference...) Figure 4b and Figure 4c The PCB may include a first layer 491, a second layer 492, and a third layer 493. The first layer 491 may be... Figure 3b The first layer, 391, is the same as the second layer, 492. Figure 3b The second layer 392 can be the same as or different from the third layer 493. Figure 3b The third layer 393 is the same as or different from the third layer.

[0071] According to various embodiments, a first pad 441, a second pad 442, and a first portion 411 of HC1 410 and a first portion 421 of HC2 420 can be formed in the first layer 491. One end (O) of HL1 440 can be attached to the first pad 441, and the other end (P) of HL1 440 can be attached to the second pad 442, which is separate from the first pad 441. The second pad 442 can be connected to ground. One end (M) of HC3 430 can be connected to the first portion 411 of HC1 410, while the other end (N) of HC3 430 can be connected to the first portion 421 of HC2 420. For example, two adjacent edges 411a and 421a of the first portion 411 of HC1 410 and the first portion 421 of HC2 420 can be used as pads to which HC3 430 is to be attached. The first portion 411 of HC1 410 can be connected to a first port 221. For example, a second contact 481 (1) extending from the first part 411 can be connected to the first port 221. The first part 421 of HC2 420 can be connected to the third port 223. For example, a third contact 482 (L) extending from the first part 421 can be connected to the third port 223.

[0072] According to various embodiments, the second portion 412 of HC1 410 and the second portion 422 of HC2 420 can be formed in the second layer 492. The second portions 412 of HC1 410 and 422 of HC2 420 can be connected to each other and can be connected to the first pad 441 using a sixth through-hole 471. According to one embodiment, when viewed along the z-axis, at least a portion of the first portion 411 of HC1 410 can overlap with the second portion 412 of HC1 410. As another example, when viewed along the z-axis, at least a portion of the first portion 421 of HC2 420 can overlap with the second portion 422 of HC2 420.

[0073] According to various embodiments, a third portion 413 of HC1 410 and a third portion 423 of HC2 420, separate from it, can be formed in a third layer 493. The third portion 413 of HC1 410 can be connected to the first portion 411. For example, a fourth contact point 483, separate from the second portion 412 of HC1 410, can be formed in a second layer 492. A fifth contact point 484 extending from the third portion 413 of HC1 410 can be connected to the fourth contact point 483 using a seventh through-hole 472, and the fourth contact point 483 can be connected to the second contact point 481 using an eighth through-hole 473. The third portion 423 of HC2 420 can be connected to the first portion 421. For example, a sixth contact point 485, separate from the second portion 422 of HC2 420, can be formed in a second layer 492. The seventh contact point 486, extending from the third portion 423 of HC2420, can be connected to the sixth contact point 485 using the ninth through hole 474, and the sixth contact point 485 can be connected to the third contact point 482 using the tenth through hole 475. According to one embodiment, when viewed along the z-axis, at least a portion of the second portion 412 of HC1 410 can overlap with the third portion 413 of HC1 410. As another example, when viewed along the z-axis, at least a portion of the second portion 421 of HC2 420 can overlap with the third portion 423 of HC2 420.

[0074] refer to Figure 4d When an RF signal is input to one of the first port 221 and the third port 223, for example, an RF signal of approximately 3 GHz or higher can be output to the other port via HPF 220b without any loss. RF signals of approximately 3 GHz or lower can essentially bypass HPF 220b. For example, the cutoff frequency of HPF 220b can be 3 GHz, and the cutoff band can be approximately 3 GHz or lower. According to one embodiment, the cutoff frequency can be changed when the capacitance of the capacitors (e.g., HC1 410, HC2 420, HC3 430) and / or the inductance of HL1 440 is changed.

[0075] Figure 5a This is a diagram showing the surface of the PCB 500, including the duplexer 220. Figure 5b This is a diagram showing the layer structure of the duplexer 220 in PCB 500, and Figure 5c This is a diagram illustrating the grounding layer structure in a PCB 500 according to an embodiment. Structurally and / or functionally related to... Figures 3a to 3d and Figures 4a to 4d The same configurations described herein may be represented by the same names and the same reference numerals, without being described in detail, or may be described briefly.

[0076] Reference Figure 5a PCB 500 may include a duplexer 220, which includes an LPF 220a and an HPF 220b. According to one embodiment, a first port 221, a second port 222, and a third port 223 may be formed in a first layer 510 of PCB 500. The first port 221 may be connected to a second contact point 481 in HPF 220b (e.g., ...). Figure 4a One end (1) of HC1 410 in the middle). The second port 222 can be connected to the first contact point 381 in LPF 220a (e.g. Figure 3a The other end (D) of LL2 322 in the middle). The third port 223 can be connected to the third contact point 482 in HPF 220b (e.g., Figure 4a The other end (L) of HC2420 in the diagram. According to one embodiment, LC2 312, LC3 313, HC3 430 and / or HL1 440 may be lumped elements disposed in the first layer 510. Lumped elements may be selectively disposed on PCB 500. For example, in the case of designing duplexer 220, lumped elements with values ​​that conform to the filtering performance of duplexer 220 may be selected.

[0077] Despite Figure 5a Not shown in the diagram, but LL1 321 and LL2 322 can be patterned on PCB 500. For example... Figure 5a As shown in sections 411 and 421, HC1 410 and HC2 420 can be patterned on PCB 500. Ground connected to the (2-2) pad 313b and the second pad 442 can be formed on PCB 500. For example, the first ground pattern 591 can be formed in the first layer 510 in the form of (e.g., a rectangular shape) surrounding at least a portion of LPF220a or HPF 220b. As illustrated in the embodiment, the (2-2) pad 313b can be formed as part of the first ground pattern 591. Although in Figure 5a Although not shown, the second pad 442 can be connected to the first ground pattern 591 via a conductive pattern (e.g., wiring, via) formed below the first layer 510 of the PCB 500. As another example, although the first ground pattern 591 is formed in the first layer 510, it can also be formed in another layer of the PCB 500.

[0078] Reference Figure 5bIn addition to the first layer 510, PCB 500 may also include a second layer 520, a third layer 530, a fourth layer 540, and / or a fifth layer 550. In addition to the first ground pattern 591, ground 590 may also include a second ground pattern 592 formed in the second layer 520, a third ground pattern 593 formed in the third layer 530, and / or a fourth ground pattern 594 formed in the fourth layer 540.

[0079] In the second layer 520, a first portion 321a of LL1 321, a first portion 322a of LL2 322, a second portion 412 of HC1410, and a second portion 422 of HC2 420 can be formed. A second ground pattern 592 can be configured to surround portions 321a, 322a, 412, and 422. According to one embodiment, the second ground pattern 592 can be aligned with the first ground pattern 591 and can have substantially the same shape as the first ground pattern 591 (e.g., a rectangular shape). For example, when viewed in the z-axis direction, the second ground pattern 592 can overlap with the first ground pattern 591.

[0080] According to one embodiment, a first wiring 521 extending from point 592a on the first side of the second grounding pattern 592 to point 592b on the second side parallel to the first side can be additionally formed in the second layer 520.

[0081] According to one embodiment, the second pad 442 can be connected to a point (eighth contact point) 521a of the first wiring 521 using an eleventh via 571. For example, the second pad 442 can be connected to a second ground pattern 592 using the eleventh via 571 and the eighth contact point 521a formed in the first wiring 521.

[0082] According to one embodiment, in the third layer 530, a second portion 321b of LL1 321, a second portion 322b of LL2 322, a third portion 413 of HC1 410, and / or a third portion 423 of HC2 420 may be formed. A third ground pattern 593 may surround portions 321b, 322b, 413, and 423. According to one embodiment, the third ground pattern 593 may be aligned with the second ground pattern 592 and may have substantially the same shape as the second ground pattern 592 (e.g., a rectangular shape). For example, when viewed in the z-axis direction, at least a portion of the third ground pattern 593 may overlap with the second ground pattern 592.

[0083] According to one embodiment, a second wiring 531 extending from point 593a in any side of the third ground pattern 593 (e.g., the side aligned with the second side of the second ground pattern 592) may be additionally formed in the third layer 530.

[0084] According to an embodiment, using the twelfth via 572, the eighth contact point 521a can be connected to the ninth contact point 531a of the second wiring 531 formed in the third layer 530. The tenth contact point 521b of the first wiring 521 can be connected to the eleventh contact point 531b of the second wiring 531 using the thirteenth via 573. For example, the second pad 442 formed in the first layer 510 can also be connected to the third ground pattern 593 using the second wiring 531 and the thirteenth via 573.

[0085] According to one embodiment, a third wiring 532 connecting the second portion 321b of LL1321 to the fifth contact point 484 can be additionally formed in the third layer 530. Therefore, LPF 220a can be connected to the first port 221 via the fifth contact point 484.

[0086] According to one embodiment, a fourth ground pattern 594 formed in the fourth layer 540 may be aligned with a third ground pattern 593 and may have substantially the same shape (e.g., a rectangular shape). For example, when viewed in the z-axis direction, at least a portion of the third ground pattern 593 may overlap with the fourth ground pattern 594. According to one embodiment, a fourth wiring 541 aligned with the first wiring 521 and having the same shape may be additionally formed in the fourth layer 540. For example, when viewed in the z-axis direction, at least a portion of the first wiring 521 may overlap with the fourth wiring 541.

[0087] According to one embodiment, the ninth contact point 531a can be connected to the twelfth contact point 541a of the fourth wiring 541 using the fourteenth via 574. The eleventh contact point 531b can be connected to the thirteenth contact point 541b of the fourth wiring 541 using the fifteenth via 575. For example, the second pad 442 formed in the first layer 510 can also be connected to the fourth ground pattern 594 using the fourth wiring 541.

[0088] According to one embodiment, a shielding sheet 560 may be formed in the fifth layer 550. The shielding sheet 560 may be formed as a single metal plate and may overlap with ground 590 when facing the PCB 500 in the z-axis direction. The shielding sheet 560 may be used to isolate the duplexer 220 from external electronic components. For example, the shielding sheet 560 may reduce the impact of RF signals transmitted or received in the duplexer 220 on external electronic components located below the fifth layer 550 (e.g., in the -z-axis direction). For example, the shielding sheet 560 may be connected to the fourth ground pattern 594 using a sixteenth via 576 and may act as a ground.

[0089] According to one embodiment, ground 590 can be implemented with a shield-like structure to increase the degree of isolation from external electronic components surrounding duplexer 220 or from other conductive parts in PCB 500. For example, as Figure 5c As shown, multiple paths for electrically connecting grounding patterns 591, 592, 593 and 594 can be formed along the edges of grounding patterns 591, 592, 593 and 594.

[0090] According to one embodiment, PCB 500 may also include one or more layers. For example, another duplexer configured with a pattern substantially the same as the duplexer 220 described above, another conductive line or other component may be disposed below the fifth layer 550 (e.g., in the -z axis direction).

[0091] Figure 6a This is a cross-sectional view of PCB 600 including duplexer 220, and... Figure 6b This is a diagram showing the layer structure of the duplexer 220 in PCB 600. It is structurally and / or functionally related to... Figures 3a to 3d and Figures 4a to 4d The same configurations described herein may be represented by the same names and the same reference numerals, without being described in detail, or may be described briefly.

[0092] Reference Figure 6a PCB 600 may include a first layer 601, a second layer 602, a third layer 603, a fourth layer 604, a fifth layer 605, a sixth layer 606, a seventh layer 607, an eighth layer 608, a ninth layer 609, and / or a tenth layer 610. A first port 221, a second port 222, and a third port 223 may be formed in the fifth layer 605, the second layer 602, and the eighth layer 608, respectively. According to one embodiment, LC2 312, LC3 313, and / or HL1 440 may be lumped elements and may be disposed in the first layer 510.

[0093] refer to Figure 6b Other components of duplexer 220 (LL1 321, LL2 322, HC1 410, HC2420, HC3620) can be patterned on PCB 600. Ground 680 connected to pad (2-2) 313b and pad 442 may include multiple ground patterns 681, 682, 683, 684, 685, 686, 687, 688, 689 and 690 formed in various layers of PCB 600.

[0094] According to one embodiment, pad (1-1) 312a, pad (1-2) 312b, pad (2-1) 313a, pad (2-2) 313b, first pad 441, and / or second pad 442 may be formed in the first layer 601. A first ground pattern 681 may be provided in the form of surrounding at least a portion of the pads (e.g., rectangular) and may be formed in the first layer 601. As shown in the embodiment, pad (2-2) 313b and second pad 442 may be formed as part of the first ground pattern 681.

[0095] According to one embodiment, the first portion 321a of LL1 321 and the first portion 322a of LL2 322 can be formed in the second layer 602. A second ground pattern 682 can be configured to surround portions 321a and 322a. For example, when viewed in the + z-axis direction, the second ground pattern 682 can at least partially overlap with the first ground pattern 681 and can have substantially the same shape as the first ground pattern 681 (e.g., a rectangular shape).

[0096] According to an embodiment, the 14th contact point 631 extending from one end 322a_1 of the first portion 322a of LL2 322 (e.g.) Figure 3a The other end (D) of LL2 322 can be connected to the second port 222 via wiring.

[0097] According to one embodiment, a 15th contact point 632 may be additionally formed in the second layer 602, and the 15th contact point 632 may be electrically connected to the first pad 441 using a through-hole.

[0098] According to one embodiment, the second portion 321b of LL1 321 and the second portion 322b of LL2 322 can be formed in the third layer 603. A third grounding pattern 683 can be formed to surround portions 321b and 322b. For example, when viewed in the +z axis direction, the third grounding pattern 683 can at least partially overlap with the second grounding pattern 682 and can have a substantially the same shape as the second grounding pattern 682 (e.g., a rectangular shape).

[0099] According to one embodiment, a 16th contact point 633 may be additionally formed in the third layer 603, and the 16th contact point 633 may be connected to the first pad 441 using the 15th contact point 632 and a through-hole.

[0100] According to one embodiment, a fourth ground pattern 684 formed in the fourth layer 604 can be connected to a third ground pattern 683 using one or more 19th vias 653. The fourth ground pattern 684 can be implemented as a single metal plate and can be used as a shield to separate an upper layer (e.g., in the + z-axis direction) from a lower layer (e.g., in the - z-axis direction) based on the fourth layer 604. According to one embodiment, the fourth layer 604 can be a ground layer of a PCB 600.

[0101] According to one embodiment, a seventeenth contact point 634 and / or an eighteenth contact point 635, separate from the fourth ground pattern 684, may be additionally formed in the fourth layer 604. The seventeenth contact point 634 may be electrically connected to the first pad 441 via the fifteenth contact point 632, the sixteenth contact point 633, and a via. The eighteenth contact point 635 may be electrically connected to the other end 321b_2 of the second portion 321b of LL1 321 using a via.

[0102] According to one embodiment, the second contact point 481, the first portion 411 of HC1 410, the second portion 422 of HC2 420, and the sixth contact point 484 may be formed in the fifth layer 605. A fifth grounding pattern 685 may be formed to surround portions 411 and 422. For example, when viewed in the + z-axis direction, the fifth grounding pattern 685 may at least partially overlap with the third grounding pattern 683 and may have substantially the same shape as the third grounding pattern 683 (e.g., a rectangular shape).

[0103] According to one embodiment, a second contact point 481 extending from the first portion 411 of HC1 410 (e.g.) Figure 4a One end (I) of HC1 410 can be connected to the first port 221 formed in the fifth layer 605 via wiring. For example, one end of HC1 410 can be connected to the first port 221 via a second contact point 481. The second contact point 481 can be connected to the eighteenth contact point 635 via a via. For example, one end of LL1 321 can be connected to the first port 221 via the eighteenth contact point 635.

[0104] According to one embodiment, a nineteenth contact 636 extending from the second portion 422 of HC2 420 can be connected to a seventeenth contact 634 via a path. For example, the second portion 422 of HC2 420 can be connected to a first pad 441 via the nineteenth contact 636.

[0105] According to one embodiment, the third contact point 482, the fourth contact point 483, the second portion 412 of HC1 410, and / or the first portion 421 of HC2 420 may be formed in the sixth layer 606. The sixth grounding pattern 686 may be formed to surround at least a portion of portions 412 and 421. For example, when viewed in the + z-axis direction, the sixth grounding pattern 686 may at least partially overlap with the fifth grounding pattern 685 and may have substantially the same shape as the fifth grounding pattern 685 (e.g., a rectangular shape). The third contact point 482 extends from the first portion 421 of HC2 420 (e.g., ...). Figure 4a The other end (L) of the HC2420 can be connected to the third port 223 via wiring. For example, the other end (L) of the HC2420 can be electrically connected to the third port 223.

[0106] According to one embodiment, a twentieth contact 637 extending from the second portion 412 of HC1 410 can be connected to a nineteenth contact 636 via a path. For example, the twentieth contact 637 can be used to electrically connect the second portion 412 of HC1 410 to the first pad 441 and the second portion 422 of HC2 420.

[0107] According to one embodiment, the third portion 413 of HC1 410, the third portion 423 of HC2 420, and the fifth contact point 484 may be formed in the seventh layer 607. The seventh grounding pattern 687 may be formed to surround at least a portion of portions 413 and 423. For example, when viewed in the + z-axis direction, the seventh grounding pattern 687 may at least partially overlap with the sixth grounding pattern 686 and may have substantially the same shape as the sixth grounding pattern 686 (e.g., a rectangular shape).

[0108] According to one embodiment, a second 1st contact point 638 extending from the third portion 423 of HC2 420 may be additionally formed in the seventh layer 570. The second 1st contact point 638 may be connected to the 20th contact point 637 via a via. For example, the third portion 423 of HC2420 may be connected to the first pad 441 via the second 1st contact point 638.

[0109] According to one embodiment, a second contact point 639, separate from the third portion 423 of HC2 420, may be additionally formed in the seventh layer 570. The second contact point 639 may be connected to the third contact point 482 using a through-hole.

[0110] According to one embodiment, a first portion 621 of HC3 620 may be formed in an eighth layer 608. An eighth ground pattern 688 may be formed to surround the first portion 621 of HC3 620. For example, when viewed in the + z axis direction, the eighth ground pattern 688 may at least partially overlap with a seventh ground pattern 687 and may have substantially the same shape as the seventh ground pattern 687 (e.g., a rectangular shape).

[0111] According to one embodiment, a 23rd contact point 621a extending from a first portion 621 of HC3 620 can be connected to a 22nd contact point 639 via a path. For example, the first portion 621 of HC3 620 can be connected to a third port 223 via the 23rd contact point 621a.

[0112] According to one embodiment, the twenty-fourth contact point 640 and the twenty-fifth contact point 641 connected thereto may be additionally formed in the eighth layer 608. The twenty-fourth contact point 640 may be connected to the fifth contact point 484 via a path.

[0113] According to one embodiment, the second portion 622 of HC3 620 may be formed in the ninth layer 609. A ninth ground pattern 689 may be formed to surround the second portion 622 of HC3 620. For example, when viewed in the + z axis direction, the ninth ground pattern 689 may at least partially overlap with the eighth ground pattern 688 and may have substantially the same shape as the eighth ground pattern 688 (e.g., a rectangular shape).

[0114] According to one embodiment, a twenty-sixth contact 622a extending from the second portion 622 of HC3 620 can be connected to a twenty-fifth contact 641 via a path. For example, the second portion 622 of HC3 620 can be connected to a first port 221 via the twenty-sixth contact 622a.

[0115] According to one embodiment, when viewed in the + z axis direction, the tenth ground pattern 690 formed in the tenth layer 610 may at least partially overlap with the ninth ground pattern 689 and may have the same shape (e.g., a rectangular shape).

[0116] According to one embodiment, ground 680 can be implemented with the following characteristics: Figure 5c The cage-like structure shown uses multiple vias to increase the degree of isolation from external electronic components surrounding the duplexer 220. For example, the first to tenth ground patterns 681 to 690 can be electrically connected using multiple vias. As another example, the first to tenth ground patterns 681 to 690 can be electrically connected to a ground included in the PCB 600.

[0117] According to one embodiment, the first to third layers 681 to 683 can form an LPF (e.g., Figure 3a LPF 220a). As another example, layers 685 to 689, from the fifth to the ninth, can form an HPF (e.g., LPF 220a). Figure 4a HPF 220b).

[0118] Figure 6a and Figure 6b A duplexer layer structure can include a greater number of layers for the PCB. Therefore, it can be more... Figures 5a to 5c The duplexer layer structure is thick, but it can preserve the usable area (XY region). Therefore, it can selectively use the duplexer based on the internal spatial structure of the set (e.g., a smartphone). Figures 5a to 5c structure or Figure 6a and Figure 6b The structure.

[0119] Electronic devices according to various embodiments may include an antenna, wireless communication circuitry, and a duplexer (e.g., duplexer 220) connected to the antenna and the wireless communication circuitry. The duplexer may include a first port connected to the antenna; a second port connected to the wireless communication circuitry; a third port connected to the wireless communication circuitry; a low-pass filter (LPF) (e.g., LPF 220a) configured to filter a signal received from one of the first and second ports to obtain a low-frequency RF signal and output it to another port between the first and second ports; and a high-pass filter (HPF) (e.g., HPF 220b) configured to filter a signal received from one of the first and third ports to obtain a high-frequency RF signal and output it to another port between the first and third ports. The LPF may include a capacitor disposed on the surface of a printed circuit board (PCB) and an inductor formed in a pattern on the PCB. The HPF may include an inductor disposed on the surface of the PCB and a capacitor formed in a pattern on the PCB.

[0120] The LPF may include LPF capacitors (LC)2 and LC3, LPF inductors (LL)1 and LL2, and the HPF may include HPF capacitors (HC)1, HC2, HC3, and HPF inductor (HL)1. One end of LL1 can be connected to a first port, the other end of LL1 is connected to one end of LL2, and the other end of LL2 is connected to a second port. One end of LC2 is connected to one end of LL2, and the other end of LC2 is connected to the other end of LL2. One end of LC3 can be connected to the other end of LL1 and one end of LL2, and the other end of LC3 is connected to ground formed in the PCB. One end of HC1 is connected to the first port, and the other end of HC1 is connected to one end of HC2. The other end of HC2 can be connected to a third port 223. One end of HC3 can be connected to one end of HC1, and the other end of HC3 can be connected to the other end of HC2. One end of HL1 can be connected to the other end of HC1 and one end of HC2. The other end of HL1 can be connected to ground formed in the PCB. LC2, LC3, and HL1 can be lumped elements disposed on the PCB surface, and LL1, LL2, HC1, and HC2 can be patterned on the PCB. HC3 can be a lumped element disposed on the PCB surface, or can be patterned on the PCB.

[0121] The HC3 may be a lumped element disposed on the surface of the PCB, and the PCB may include a first layer, the first layer including the PCB surface, and forming pads for disposing of the lumped element, a first portion of the HC1 and a first portion of the HC2; a second layer disposed below the first layer, and forming a first portion of the LL1, a first portion of the LL2, a second portion of the HC1 and a second portion of the HC2; and a third layer disposed below the second layer, and forming a second portion of the LL1, a second portion of the LL2, a third portion of the HC1 and a third portion of the HC2.

[0122] The PCB may also include a shield disposed below the third layer. Grounding may include ground patterns formed in each layer of the PCB. Grounding may include a first ground pattern disposed in the first layer as a package pad, a first portion of HC1, and a first portion of HC2; a second ground pattern disposed in the second layer as surrounding a first portion of LL1, a first portion of LL2, a second portion of HC1, and a second portion of HC2; and a third ground pattern disposed in the third layer as surrounding a second portion of LL1, a second portion of LL2, a third portion of HC1, and a third portion of HC2. The pad to which the other end of LC3 is connected may be configured as part of the first ground pattern. Ground patterns may be aligned, and multiple paths connecting the ground patterns may be formed along the edges of the ground patterns.

[0123] HC3 can be patterned on a PCB, and the PCB can include a first layer including a PCB surface and forming pads for mounting lumped components in the first layer; a second layer below the first layer, in which first portions of LL1 and LL2 are formed; a third layer below the second layer, in which second portions of LL1 and LL2 are formed; a fourth layer below the third layer and including a shield; a fifth layer below the fourth layer, in which the first portions of HC1 and HC2 are formed; a sixth layer below the fifth layer, in which the second portions of HC1 and HC2 are formed; a seventh layer below the sixth layer, in which third portions of HC1 and HC2 are formed; an eighth layer below the seventh layer, in which the first portion of HC3 is formed; and a ninth layer below the eighth layer, in which the second portion of HC3 is formed.

[0124] Grounding may include ground patterns formed in each layer of the PCB. Grounding may include a first ground pattern in the form of package pads in a first layer; a second ground pattern in the form of first portions of packages LL1 and LL2 in a second layer; a third ground pattern in the form of second portions of packages LL1 and LL2 in a third layer; a fourth ground pattern including the shielding sheet formed in the fourth layer; a fifth ground pattern in the form of first portions of packages HC1 and HC2 in a fifth layer; a sixth ground pattern in the form of second portions of packages HC1 and HC2 in a sixth layer; a seventh ground pattern in the form of third portions of packages HC1 and HC2 in a seventh layer; an eighth ground pattern in the form of first portions of packages HC3 in an eighth layer; and a ninth ground pattern in the form of second portions of packages HC3 in a ninth layer. A pad connected to the other end of LC3 may be configured as part of the first ground pattern. A pad connected to the other end of HL1 may be configured as another part of the first ground pattern. Ground patterns may be aligned, and multiple vias connecting the ground patterns may be formed along the edges of the ground patterns.

[0125] The first, second, and third ports can be formed on the surface of the PCB. The ground pattern connecting the LPF and HPF can be formed on the PCB in the form of LPF and HPF packages, and the first, second, and third ports can be formed within the outer boundary of the ground pattern.

[0126] The low-frequency band can be less than or equal to approximately 3 GHz, while the high-frequency band can be greater than or equal to approximately 3 GHz.

[0127] The embodiments of this disclosure provided in this specification and accompanying drawings are merely examples to facilitate the description of the technology associated with the embodiments of this disclosure and to aid in the understanding of the embodiments of this disclosure, and are not intended to limit the scope of the embodiments of this disclosure. Therefore, the scope of the various embodiments of this disclosure should be interpreted to include all modifications or variations based on the technical ideas of the various embodiments of this disclosure, in addition to the embodiments disclosed herein.

Claims

1. An electronic device comprising: antenna; Wireless communication circuits; as well as A duplexer, connected to the antenna and the wireless communication circuit, The duplexer includes: The first port is connected to the antenna; The second port is connected to the wireless communication circuit; The third port is connected to the wireless communication circuit; A low-pass filter (LPF) is configured to filter a signal received from one of the first port and the second port to obtain a low-frequency RF signal and output it to another port between the first port and the second port. A high-pass filter (HPF) is configured to filter a signal received from one of the first port and the third port to obtain a high-frequency RF signal, and output it to another port between the first port and the third port; and The grounding structure is connected to the LPF and the HPF. The LPF includes capacitors disposed as lumped elements on the surface of a printed circuit board (PCB) and inductors embedded in the PCB in a patterned manner. The HPF includes an inductor disposed as a lumped element on the surface of the PCB and a capacitor embedded in the PCB in a patterned manner. The PCB includes multiple layers, and The grounding structure is formed in the PCB and includes multiple grounding patterns that surround the LPF and HPF, are aligned in the direction in which the multiple layers are stacked, and are electrically connected through multiple vias.

2. The electronic device according to claim 1, wherein, The LPF includes LPF capacitors LC2 and LC3, and LPF inductors LL1 and LL2, and the HPF includes HPF capacitors HC1, HC2, and HC3, and HPF inductor HL1. One end of LL1 is connected to the first port, and the other end of LL1 is connected to one end of LL2. The other end of LL2 is connected to the second port, one end of LC2 is connected to one end of LL2, and the other end of LC2 is connected to the other end of LL2. One end of LC3 is connected to the other end of LL1 and one end of LL2, and the other end of LC3 is connected to the grounding structure. Wherein, one end of HC1 is connected to the first port, and the other end of HC1 is connected to one end of HC2. The other end of HC2 is connected to the third port. Wherein, one end of HC3 is connected to one end of HC1, and the other end of HC3 is connected to the other end of HC2. Wherein, one end of HL1 is connected to the other end of HC1 and one end of HC2. The other end of HL1 is connected to the grounding structure. Wherein, LC2, LC3, and HL1 are lumped elements disposed on the surface of the PCB. Wherein, LL1, LL2, HC1 and HC2 are formed on the PCB in the form of a pattern, and HC3 is a lumped element disposed on the surface of the PCB, or is formed on the PCB in the form of a pattern.

3. The electronic device according to claim 2, wherein, The HC3 is a lumped element disposed on the surface of the PCB, and the PCB includes: The first layer includes the surface of the PCB, and pads for mounting lumped components, the first portion of HC1, and the first portion of HC2 are formed therein; A second layer is disposed below the first layer, and wherein a first portion of LL1, a first portion of LL2, a second portion of HC1, and a second portion of HC2 are formed therein; and The third layer is disposed below the second layer, wherein the second part of LL1, the second part of LL2, the third part of HC1, and the third part of HC2 are formed.

4. The electronic device according to claim 3, wherein, The PCB also includes a shielding sheet disposed below the third layer.

5. The electronic device according to claim 3, wherein, The plurality of grounding patterns include: A first grounding pattern is disposed in the first layer and encapsulates the pads, the first portion of HC1, and the first portion of HC2; A second grounding pattern is disposed in the second layer and encapsulates the first portion of LL1, the first portion of LL2, the second portion of HC1, and the second portion of HC2; and A third grounding pattern is disposed in the third layer and encapsulates the second portion of LL1, the second portion of LL2, the third portion of HC1, and the third portion of HC2.

6. The electronic device according to claim 5, wherein, The pad connected to the other end of the LC3 is configured as part of the first grounding pattern.

7. The electronic device according to claim 5, wherein, The plurality of vias are formed along the edges of the plurality of grounding patterns.

8. The electronic device according to claim 2, wherein, The HC3 is patterned on the PCB, and the PCB includes: The first layer defines the surface of the PCB and has pads formed therein for mounting lumped components; The second layer is located below the first layer, and forms the first portion of LL1 and the first portion of LL2 therein; The third layer is located below the second layer, and forms the second portion of LL1 and the second portion of LL2 therein; The fourth layer, located below the third layer, includes a shielding sheet; The fifth layer is located below the fourth layer, and the first portion of HC1 and the first portion of HC2 are formed therein; The sixth layer is located below the fifth layer, and the second portion of HC1 and the second portion of HC2 are formed therein; The seventh layer is located below the sixth layer, and the third portion of HC1 and the third portion of HC2 are formed therein; The eighth layer, located below the seventh layer, and wherein the first portion of the HC3 is formed; and The ninth layer is located below the eighth layer and forms the second part of the HC3 therein.

9. The electronic device according to claim 8, wherein, The plurality of grounding patterns include: A first grounding pattern is disposed in the first layer and encapsulates the pads; A second grounding pattern is disposed in the second layer and encapsulates the first portion of LL1 and the first portion of LL2; A third grounding pattern is disposed in the third layer and encapsulates the second portion of LL1 and the second portion of LL2; The fourth grounding pattern includes the shielding sheet and is formed in the fourth layer; A fifth grounding pattern is disposed in the fifth layer and encapsulates the first portion of HC1 and the first portion of HC2; A sixth grounding pattern is disposed in the sixth layer and encapsulates the second portion of HC1 and the second portion of HC2; A seventh grounding pattern is disposed in the seventh layer and encapsulates the third portion of HC1 and the third portion of HC2; An eighth grounding pattern is disposed in the eighth layer and encapsulates the first portion of the HC3; and A ninth grounding pattern is disposed in the ninth layer and encapsulates the second part of the HC3.

10. The electronic device according to claim 9, wherein, The pad connected to the other end of LC3 is configured as part of the first grounding pattern, and The pad connected to the other end of the HL1 is configured as another part of the first grounding pattern.

11. The electronic device according to claim 9, wherein, The plurality of vias are formed along the edges of the plurality of grounding patterns.

12. The electronic device according to claim 1, in, The first port, the second port, and the third port are formed in the surface of the PCB and in the outer boundary of the plurality of grounding patterns.

13. The electronic device according to claim 1, wherein, The low-frequency band is less than or equal to 3 GHz, and the high-frequency band is greater than or equal to 3 GHz.

14. The electronic device according to claim 1, further comprising: A first duplexer is configured to filter a signal received from the wireless communication circuit to obtain an RF signal having a first transmit frequency band and output it to the LPF, and is also configured to filter a signal received from the LPF to obtain an RF signal having a first receive frequency band and output it to the wireless communication circuit. as well as The second duplexer is configured to filter the signal received from the wireless communication circuit to obtain an RF signal with a second transmit frequency band and output it to the HPF, and is also configured to filter the signal received from the HPF to obtain an RF signal with a second receive frequency band and output it to the wireless communication circuit.

15. The electronic device of claim 14, further comprising: A power amplifier is configured to amplify the power of a signal received from the wireless communication circuit and output it to the first duplexer or the second duplexer.

16. The electronic device according to claim 1, wherein, The lumped element is disposed on the outer surface of the PCB.

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