A transceiver circuit, communication system and electronic device

Abstract

Embodiments of the present application provide a transceiver circuit, a communication system and an electronic device, relate to the technical field of communication, and can solve the problem of large insertion loss of the transceiver circuit. The transceiver circuit comprises a first transformer, a receiving amplification circuit, a transmitting amplification circuit, a voltage terminal and an input / output port. The first transformer comprises a first coil and a second coil which are coupled to each other. The first coil is coupled to the voltage terminal, an input port of the receiving amplification circuit and an output port of the transmitting amplification circuit respectively. The second coil is coupled to the input / output port.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a transceiver circuit, a communication system, and an electronic device. Background Technology

[0002] To reduce the area and complexity of communication systems in electronic devices, such as to save antenna array area in communication systems, communication systems usually adopt the method of TR (transmitter and receiver) sharing an antenna. Therefore, TR combining is required in front of the antenna feed point through transceiver circuit (that is, the output port of the transmit link and the input port of the receive link are combined into one port).

[0003] However, existing TR combining methods using transceiver circuits introduce significant insertion loss, which drastically reduces the output power and efficiency of the TX (transmit) link while increasing noise in the RX (receive) link. The classic Shannon theorem states that communication rate is related to bandwidth and signal-to-noise ratio (SNR), and can be increased by increasing bandwidth or improving the SNR (higher-order modulation). Because existing TR combining methods increase insertion loss, reduce the output power and efficiency of the TX link, and increase noise in the RX link, they consequently reduce bandwidth and lower the SNR, leading to a decrease in communication rate. Summary of the Invention

[0004] Embodiments of this application provide a transceiver circuit, a communication system, and an electronic device that can solve the problem of high insertion loss in the transceiver circuit.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] Firstly, a transceiver circuit is provided, comprising a first transformer, a receiving amplifier circuit, a transmitting amplifier circuit, a voltage terminal, and input / output ports. The first transformer includes a first coil and a second coil coupled to each other. The first coil is coupled to the voltage terminal, the input port of the receiving amplifier circuit, and the output port of the transmitting amplifier circuit, respectively. The second coil is coupled to the input / output ports. The transmitting and receiving amplifier circuits can be used to transmit differential signals or single-ended signals. Both the input port of the receiving amplifier circuit and the output port of the transmitting amplifier circuit are coupled to the first coil of the first transformer, and the second coil of the first transformer is coupled to the input / output ports. When the transmitting amplifier circuit is in a non-operating mode and the receiving amplifier circuit is in an operating mode, the transmitting amplifier circuit has a relatively small impact on the receiving amplifier circuit because it is in a high-impedance state. When the transmitting amplifier circuit adopts a common-source common-gate structure, its impedance is even higher when it is in a non-operating mode, further reducing its impact on the receiving amplifier circuit. When the receiving amplifier circuit is in a non-operating mode and the transmitting amplifier circuit is in an operating mode, the input port of the receiving amplifier circuit is in a high-impedance state because the transceiver circuit operates at low frequencies. Since both the input port of the receiving amplifier circuit and the output port of the transmitting amplifier circuit are coupled to the first coil of the first transformer, the receiving amplifier circuit has little impact on the transmitting amplifier circuit in the low-frequency operating mode. This allows for low insertion loss. In the transmitting mode, the output power and efficiency of the transmitting link can be improved, and in the receiving mode, the noise of the receiving link can be reduced, thereby increasing the communication rate.

[0007] In one possible implementation, the transceiver circuit further includes a first matching network coupled between the input port of the receiving amplifier circuit and the first coil. Since the impedance of the input port of the receiving amplifier circuit is low at high frequencies, the receiving amplifier circuit can influence the transmitting amplifier circuit during operation, increasing insertion loss. Therefore, by adding a first matching network between the input port of the receiving amplifier circuit and the first coil, the impedance of the receiving amplifier circuit connected to the first coil can be directly transformed into a high impedance through the impedance transformation characteristics of the first matching network. This ensures that the influence of the receiving amplifier circuit on the transmitting amplifier circuit is minimized at high frequencies, reducing insertion loss.

[0008] Based on this, when the transmitting amplifier circuit is operating, since the receiving amplifier circuit has a high impedance, the first transformer can transform the load impedance of the input and output ports to the optimal impedance required by the transmitting amplifier circuit. When the receiving amplifier circuit is operating and the transmitting amplifier circuit is not operating, the transmitting amplifier circuit has a high impedance. In this case, the first transformer transforms the load impedance of the input and output ports to a lower impedance, and then transforms it to the optimal impedance required by the receiving amplifier circuit through the first matching network. Since the receiving amplifier circuit mainly optimizes noise, while the transmitting amplifier circuit mainly optimizes power and efficiency, the difference between the optimal impedances of the receiving and transmitting amplifier circuits is relatively large. However, due to the addition of the first matching network, the load impedance of the input and output ports can be matched to the optimal impedance required by the transmitting amplifier circuit in transmitting mode, and in receiving mode, the load impedance of the input and output ports can be matched to the optimal impedance required by the receiving amplifier circuit. Therefore, simultaneous matching of the optimal impedances of the transmitting and receiving amplifier circuits can be achieved.

[0009] In one possible implementation, the transceiver circuit further includes a switch coupled between the first matching network and the input port of the receiving amplifier circuit. In transmit mode, the switch is on; in receive mode, the switch is off. With the switch included, in transmit mode, when the switch is on, and the transceiver circuit operates at high frequencies, the sum of the impedance of the switch and the impedance of the receiving amplifier circuit is low, approximately equal to the on-resistance of the switch. Through the impedance transformation characteristics of the first matching network, the impedance on the side of the receiving amplifier circuit connected to the first coil can be directly transformed into high impedance. This ensures that, at high frequencies, the influence of the receiving amplifier circuit on the transmitting amplifier circuit is minimized, reducing insertion loss.

[0010] In one possible implementation, the first matching network is located within the first and second coils of the first transformer. This reduces the area of ​​the transceiver circuit.

[0011] In one possible implementation, the transceiver circuit further includes a second matching network coupled between the output port of the transmitting amplifier circuit and the first coil. Coupled between the output port of the transmitting amplifier circuit and the first coil, the second matching network serves two purposes. First, when the receiving amplifier circuit is operating and the transmitting amplifier circuit is not operating, the impedance of the transmitting amplifier circuit is high. In this case, the impedance of the transmitting amplifier circuit plus the impedance of the second matching network can make the impedance on the side of the transmitting amplifier circuit connected to the first coil even higher. This further reduces the impact of the transmitting amplifier circuit on the receiving amplifier circuit when the receiving amplifier circuit is operating, and further reduces insertion loss. Second, in the transmitting mode, the first transformer transforms the load impedance of the input / output port to an impedance, and then transforms it to the optimal impedance required by the transmitting amplifier circuit through the second matching network. This is more conducive to matching the optimal impedance required by the transmitting amplifier circuit.

[0012] In one possible implementation, the second matching network is located within the first and second coils of the first transformer. This reduces the area of ​​the transceiver circuit.

[0013] In one possible implementation, the transceiver circuit further includes a ground terminal; the input / output port is a single-ended port, with a first end of the second coil coupled to the input / output port and a second end of the second coil coupled to the ground terminal; alternatively, the input / output port includes a first differential input / output port and a second differential input / output port, with a first end of the second coil coupled to the first differential input / output port and a second end of the second coil coupled to the second differential input / output port. When the input / output port is a single-ended port, it can transmit single-ended signals; when it is a differential port, it can be used to transmit differential signals.

[0014] In one possible implementation, the transceiver circuit further includes an antenna; the input / output ports are single-ended ports, and the antenna is coupled to the input / output ports; alternatively, the input / output ports include a first differential input / output port and a second differential input / output port, and the antenna includes a first antenna differential port and a second antenna differential port; the first differential input / output port is coupled to the first antenna differential port, and the second differential input / output port is coupled to the second antenna differential port. The antenna can be used to transmit single-ended signals or differential signals.

[0015] In one possible implementation, the output ports of the transmitting amplifier circuit include a first differential transmitting output port and a second differential transmitting output port; a first end of the first coil is coupled to the first differential transmitting output port, and a second end of the first coil is coupled to the second differential transmitting output port; and / or, the input ports of the receiving amplifier circuit include a first differential receiving input port and a second differential receiving input port; a first end of the first coil is coupled to the first differential receiving input port, and a second end of the first coil is coupled to the second differential receiving input port. In this case, the transmitting amplifier circuit and the receiving amplifier circuit are used to transmit differential signals.

[0016] In one possible implementation, the transceiver circuit includes a first matching network; the first matching network includes a first matching device and a second matching device; the first matching device is coupled between a first end of a first coil and a first differential receive input port, and the second matching device is coupled between a second end of the first coil and a second differential receive input port. In this case, the first matching device and the second matching device can be, for example, a transmission line, an inductor, a capacitor, a resistor, etc.

[0017] In one possible implementation, the transceiver circuit includes a first matching network, which includes a first matching device and a second matching device; the first matching network is a second transformer; both the first and second matching devices are coils; the first matching device is coupled between a first end and a second end of a first coil; and the second matching device is coupled between a first differential receive input port and a second differential receive input port. In this case, the first matching network is the second transformer, and the first and second matching devices are the primary and secondary coils of the second transformer, respectively.

[0018] In one possible implementation, the transceiver circuit includes a first matching network; the first matching network is located within the first and second coils of the first transformer; the first matching network forms a figure-eight shape with four ports. Because the figure-eight shape has good anti-interference characteristics, when the first matching network forms a figure-eight shape with four ports, the coupling between the first matching network and the first transformer is very low, thus ensuring that the first matching network and the first transformer do not interfere with each other.

[0019] In one possible implementation, the first matching network includes a first matching device and a second matching device; both the first and second matching devices are arranged in a figure-eight configuration with two ports. When the first matching device is arranged in a figure-eight configuration with two ports, the coupling between the first matching device and the first transformer is very low due to the good anti-interference characteristics of the figure-eight configuration, thus preventing them from interfering with each other. Similarly, when the second matching device is arranged in a figure-eight configuration with two ports, the coupling between the second matching device and the first transformer is also very low due to the good anti-interference characteristics of the figure-eight configuration, preventing them from interfering with each other.

[0020] In one possible implementation, portions of the first matching device and the second matching device overlap. This reduces the area occupied by the first matching network.

[0021] In one possible implementation, the transceiver circuit includes a second matching network; the second matching network includes a third matching device and a fourth matching device; the third matching device is coupled between a first end of the first coil and a first differential transmit output port, and the fourth matching device is coupled between a second end of the first coil and a second differential transmit output port. In this case, the third and fourth matching devices can be, for example, transmission lines, inductors, capacitors, resistors, etc.

[0022] In one possible implementation, the transceiver circuit includes a second matching network, which comprises a third matching device and a fourth matching device; the second matching network is a third transformer; both the third and fourth matching devices are coils; the third matching device is coupled between a first end and a second end of a first coil; and the fourth matching device is coupled between a first differential transmit output port and a second differential transmit output port. In this case, the second matching network is a third transformer, and the third and fourth matching devices are the primary and secondary coils of the third transformer, respectively.

[0023] In one possible implementation, the transceiver circuit includes a second matching network; the second matching network is located within the first and second coils of the first transformer; the second matching network forms a figure-eight shape with four ports. Because the figure-eight shape has good anti-interference characteristics, when the second matching network forms a figure-eight shape with four ports, the coupling between the second matching network and the first transformer is very low, thus ensuring that the first matching network and the first transformer do not interfere with each other.

[0024] In one possible implementation, the second matching network includes a third matching device and a fourth matching device; both the third and fourth matching devices are arranged in a figure-eight configuration with two ports. When the third matching device is arranged in a figure-eight configuration with two ports, the coupling between the third matching device and the first transformer T is very low due to the good anti-interference characteristics of the figure-eight configuration, thus preventing them from interfering with each other. Similarly, when the fourth matching device is arranged in a figure-eight configuration with two ports, the coupling between the fourth matching device and the first transformer is also very low due to the good anti-interference characteristics of the figure-eight configuration, preventing them from interfering with each other.

[0025] In one possible implementation, portions of the third matching device and the fourth matching device overlap. This reduces the area occupied by the second matching network.

[0026] In one possible implementation, the transmitting amplifier circuit is a power amplifier. When the transmitting amplifier circuit is a power amplifier, the receiving amplifier circuit is typically a low-noise amplifier.

[0027] In one possible implementation, the input ports of the transmitting amplifier circuit include a first differential transmitting input port and a second differential transmitting input port; the transmitting amplifier circuit is a power amplifier; the transceiver circuit further includes a ground terminal and a first voltage bias terminal; the power amplifier includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the first terminal of the first transistor is coupled to the first end of the first coil, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the gate of the first transistor is coupled to the first voltage bias terminal; the second terminal of the second transistor is coupled to the ground terminal, and the gate of the second transistor is coupled to the first differential transmitting input port; the first terminal of the third transistor is coupled to the second end of the first coil, the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, and the gate of the third transistor is coupled to the first voltage bias terminal; the second terminal of the fourth transistor is coupled to the ground terminal, and the gate of the fourth transistor is coupled to the second differential transmitting input port; wherein, the first terminal is the source, and the second terminal is the drain; or, the first terminal is the drain, and the second terminal is the source.

[0028] In one possible implementation, the input ports of the transmitting amplifier circuit include a first differential transmitting input port and a second differential transmitting input port; the transmitting amplifier circuit is a power amplifier; the transceiver circuit further includes a ground terminal and a first voltage bias terminal; the power amplifier includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the first terminal of the first transistor is coupled to the first end of the first coil, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the base of the first transistor is coupled to the first voltage bias terminal; the second terminal of the second transistor is coupled to the ground terminal, and the base of the second transistor is coupled to the first differential transmitting input port; the first terminal of the third transistor is coupled to the second end of the first coil, the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, and the base of the third transistor is coupled to the first voltage bias terminal; the second terminal of the fourth transistor is coupled to the ground terminal, and the base of the fourth transistor is coupled to the second differential transmitting input port; wherein, the first terminal is the collector, and the second terminal is the emitter; or, the first terminal is the emitter, and the second terminal is the collector.

[0029] In one possible implementation, the receiving amplifier circuit is a low-noise amplifier. When the receiving amplifier circuit is a low-noise amplifier, the transmitting amplifier circuit is typically a power amplifier.

[0030] In one possible implementation, the output ports of the receiving amplifier circuit include a first differential receiving output port and a second differential receiving output port; the transceiver circuit also includes a ground terminal and a second voltage bias terminal; the receiving amplifier circuit is a low-noise amplifier; the low-noise amplifier includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the fifth transistor is coupled to the ground terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the gate of the fifth transistor is coupled to the first end of the first coil; the second terminal of the sixth transistor is coupled to the first differential receiving output port, and the gate of the sixth transistor is coupled to the second voltage bias terminal; the first terminal of the seventh transistor is coupled to the ground terminal, the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor, and the gate of the seventh transistor is coupled to the second end of the first coil; the second terminal of the eighth transistor is coupled to the second differential receiving output port, and the gate of the eighth transistor is coupled to the second voltage bias terminal; wherein, the first terminal is the source, and the second terminal is the drain; or, the first terminal is the drain, and the second terminal is the source.

[0031] In one possible implementation, the output ports of the receiving amplifier circuit include a first differential receiving output port and a second differential receiving output port; the transceiver circuit also includes a ground terminal and a second voltage bias terminal; the receiving amplifier circuit is a low-noise amplifier; the low-noise amplifier includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the fifth transistor is coupled to the ground terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the base of the fifth transistor is coupled to the first end of the first coil; the second terminal of the sixth transistor is coupled to the first differential receiving output port, and the base of the sixth transistor is coupled to the second voltage bias terminal; the first terminal of the seventh transistor is coupled to the ground terminal, the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor, and the base of the seventh transistor is coupled to the second end of the first coil; the second terminal of the eighth transistor is coupled to the second differential receiving output port, and the base of the eighth transistor is coupled to the second voltage bias terminal; wherein, the first terminal is the collector, and the second terminal is the emitter; or, the first terminal is the emitter, and the second terminal is the collector.

[0032] In one possible implementation, a first end of the first coil is coupled to a voltage terminal, and a second end of the first coil is coupled to both the output port of the transmitting amplifier circuit and the input port of the receiving amplifier circuit. In this case, the transmitting amplifier circuit and the receiving amplifier circuit are used to transmit single-ended signals.

[0033] In one possible implementation, the transceiver circuit includes a first matching network coupled between a second end of a first coil and an input port of a receiving amplifier circuit. The first matching network can be, for example, a transmission line, inductor, resistor, capacitor, etc.

[0034] In one possible implementation, the first matching network is arranged in a figure-eight shape with two ports. When the first matching network is arranged in a figure-eight shape with two ports, the coupling between the first matching network and the first transformer is very low due to the good anti-interference characteristics of the figure-eight shape, thus ensuring that the first matching network and the first transformer do not interfere with each other.

[0035] In one possible implementation, the transceiver circuit includes a second matching network coupled between a second end of the first coil and the output port of the transmitting amplifier circuit. The second matching network can be, for example, a transmission line, inductor, capacitor, resistor, etc.

[0036] In one possible implementation, the second matching network is arranged in a figure-eight shape with two ports. When the second matching network is arranged in a figure-eight shape with two ports, the coupling between the second matching network and the first transformer is very low due to the good anti-interference characteristics of the figure-eight shape, thus ensuring that the second matching network and the first transformer do not interfere with each other.

[0037] In one possible implementation, the transceiver circuit further includes a ground terminal and a first voltage bias terminal; the power amplifier includes a first transistor and a second transistor. The first terminal of the first transistor is coupled to the second terminal of the first coil, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the gate of the first transistor is coupled to the first voltage bias terminal. The first terminal of the first transistor is coupled to the output port of the transmitting amplifier circuit. The second terminal of the second transistor is coupled to the ground terminal, and the gate of the second transistor is coupled to the input port of the transmitting amplifier circuit. The first terminal is the source, and the second terminal is the drain; or, the first terminal is the drain, and the second terminal is the source.

[0038] In one possible implementation, the transceiver circuit further includes a ground terminal and a first voltage bias terminal; the power amplifier includes a first transistor and a second transistor. The first terminal of the first transistor is coupled to the second terminal of the first coil, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the base of the first transistor is coupled to the first voltage bias terminal. The first terminal of the first transistor is coupled to the output port of the transmitting amplifier circuit. The second terminal of the second transistor is coupled to the ground terminal, and the base of the second transistor is coupled to the input port of the transmitting amplifier circuit. The first terminal is the collector, and the second terminal is the emitter; or, the first terminal is the emitter, and the second terminal is the collector.

[0039] In one possible implementation, the transceiver circuit further includes a ground terminal and a second voltage bias terminal; the low-noise amplifier includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the ground terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the gate of the fifth transistor is coupled to the second terminal of the first coil. The gate of the fifth transistor is coupled to the input port of the receiving amplifier circuit. The second terminal of the sixth transistor is coupled to the output port of the receiving amplifier circuit, and the gate of the sixth transistor is coupled to the second voltage bias terminal. The first terminal is the source, and the second terminal is the drain; or, the first terminal is the drain, and the second terminal is the source.

[0040] In one possible implementation, the transceiver circuit further includes a ground terminal and a second voltage bias terminal; the low-noise amplifier includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the ground terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the base of the fifth transistor is coupled to the second terminal of the first coil. The base of the fifth transistor is coupled to the input port of the receiving amplifier circuit. The second terminal of the sixth transistor is coupled to the output port of the receiving amplifier circuit, and the base of the sixth transistor is coupled to the second voltage bias terminal. The first terminal is the collector, and the second terminal is the emitter; or, the first terminal is the emitter, and the second terminal is the collector.

[0041] In one possible implementation, the transceiver circuitry is integrated on a chip, and the first and second coils are formed by metal wires within the chip. This allows the first and second coils to be fabricated simultaneously with the metal wires on the chip, thus simplifying the manufacturing process.

[0042] In one possible implementation, the metal wires include those located within the redistribution layer. This allows the first and second coils to be fabricated simultaneously with the metal wires in the redistribution layer.

[0043] In one possible implementation, the first and second coils in the transceiver circuit are integrated on a package substrate, and the transmitting and receiving amplifier circuits are integrated on a single chip; the first and second coils are formed by metal wires on the package substrate. This allows the first and second coils to be fabricated simultaneously with the metal wires in the package substrate, thereby simplifying the manufacturing process.

[0044] In one possible implementation, the transceiver circuit further includes one or more of a phase shifter, frequency synthesizer, mixer, attenuator, and digital-to-analog / analog-to-digital converter. The transceiver circuit may include RF front-end circuitry, bidirectional amplifier circuitry, etc.

[0045] Secondly, a communication system is provided, including a circuit board and the transceiver circuit provided in the first aspect; the transceiver circuit and the circuit board are coupled. Since the communication system has the same technical effects as the transceiver circuit provided in the first aspect, it can be referred to above, and will not be repeated here.

[0046] In one possible implementation, the communication system further includes a self-loopback calibration system; the self-loopback calibration system includes a transceiver circuit. When in operation, the self-loopback calibration system receives a signal from the input port of the transmitting amplifier circuit of the transceiver circuit and detects the signal output from the output port of the receiving amplifier circuit of the transceiver circuit. It can be applied to carrier wave and harmonic leakage calibration, nonlinear calibration, DPD calibration, etc.

[0047] In one possible implementation, the communication system further includes a cable coupled to the input / output ports of the transceiver circuit. In this case, the communication system is a wired communication system.

[0048] Thirdly, an electronic device is provided, including a processor and the communication system provided in the second aspect above; the processor and the communication system are coupled. Since the electronic device has the same technical effects as the transceiver circuit provided in the first aspect above, it can be referred to the above, and will not be repeated here. Attached Figure Description

[0049] Figure 1 A schematic diagram of the structure of an electronic device provided for an embodiment of this application;

[0050] Figure 2 A schematic diagram of the structure of a wired communication system or a wireless communication system provided for embodiments of this application;

[0051] Figure 3 A schematic diagram of a transceiver circuit provided for an embodiment of this application;

[0052] Figure 4a A schematic diagram of a transceiver circuit is provided for another embodiment of this application;

[0053] Figure 4b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0054] Figure 4c A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0055] Figure 5a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0056] Figure 5b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0057] Figure 5c A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0058] Figure 6 A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0059] Figure 7a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0060] Figure 7b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0061] Figure 7c A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0062] Figure 7d A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0063] Figure 8a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0064] Figure 8b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0065] Figure 9a A schematic diagram of the structure of a power amplifier PA provided for an embodiment of this application;

[0066] Figure 9b A schematic diagram of the structure of a power amplifier PA provided for another embodiment of this application;

[0067] Figure 9c A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0068] Figure 9d A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0069] Figure 9e A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0070] Figure 9f A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0071] Figure 9g A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0072] Figure 9h A schematic diagram of the structure of a power amplifier PA provided in another embodiment of this application;

[0073] Figure 10a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0074] Figure 10b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0075] Figure 11a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0076] Figure 11b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0077] Figure 12 A schematic diagram of the structure of a first transformer, resonant capacitor C1, and resonant capacitor C2 provided for embodiments of this application;

[0078] Figure 13a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0079] Figure 13b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0080] Figure 13c A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0081] Figure 13d A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0082] Figure 13e A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0083] Figure 14a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0084] Figure 14b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0085] Figure 14c A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0086] Figure 14d A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0087] Figure 14e A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0088] Figure 15 A schematic diagram of the structure of a first matching network provided for an embodiment of this application;

[0089] Figure 16a A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0090] Figure 16b A schematic diagram of a transceiver circuit provided for another embodiment of this application;

[0091] Figure 17 This is a schematic diagram of a transceiver circuit based on a phased array architecture, provided for an embodiment of this application.

[0092] Reference numerals: 10-Transceiver circuit; 20-Circuit board; 30-RF front-end circuit; 100-Electronic device; 101-Transmitter amplifier circuit; 102-Receiver amplifier circuit; 103-Antenna; 104-First matching network; 105-Second matching network; 110-Processor; 120-External memory interface; 121-Internal memory; 130-Universal Serial Bus interface; 140-Charging management module; 141-Power management module; 142-Battery; 150-Wired communication system; 160-Wireless communication system; 170-Audio module; 180-Sensor module; 190-Button; 191-Motor; 192-Indicator; 193-Camera; 194-Display screen; 195-SIM card interface; 1041-First matching device; 1042-Second matching device; 1051-Third matching device; 1052-Fourth matching device. Detailed Implementation

[0093] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0094] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0095] In the embodiments of this application, unless otherwise expressly specified and limited, the term "coupling" can refer to direct coupling or indirect coupling through an intermediate medium.

[0096] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0097] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0098] This application provides an electronic device, which can be any electronic device with transceiver functions. Examples of such devices include mobile phones, tablets, personal digital assistants (PDAs), televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0099] Figure 1 This is a schematic diagram of the structure of an electronic device provided as an example of an embodiment of this application. Figure 1 As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, a wired communication system 150, a wireless communication system 160, an audio module 170, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0100] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0101] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors. The controller can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0102] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0103] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0104] USB interface 130 is an interface that conforms to the USB standard specification, specifically it can be a Mini USB interface, Micro USB interface, USB Type C interface, etc.

[0105] The charging management module 140 is used to receive charging input from the charger. The charger can be a wireless charger or a wired charger.

[0106] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication system 160. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance).

[0107] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 194 and the application processor.

[0108] The display screen 194 is used to display images, videos, etc. In some embodiments, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.

[0109] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0110] The ISP is used to process the data fed back by the camera 193.

[0111] Camera 193 is used to capture still images or videos.

[0112] Video codecs are used to compress or decompress digital video.

[0113] The external storage interface 120 can be used to connect an external storage card, such as a Micro SD card, to expand the storage capacity of the electronic device 100.

[0114] Internal memory 121 can be used to store computer executable program code, which includes instructions.

[0115] Electronic device 100 can implement audio functions through audio module 170, speaker, receiver, microphone, headphone jack, and application processor.

[0116] Audio module 170 is used to convert digital audio information into analog audio signal output, and also to convert analog audio input into digital audio signal. The speaker is used to convert audio electrical signals into sound signals. The receiver is used to convert audio electrical signals into sound signals. The microphone is used to convert sound signals into electrical signals. The headphone jack is used to connect wired headphones.

[0117] The sensor module 180 may include an image sensor, a pressure sensor, a magnetic sensor, a distance sensor, etc. The image sensor may be, for example, a contact image sensor (CIS).

[0118] Button 190 includes the power button, volume buttons, etc.

[0119] Motor 191 can generate vibration alerts.

[0120] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0121] The SIM card interface 195 is used to connect the SIM card.

[0122] The communication function of electronic device 100 can be realized through wired communication system 150, wireless communication system 160, modem processor and baseband processor, etc.

[0123] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through audio devices (not limited to speakers, receivers, etc.) or displays images or videos through the display screen 194.

[0124] The wireless communication system 160 can provide solutions for wireless communication applications on electronic devices 100, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), and other wireless communication technologies.

[0125] This application provides a communication system, which can be a wired communication system 150 or a wireless communication system 160. The wired communication system 150 or the wireless communication system 160 provided in this application embodiment can be applied to the above-described electronic device 100.

[0126] Among them, such as Figure 2 As shown, the above communication system includes a circuit board 20 and a transceiver circuit (also known as a TX / RX (transmit / receive) bidirectional switch circuit) 10, with the transceiver circuit 10 and the circuit board 20 coupled together.

[0127] Here, circuit board 20 can be, for example, a printed circuit board (PCB).

[0128] In the case where the communication system provided in the embodiments of this application is a wired communication system 150, the communication system also includes a cable, and in some examples, the cable is coupled to the input / output port of the transceiver circuit 10.

[0129] In the case where the communication system provided in the embodiments of this application is a wireless communication system 160, in some examples, the transceiver circuit 10 described above further includes an antenna, which is coupled to the input and output ports of the transceiver circuit 10.

[0130] It should be noted that the transceiver circuit 10 provided in this application embodiment can operate in a single frequency band or in multiple frequency bands.

[0131] To reduce the area and complexity of the communication system in the electronic device 100, TR combining is often used, which can be implemented by the transceiver circuit 10. The following provides three exemplary implementations to illustrate the structure of the transceiver circuit 10.

[0132] In the first alternative implementation, such as Figure 3 As shown, the TR combiner (or transceiver circuit 10) can be implemented by a bidirectional amplifier, which includes a transmit input port TX_IN, a receive output port RX_OUT, and input / output ports, which can be coupled to an antenna, for example.

[0133] For example, Figure 3 The bidirectional amplifier shown can be implemented using the following two structures: First, the structure of the bidirectional amplifier is as follows... Figure 4a and Figure 4bAs shown, it includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first inductor L1, a second inductor L2, a third inductor L3, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a voltage terminal VDD_PA, a voltage terminal VDD_LNA, a control terminal VB1, a control terminal VB2, and a control terminal VB3. The first switch S1 is coupled between the voltage terminal VDD_PA and the first inductor L1. The second switch S2 is coupled between the first inductor L1 and the ground terminal GND. One end of the first inductor L1 is coupled to the first terminal of the first transistor M1, and the other end of the first inductor L1 is coupled to the first terminal of the second transistor M2. The second terminal of the first transistor M1 is coupled to the first terminal of the third transistor M3. The second terminal of the second transistor M2 is coupled to the first terminal of the fourth transistor M4. The gate of the first transistor M1 is coupled to both control terminals VB1 and VB2. The gate of the second transistor M2 is coupled to both control terminals VB1 and VB2. The gates of the third transistor M3 and the fourth transistor M4 are coupled to the emitter input port TX_IN of the emitter amplifier circuit (e.g., the input port PA_IN of the power amplifier) ​​or to the control terminal VB3. The third switch S3 is coupled between the second terminal of the third transistor S3 and the ground terminal GND. The fourth switch S4... The fifth switch S5 is coupled between the second terminal of the fourth transistor S4 and the ground terminal GND. The fifth switch S5 is coupled between the second terminal of the third transistor M3 and the second inductor L2. The second inductor L2 is coupled between the fifth switch S5 and the voltage terminal VDD_LNA. The sixth switch S6 is coupled between the second terminal of the fourth transistor M4 and the third inductor L3. The third inductor L3 is coupled between the sixth switch S6 and the voltage terminal VDD_LNA. The transmit output port TX_OUT of the transmit amplifier circuit (e.g., the output port PA_OUT of the power amplifier) ​​and the receive input port RX_IN of the receive amplifier circuit (e.g., the input port LNA_IN of the low noise amplifier) ​​are coupled between the first terminal of the first transistor M1 and the first terminal of the second transistor M2. The receive output port RX_OUT of the receive amplifier circuit (e.g., the output port LNA_OUT of the low noise amplifier) ​​is coupled between the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4.

[0134] The bidirectional function of a bidirectional amplifier can be achieved by switching between cascode (common source, common gate) and CG (common gate) structures. In transmit mode, the bidirectional amplifier achieves transmit functionality through the cascode structure. At this time, as... Figure 4a As shown, the first switch S1 is on, the second switch S2 is off, the third switch S3 is on, the fourth switch S4 is on, the fifth switch S5 is off, and the sixth switch S6 is off. The control terminal VB1 controls the first transistor M1 and the second transistor M2 to be on.

[0135] In receive mode, the bidirectional amplifier achieves its receiving function through a common-gate structure. At this time, as... Figure 4b As shown, the first switch S1 is open, the second switch S2 is on, the third switch S3 is open, the fourth switch S4 is open, the fifth switch S5 is on, the sixth switch S6 is on, the control terminal VB2 controls the first transistor M1 and the second transistor M2 to be on, and the control terminal VB3 controls the third transistor M3 and the fourth transistor M4 to be on.

[0136] Taking a bidirectional amplifier in transmit mode as an example, such as Figure 4c As shown, the on-resistance Ron of the first switch S1, the third switch S3, and the fourth switch S4 consumes power and increases insertion loss, thereby reducing the output power and efficiency of the transmit link. Similarly, in receive mode, the on-resistance Ron of the second switch S2, the fifth switch S5, and the sixth switch S6 consumes power and increases insertion loss, thereby increasing the noise of the receive link. This reduces the communication rate and degrades performance.

[0137] Furthermore, since the switching between cascode and CG structures usually requires switching the power ground, this introduces additional losses and increases power consumption.

[0138] The second type, the structure of the bidirectional amplifier is as follows: Figure 5a As shown, Figure 5aThis is a bidirectional amplifier based on a neutralizing capacitor architecture. The bidirectional amplifier includes a transmitting amplifier circuit 101 and a receiving amplifier circuit 102. The transmitting amplifier circuit 101 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first terminal of the first transistor M1 is coupled to the second terminals of the second transistor M2 and the third transistor M3. The second terminal of the first transistor M1 is coupled to the ground terminal GND. The gate of the first transistor M1 is coupled to the control terminal VGTX. The first terminals of the second transistor M2 and the third transistor M3 are coupled to the transmitting output port TX_OUT of the transmitting amplifier circuit 101 and the receiving input port RX_IN of the receiving amplifier circuit 102 (the transmitting output port TX_OUT and the receiving input port RX_IN are combined into one port). The gates of the second transistor M2 and the third transistor M3 are coupled to the transmitting input port TX_IN of the transmitting amplifier circuit 101. The receiving amplifier circuit 102 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first terminal of the fourth transistor M4 is coupled to the second terminals of the fifth transistor M5 and the sixth transistor M6. The second terminal of the fourth transistor M4 is coupled to the ground terminal GND. The gate of the fourth transistor M4 is coupled to the control terminal VGRX. The first terminals of the fifth transistor M5 and the sixth transistor M6 are coupled to the output port RX_OUT of the receiving amplifier circuit 102. The gates of the fifth transistor M5 and the sixth transistor M6 are coupled to the transmit output port TX_OUT of the transmit amplifier circuit 101 and the receive input port RX_IN of the receiving amplifier circuit 102.

[0139] In transmit mode, the bidirectional amplifier, such as Figure 5b As shown, the receiving amplifier circuit 102 is turned off. At this time, the parasitic capacitance Cgd of the receiving amplifier circuit 102 becomes the neutralizing capacitance of the transmitting amplifier circuit 101, allowing the transmitting amplifier circuit 101 to operate normally. In the receiving mode, as... Figure 5c As shown, the transmitting amplifier circuit 101 is turned off. At this time, the parasitic capacitance Cgd of the transmitting amplifier circuit 101 will become the neutralizing capacitance of the receiving amplifier circuit 102, and the receiving amplifier circuit 102 can work normally.

[0140] Taking the launch operation mode as an example, such as Figure 5b As shown, the receiving amplifier circuit 102 is turned off, due to the parasitic resistance R of the off-state transistor. para and parasitic capacitance ( Figure 5b (Not shown) This will cause additional losses, increasing insertion loss and thus reducing the output power and efficiency of the transmit link. Similarly, in receive mode, it will also increase insertion loss, thereby increasing the noise of the receive link. This will reduce the communication rate and degrade performance.

[0141] Since the receiving amplifier circuit primarily optimizes for noise, while the transmitting amplifier circuit mainly optimizes for power and efficiency, the optimal impedances of the receiving and transmitting amplifier circuits differ significantly. Furthermore, bidirectional amplifiers share the same matching network, thus typically only achieving impedance matching at a single level, making it difficult to simultaneously accommodate both the receiving and transmitting amplifier circuits.

[0142] In a second optional implementation, the TR combiner (or transceiver circuit 10) can switch between the receive link and the transmit link using series and parallel switches. For example... Figure 6 As shown, the power amplifier (PA) is coupled to the antenna through the first switch S1, and the power amplifier PA is also coupled to the ground terminal GND through the second switch S2. The low noise amplifier (LNA) is coupled to the antenna through the third switch S3, and the low noise amplifier LNA is also coupled to the ground terminal GND through the fourth switch S4.

[0143] In transmit mode, switch S1 is on, switch S2 is off, switch S3 is off, and switch S4 is on. In receive mode, switch S1 is off, switch S2 is on, switch S3 is on, and switch S4 is off. Taking transmit mode as an example, the on-resistance Ron of switch S1, and the parasitic capacitance Coff and parasitic resistance Roff of switch S4 (off state) introduce significant insertion loss. In receive mode, the on-resistance Ron of switch S3, and the parasitic capacitance Coff and parasitic resistance Roff of switch S2 (off state) introduce significant insertion loss.

[0144] Therefore, using series-parallel switches to switch between the receive and transmit links introduces significant insertion losses. Furthermore, in high-power scenarios, the reliability of the switches becomes a serious issue.

[0145] In a third alternative implementation, the TR combiner (or transceiver circuit 10) can be implemented using a passive network combiner. The structure of the passive network combiner can be exemplarily described as follows: Figure 7a , Figure 7b , Figure 7c and Figure 7d The structure shown.

[0146] like Figure 7a As shown, the passive network circuit includes a transformer T, an inductor L, and a switch S. The first coil of the transformer T is coupled to the voltage terminal V and the power amplifier PA, respectively. The second coil of the transformer T is coupled to the antenna and the ground terminal GND, respectively. The first end of the inductor L is coupled to the antenna, and the second end of the inductor L is coupled to the low noise amplifier LNA. The switch S is coupled between the second end of the inductor L and the ground terminal GND.

[0147] like Figure 7b As shown, the passive network combiner includes transmission line 1, transmission line 2, first switch S1 and second switch S2. Transmission line 1 is coupled between the antenna and the power amplifier PA. The first switch S1 is coupled between the power amplifier PA and the ground terminal GND. Transmission line 2 is coupled between the antenna and the low noise amplifier LNA. The second switch S2 is coupled between the low noise amplifier LNA and the ground terminal GND.

[0148] like Figure 7c As shown, the passive network combiner includes a transformer T and a switch S. The first coil of the transformer T is coupled to the voltage terminal V, the power amplifier PA, and the ground terminal GND. The second coil of the transformer T is coupled to the antenna, the ground terminal GND, and the low noise amplifier LNA. The switch S is coupled between the low noise amplifier LNA and the ground terminal GND.

[0149] like Figure 7d As shown, the passive network combiner includes a transformer T and a switch S. The first coil of the transformer T is coupled to the voltage terminal V and the power amplifier PA, respectively. The second coil of the transformer T is coupled to the antenna, the ground terminal GND, and the low noise amplifier LNA, respectively. The switch S is coupled between the low noise amplifier LNA and the ground terminal GND.

[0150] for Figure 7a In the structure shown, the output shut-off impedance of the transmit (TX) link is converted to low impedance due to the effect of transformer T in the receive (RX) mode, which increases the insertion loss in RX mode.

[0151] for Figure 7b In the structure shown, the power amplifier PA and the low-noise amplifier LNA each have their own matching networks. Therefore, the final insertion loss is the sum of the matching network insertion loss and the switching insertion loss based on transmission line 1 and transmission line 2, so the insertion loss is relatively large.

[0152] for Figure 7c In the structure shown, the shut-off impedance of the power amplifier (PA) and the low-noise amplifier (LNA) is achieved by switch S. The on-resistance of switch S appears directly in the signal path, resulting in relatively large insertion loss.

[0153] for Figure 7d The structure shown has a large insertion loss because the coils coupled to the power amplifier PA and the low-noise amplifier LNA in the transformer T will affect each other, and the transformer T causes the on-resistance of the switch S to be lower than the output impedance.

[0154] Based on the above, Figure 7a , Figure 7b , Figure 7c and Figure 7d The passive network structures provided generally result in significant insertion loss, typically around 2dB. This drastically reduces the power and efficiency of the power amplifier (PA) and increases the noise figure of the low-noise amplifier (LNA), thus lowering the communication speed. Furthermore, the larger area of ​​passive network structures increases the manufacturing cost of the chip.

[0155] To address the issue of high insertion loss in the transceiver circuit 10 (i.e., the TR combining structure) described above, this application also provides a transceiver circuit 10. Several specific embodiments are provided below to illustrate the structure of the transceiver circuit 10.

[0156] Example 1

[0157] like Figure 8a As shown, Embodiment 1 provides a transceiver circuit 10, which includes a first transformer T, a receiving amplifier circuit 102, a transmitting amplifier circuit 101, a voltage terminal VB, and an input / output port RF_IO.

[0158] The first transformer T includes a first coil T1 and a second coil T2 that are coupled to each other. The first coil T1 is coupled to the voltage terminal VB, the input port RX_IN of the receiving amplifier circuit 102, and the output port TX_OUT of the transmitting amplifier circuit 101, respectively. The second coil T2 is coupled to the input / output port RF_IO.

[0159] It should be noted that the voltage terminal VB mentioned in the embodiments of this application can be either a power supply terminal or a ground terminal.

[0160] The following describes the operation of the transceiver circuit 10. In the transmit mode, the transmit amplifier circuit 101 is in operation and the receive amplifier circuit 102 is in operation. The transmit amplifier circuit 101 transmits the received signal through the input / output port RF_IO. In the receive mode, the receive amplifier circuit 102 is in operation and the transmit amplifier circuit 101 is in operation. The receive amplifier circuit 102 transmits the signal received from the input / output port RF_IO to other circuits.

[0161] Here, the first coil T1 can be the primary coil and the second coil T2 can be the secondary coil; or the first coil T1 can be the secondary coil and the second coil T2 can be the primary coil.

[0162] It should be noted that the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 can be used to transmit differential signals or single-ended signals.

[0163] When the transmitting amplifier circuit 101 is used to transmit differential signals, such as Figure 8a As shown, the output port TX_OUT of the transmitting amplifier circuit 101 includes a first differential transmitting output port TX_OUT1 and a second differential transmitting output port TX_OUT2; the input port RX_IN of the receiving amplifier circuit 102 includes a first differential receiving input port RX_IN1 and a second differential receiving input port RX_IN2. The first terminal A of the first coil T1 is coupled to the first differential transmitting output port TX_OUT1 of the transmitting amplifier circuit 101, and the second terminal B of the first coil T1 is coupled to the second differential output port TX_OUT2 of the transmitting amplifier circuit 101; the first terminal A of the first coil T1 is coupled to the first differential receiving input port RX_IN1 of the receiving amplifier circuit 102, and the second terminal B of the first coil T1 is coupled to the second differential receiving input port RX_IN2 of the receiving amplifier circuit 102.

[0164] It is understood that the transmitter amplifier circuit 101 also includes an input port TX_IN, which can be coupled to other circuits such as the transmitter circuit. In some examples, such as Figure 8a As shown, the input port TX_IN of the transmitting amplifier circuit 102 can be coupled to other circuits through an input matching network. This input matching network can be, for example, a resistor, inductor, capacitor, transformer, or transmission line.

[0165] Based on this, when the transmitting amplifier circuit 101 is used to transmit differential signals, the input port TX_IN of the transmitting amplifier circuit 101 is a differential port. In this case, the input port TX_IN of the transmitting amplifier circuit 101 includes a first differential transmitting input port TX_IN1 and a second differential transmitting input port TX_IN2.

[0166] The receiver amplifier circuit 102 also includes an output port RX_OUT, which can be coupled to other circuits, such as a receiver circuit. In some examples, such as Figure 8a As shown, the output port RX_OUT of the receiving amplifier circuit 102 can be coupled to other circuits through an output matching network. This output matching network can be, for example, a resistor, inductor, capacitor, transformer, or transmission line.

[0167] It is understood that when the receiving amplifier circuit 102 is used to transmit differential signals, the output port RX_OUT of the receiving amplifier circuit 102 is a differential port. In this case, the output port RX_OUT of the receiving amplifier circuit 102 includes a first differential receiving output port RX_OUT1 and a second differential receiving output port RX_OUT2.

[0168] For example, in different application scenarios, the above-mentioned transmitter amplifier circuit 101 can be a power amplifier, a transmitter driver amplifier, or a mixer.

[0169] When the transmitting amplifier circuit 101 is a power amplifier and is used to transmit differential signals, the input port TX_IN of the transmitting amplifier circuit 101 includes a first differential transmitting input port TX_IN1 and a second differential transmitting input port TX_IN2. In some examples, the transceiver circuit 10 also includes a ground terminal GND and a first voltage bias terminal Vbias1, such as... Figure 8b As shown, the power amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

[0170] The first terminal of the first transistor M1 is coupled to the first terminal A of the first coil T1, the second terminal of the first transistor M1 is coupled to the first terminal of the second transistor M2, and the third terminal of the first transistor M1 is coupled to the first voltage bias terminal Vbias1. The first terminal of the first transistor M1 is also coupled to the first differential emitter output port TX_OUT1.

[0171] The second terminal of the second transistor M2 is coupled to the ground terminal GND, and the third terminal of the second transistor M2 is coupled to the first differential emitter input port TX_IN1.

[0172] The first terminal of the third transistor M3 is coupled to the second terminal B of the first coil T1. The second terminal of the third transistor T3 is coupled to the first terminal of the fourth transistor M4. The third terminal of the third transistor M3 is coupled to the first voltage bias terminal Vbias1. The first terminal of the third transistor M3 is also coupled to the second differential output terminal TX_OUT2.

[0173] The second terminal of the fourth transistor M4 is coupled to the ground terminal GND, and the third terminal of the fourth transistor M4 is coupled to the second differential emitter input port TX_IN2.

[0174] In the embodiments of this application, the grounding terminal GND can be, for example, AC ground.

[0175] It should be noted that the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 mentioned above can be MOS transistors (MOS transistor is short for MOSFET (metal-oxide-semiconductor field-effect transistor)); or they can be BTJ (bipolar junction transistor).

[0176] When the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are MOS transistors, the third terminal is called the gate. In this case, the first terminal can be the source and the second terminal can be the drain; or the first terminal can be the drain and the second terminal can be the source.

[0177] When the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are BTJ transistors, the third terminal is called the base. In this case, the first terminal can be the collector and the second terminal can be the emitter; or the first terminal can be the emitter and the second terminal can be the collector.

[0178] Based on this, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the embodiments of this application can be either P-type transistors or N-type transistors. The accompanying drawings of this application illustrate an example where the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type transistors.

[0179] It is understandable that the structure of a power amplifier (PA) includes, but is not limited to, the following: Figure 8b The structure shown is illustrated below. Several other power amplifier structures are provided as examples below.

[0180] The first type, such as Figure 9a As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. Figure 9a The provided power amplifier PA is a power amplifier with a common source and common gate structure. Figure 9a The provided power amplifier and Figure 8b The difference between the power amplifiers in the two systems is that... Figure 9a In the provided power amplifier, the third terminals of both the first transistor M1 and the third transistor M3 are coupled to AC (alternating current) GND. The other connections of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be referenced above. Figure 8b The descriptions of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are not repeated here.

[0181] The second type, such as Figure 9b As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first inductor L1, and a second inductor L2. Figure 9b The provided power amplifier PA is a common-source, common-gate power amplifier with active negative feedback. Figure 9b The provided power amplifier and Figure 9a The difference in the power amplifiers offered is that... Figure 9b In the provided power amplifier, the second terminal of the second transistor M2 is coupled to ground GND through the first inductor L1, and the second terminal of the fourth transistor M4 is coupled to ground GND through the second inductor L2. Other connections between the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be found in [reference needed]. Figure 9a The relevant descriptions in the document will not be repeated here.

[0182] The third type, such as Figure 9c As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. Figure 9c The provided power amplifier PA is a power amplifier with a stack structure. Figure 9c The provided power amplifier and Figure 8b The difference between the power amplifiers in the two systems is that... Figure 9c In the provided power amplifier, the third terminal of the first transistor M1 is coupled to ground GND through the first capacitor C1, and the third terminal of the third transistor M3 is coupled to ground GND through the second capacitor C2. Other connections between the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be referenced above. Figure 8b The descriptions of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are not repeated here.

[0183] The fourth type, such as Figure 9d As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first inductor L1, and a second inductor L2. Figure 9d The provided power amplifier PA is a stacked power amplifier with active negative feedback. Figure 9d The provided power amplifier and Figure 9c The difference in the power amplifiers offered is that... Figure 9d In the provided power amplifier PA, the second terminal of the second transistor M2 is coupled to the ground terminal through the first inductor L1, and the second terminal of the fourth transistor M4 is coupled to the ground terminal through the second inductor L2. Other connections between the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be found in [reference needed]. Figure 9c The relevant descriptions in the document will not be repeated here.

[0184] The fifth type, such as Figure 9e As shown, the power amplifier PA includes a first transistor M1 and a second transistor M2. Figure 9e The provided power amplifier PA is a common source amplifier (CS). Figure 9e In the provided power amplifier PA, the first terminal of the first transistor M1 is coupled to the first terminal A of the first coil T1, the second terminal of the first transistor M1 is coupled to the ground terminal GND, and the third terminal of the first transistor M1 is coupled to the first differential emitter input port TX_IN1. The first terminal of the second transistor M2 is coupled to the second terminal B of the first coil T1, the second terminal of the second transistor M2 is coupled to the ground terminal GND, and the third terminal of the second transistor M2 is coupled to the second differential emitter input port TX_IN2.

[0185] The sixth type, such as Figure 9f As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a first inductor L1, and a second inductor L2. Figure 9f The provided power amplifier PA is a common-source power amplifier with active negative feedback. Figure 9f The provided power amplifier PA and Figure 9e The difference between the supplied power amplifiers (PAs) is that... Figure 9f In the provided power amplifier PA, the second terminal of the first transistor M1 is coupled to ground GND through the first inductor L1, and the second terminal of the second transistor M2 is coupled to ground GND through the second inductor L2. Other connection relationships between the first transistor M1 and the second transistor M2 can be found in [reference needed]. Figure 9e The relevant descriptions in the document will not be repeated here.

[0186] The seventh type, such as Figure 9g As shown, the power amplifier PA includes a first transistor M1 and a second transistor M2. Figure 9g The provided power amplifier PA is a power amplifier with a common gate structure. Figure 9d In the provided power amplifier PA, the first terminal of the first transistor M1 is coupled to the first terminal A of the first coil T1, the second terminal of the first transistor M1 is coupled to the first differential emitter input port TX_IN1, and the third terminal of the first transistor M1 is coupled to the ground terminal GND. The first terminal of the second transistor M2 is coupled to the second terminal B of the first coil T1, the second terminal of the second transistor M2 is coupled to the second differential emitter input port TX_IN2, and the third terminal of the second transistor M2 is coupled to the ground terminal GND.

[0187] The eighth type, such as Figure 9h As shown, the power amplifier PA includes a first transistor M1, a second transistor M2, a fourth transformer, and a fifth transformer. Figure 9h The provided power amplifier PA is a common-gate power amplifier with gain multiplication. Figure 9h The provided power amplifier PA and Figure 9g The difference in the power amplifiers offered is that... Figure 9hIn the provided power amplifier, the first transistor M1 is coupled to the ground terminal GND via a fourth transformer. Specifically, the first coil T1 of the fourth transformer is coupled between the third terminal of the first transistor M1 and the ground terminal GND, and the second coil T2 of the fourth transformer is coupled between the second terminal of the first transistor M1 and the ground terminal GND. Similarly, the second transistor M2 in the power amplifier is coupled to the ground terminal GND via a fifth transformer. Specifically, the first coil T1 of the fifth transformer is coupled between the third terminal of the second transistor M2 and the ground terminal GND, and the second coil T2 of the fifth transformer is coupled between the second terminal of the second transistor M2 and the ground terminal GND. Other connection relationships between the first transistor M1 and the second transistor M2 can be found in [reference needed]. Figure 9g The relevant descriptions in the document will not be repeated here.

[0188] It should be noted that the above Figures 9a to 9h The types of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be referenced above and will not be repeated here. Furthermore, the above... Figures 9a to 9h The specific terminals of a transistor, including the first, second, and third terminals, depend on the type of transistor and can be found in the description above; they will not be repeated here.

[0189] For example, in different application scenarios, the above-mentioned receiver amplifier circuit 102 can be a low-noise amplifier, a receiver driver amplifier, or a mixer.

[0190] It is understandable that when the transmitting amplifier circuit 101 is a power amplifier, the receiving amplifier circuit 102 is typically a low-noise amplifier. When the transmitting amplifier circuit 101 is a transmitting drive amplifier, the receiving amplifier circuit 102 is typically a receiving drive amplifier. When the transmitting amplifier circuit 101 is a mixer, the receiving amplifier circuit 102 is typically a mixer.

[0191] When the receiving amplifier circuit 102 is a low-noise amplifier (LNA) and is used to transmit differential signals, the output port RX_OUT of the receiving amplifier circuit 102 includes a first differential receiving output port RX_OUT1 and a second differential receiving output port RX_OUT2. In some examples, the transceiver circuit 10 also includes a ground terminal GND and a second voltage bias terminal Vbias2, such as... Figure 8b As shown, the low-noise amplifier includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

[0192] The first terminal of the fifth transistor M5 is coupled to ground (GND), the second terminal of the fifth transistor M5 is coupled to the first terminal of the sixth transistor M6, and the third terminal of the fifth transistor M5 is coupled to the first terminal A of the first coil T1. The third terminal of the fifth transistor M5 is also coupled to the first differential receiver input port RX_IN1.

[0193] The second terminal of the sixth transistor M6 is coupled to the first differential receive output port RX_OUT1, and the third terminal of the sixth transistor M6 is coupled to the second voltage bias terminal Vbias2.

[0194] The first terminal of the seventh transistor M7 is coupled to ground GND, the second terminal of the seventh transistor M7 is coupled to the first terminal of the eighth transistor M8, and the third terminal of the seventh transistor M7 is coupled to the second terminal B of the first coil T1. The third terminal of the seventh transistor M7 is coupled to the second differential receiver input port RX_IN2.

[0195] The second terminal of the eighth transistor M8 is coupled to the second differential receive output port RX_OUT2, and the third terminal of the eighth transistor M8 is coupled to the second voltage bias terminal Vbias2.

[0196] It should be noted that the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 mentioned above can be MOSFETs or BTJ transistors.

[0197] When the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are MOS transistors, the third terminal is called the gate. In this case, the first terminal can be the source and the second terminal can be the drain; or the first terminal can be the drain and the second terminal can be the source.

[0198] When the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are BTJ transistors, the third terminal is called the base. In this case, the first terminal can be the collector and the second terminal can be the emitter; or the first terminal can be the emitter and the second terminal can be the collector.

[0199] Based on this, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be either P-type transistors or N-type transistors. The accompanying drawings in this application illustrate an example where the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type transistors.

[0200] It is understandable that the structure of a low-noise amplifier (LNA) includes, but is not limited to, […]. Figure 8b The structure shown is an example. The structure of a low-noise amplifier (LNA) can also be... Figure 9a , Figure 9b , Figure 9c , Figure 9d, Figure 9e , Figure 9f , Figure 9g and Figure 9h The structure shown is different in that the first differential transmit input port TX_IN1 is replaced with the first differential receive input port RX_IN1, the second differential transmit input port coupled TX_IN2 is replaced with the second differential receive input port RX_IN2, the first differential transmit output port TX_OUT1 is replaced with the first differential receive output port RX_OUT1, and the second differential output port TX_OUT2 is replaced with the second differential receive output port RX_OUT2.

[0201] When the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit single-ended signals, such as Figure 10a As shown, the first terminal A of the first coil T1 is coupled to the voltage terminal VB, and the second terminal B of the first coil T1 is coupled to the output port TX_OUT of the transmitting amplifier circuit 101 and the input port RX_IN of the receiving amplifier circuit 102, respectively.

[0202] It is understood that the transmitter amplifier circuit 101 also includes an input port TX_IN, which can be coupled to other circuits such as the transmitter circuit. In some examples, such as Figure 10a As shown, the input port TX_IN of the transmitting amplifier circuit 101 can be coupled to other circuits through an input matching network. When the transmitting amplifier circuit 101 is used to transmit a single-ended signal, the input port TX_IN of the transmitting amplifier circuit 101 is also a single-ended port.

[0203] The receiver amplifier circuit 102 also includes an output port RX_OUT, which can be coupled to other circuits, such as a receiver circuit. In some examples, such as Figure 10a As shown, the output port RX_OUT of the receiving amplifier circuit 102 can be coupled to other circuits through an output matching network. When the receiving amplifier circuit 102 is used to transmit a single-ended signal, the output port RX_OUT of the receiving amplifier circuit 102 is also a single-ended port.

[0204] The type of the transmitting amplifier circuit 101 can be referred to above, and will not be repeated here.

[0205] Taking the transmitting amplifier circuit 101 as a power amplifier PA as an example, when the transmitting amplifier circuit 101 is used to transmit single-ended signals, in some examples, the above-mentioned transceiver circuit 10 also includes a ground terminal GND and a first voltage bias terminal Vbias1; such as Figure 10b As shown, the power amplifier includes a first transistor M1 and a second transistor M2.

[0206] The first terminal of the first transistor M1 is coupled to the second terminal B of the first coil T1, the second terminal of the first transistor T1 is coupled to the first terminal of the second transistor M2, and the third terminal of the first transistor M1 is coupled to the first voltage bias terminal Vbias1. The first terminal of the first transistor M1 is coupled to the output port TX_OUT of the emitter amplifier circuit 101.

[0207] The second terminal of the second transistor M2 is coupled to the ground terminal GND, and the third terminal of the second transistor M2 is coupled to the input port TX_IN of the emitter amplifier circuit 101.

[0208] In addition, the type of receiving amplifier circuit 102 can be referred to the above, and will not be repeated here.

[0209] Taking the receiving amplifier circuit 102 as a low-noise amplifier (LNA) as an example, when the receiving amplifier circuit 102 is used to transmit single-ended signals, in some examples, the above-mentioned transceiver circuit 10 also includes a ground terminal GND and a second voltage bias terminal Vbias2; such as Figure 10b As shown, the low-noise amplifier (LNA) includes a fifth transistor M5 and a sixth transistor M6.

[0210] The first terminal of the fifth transistor M5 is coupled to ground GND, the second terminal of the fifth transistor M5 is coupled to the first terminal of the sixth transistor M6, and the third terminal of the fifth transistor M5 is coupled to the second terminal B of the first coil T1. The third terminal of the fifth transistor M5 is coupled to the input port RX_IN of the receiving amplifier circuit 102.

[0211] In some examples, the first terminal of the fifth transistor M5 is coupled to the ground terminal GND through an inductor.

[0212] The second terminal of the sixth transistor M6 is coupled to the output port RX_OUT of the receiving amplifier circuit 102, and the third terminal of the sixth transistor M6 is coupled to the second voltage bias terminal Vbias2.

[0213] It should be noted that the types of the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are the same as described above, and will not be repeated here. The first, second, and third terminals of the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are the same as described above, and will not be repeated here.

[0214] It should be understood that, when the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit single-ended signals, the power amplifier PA and the low-noise amplifier LNA include, but are not limited to, Figure 10b The provided structure can also be other structures, such as the power amplifier (PA) and low-noise amplifier (LNA) structures, which can also be similar. Figures 9a to 9hThe difference lies in the structure, where the input and output ports are single-ended ports.

[0215] Based on the above, it can be understood that the input / output port RF_IO can be a single-ended port or a differential port. In this case, the input / output port RF_IO includes a first differential input / output port RF_IO1 and a second differential input / output port RF_IO2.

[0216] When the input / output port RF_IO is a differential port, such as Figure 8a and Figure 8b As shown, the first end C of the second coil T2 is coupled to the first differential input / output port RF_IO1, and the second end D of the second coil T2 is coupled to the second differential input / output port RF_IO2.

[0217] Based on this, in some examples, such as Figure 8a As shown, the second coil T2 is also coupled to the power supply terminal Y.

[0218] When the input / output port RF_IO is a single-ended port, such as Figure 10a and Figure 10b As shown, the transceiver circuit 10 also includes a ground terminal GND, the first terminal C of the second coil T2 is coupled to the input / output port RF_IO, and the second terminal D of the second coil T2 is coupled to the ground terminal GND.

[0219] It is understandable that ESD (electrostatic discharge) phenomena often occur at the input / output port RF_IO. In the transceiver circuit 10, since the second coil T2 is coupled to the input / output port RF_IO, and the second coil T2 is usually also coupled to the ground terminal GND or the power supply terminal Y, the electrostatic discharge can be released through the ground terminal GND or the power supply terminal Y coupled to the second coil T2. In other words, the second coil T2 can provide an electrostatic discharge path (electrostatic discharge path such as...). Figure 10b As shown by the dashed line with arrows in the diagram, static electricity will not enter the internal circuit, thus effectively protecting the internal circuit. That is, the transceiver circuit 10 provided in this application embodiment can effectively protect the internal circuit.

[0220] Based on the above, when the input / output port RF_IO is a single-ended port, the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 can be used to transmit differential signals; they can also be used to transmit single-ended signals; or one can be used to transmit differential signals and the other to transmit single-ended signals.

[0221] Furthermore, depending on the different application scenarios of the transceiver circuit 10, the input / output port RF_IO can be coupled to different circuits or electronic components. In some examples, such as Figure 11a and Figure 11b As shown, the transceiver circuit 10 also includes an antenna 103, which is coupled to the input / output port RF_IO.

[0222] like Figure 11a As shown, when the input / output port RF_IO is a single-ended port, the antenna 103 is coupled to the input / output port RF_IO.

[0223] like Figure 11b As shown, when the input / output port RF_IO is a differential port, the input / output port RF_IO includes a first differential input / output port RF_IO1 and a second differential input / output port RF_IO2, and the antenna 103 includes a first antenna differential port 1031 and a second antenna differential port 1032; the first differential input / output port RF_IO1 is coupled to the first antenna differential port 1031, and the second differential input / output port RF_IO1 is coupled to the second antenna differential port 1032.

[0224] It should be noted that in some examples, the transceiver circuit 10 is integrated on a chip, meaning that the first transformer T, the transmitting amplifier circuit 101, and the receiving amplifier circuit 102 in the transceiver circuit 10 are all integrated on the chip. In this case, the first coil T1 and the second coil T2 of the first transformer are formed by metal wires in the chip. In this way, the first coil T1 and the second coil T2 can be fabricated simultaneously while the metal wires in the chip are being fabricated, thereby simplifying the manufacturing process.

[0225] The metal lines in the aforementioned chip may include, for example, metal lines located in the redistribution layer (RDL).

[0226] In other examples, the first coil T1 and the second coil T2 of the first transformer T in the transceiver circuit 10 are integrated on the package substrate, and the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are integrated on the chip; the first coil T1 and the second coil T2 are formed by metal wires in the package substrate. In this way, the first coil T1 and the second coil T2 can be fabricated simultaneously with the fabrication of the metal wires in the package substrate, thereby simplifying the manufacturing process.

[0227] Based on the transceiver circuit 10 provided in Embodiment 1 above, the input port RX_IN of the receiving amplifier circuit 102 and the output port TX_OUT of the transmitting amplifier circuit 101 in the transceiver circuit 10 are both coupled to the first coil T1 of the first transformer T, and the second coil T2 of the first transformer T is coupled to the input / output port RF_IO. When the transmitting amplifier circuit 101 is in a non-operating mode and the receiving amplifier circuit 102 is in an operating mode, the transmitting amplifier circuit 101 has a relatively small impact on the receiving amplifier circuit 102 because it is in a high-impedance state. When the transmitting amplifier circuit 101 adopts a common-source common-gate structure, its impedance will be even higher when it is in a non-operating mode, and its impact on the receiving amplifier circuit 102 will be even smaller. When the receiving amplifier circuit 102 is in a non-operating mode and the transmitting amplifier circuit 101 is in an operating mode, since the transceiver circuit 10 is operating at low frequency, the input port RX_IN of the receiving amplifier circuit 102 is in a high-impedance state. Both the input port RX_IN of the receiving amplifier circuit 102 and the output port TX_OUT of the transmitting amplifier circuit 101 are coupled to the first coil T1 of the first transformer T. Therefore, in the low-frequency operating mode, the receiving amplifier circuit 102 has a relatively small impact on the transmitting amplifier circuit 101. This allows for low insertion loss, increases the output power and efficiency of the transmitting link in the transmitting mode, and reduces noise in the receiving link in the receiving mode, thereby increasing the communication rate.

[0228] It should be understood that in the transceiver circuit 10, when the first transformer T is used to match the transmitting amplifier circuit 101 and the receiving amplifier circuit 102, in order to achieve a better matching effect, in some examples, such as... Figure 12 As shown, a resonant capacitor C1 can be connected in parallel to the first coil T1 of the first transformer T, and a resonant capacitor C2 can be connected in parallel to the second coil T2.

[0229] It is understandable that when there are parasitic capacitances in the traces of the chip or the traces of the package substrate, the parasitic capacitances may have an adverse effect on the circuit. However, since the transceiver circuit 10 provided in this application includes a first transformer T, the parasitic capacitances generated by the traces in the chip or the traces of the package substrate can act as a resonant capacitor C1 connected in parallel with the first coil T1, or act as part of the capacitance of the resonant capacitor C1 connected in parallel with the first coil T1. In this way, the adverse parasitic capacitances generated by the traces in the chip or the traces of the package substrate can be converted into capacitances that are beneficial to the transceiver circuit 10, and the parasitic capacitances generated by the traces in the chip or the traces of the package substrate are effectively utilized.

[0230] Example 2

[0231] The difference between Example 2 and Example 1 is that Example 2 adds a first matching network compared to Example 1.

[0232] like Figure 13a As shown, Embodiment 2 provides a transceiver circuit 10, which includes a first transformer T, a receiving amplifier circuit 102, a transmitting amplifier circuit 101, a voltage terminal VB, an input / output port RF_IO, and a first matching network 104.

[0233] The first transformer T includes a first coil T1 and a second coil T2 that are coupled to each other. The first coil T1 is coupled to the voltage terminal VB, the input port RX_IN of the receiving amplifier circuit 102, and the output port TX_OUT of the transmitting amplifier circuit 101, respectively. The second coil T2 is coupled to the input / output port RF_IO. The first matching network 104 is coupled between the input port RX_IN of the receiving amplifier circuit 102 and the first coil T.

[0234] It should be noted that the structure and connection relationship of the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 can be referred to the above embodiment 1, and will not be repeated here.

[0235] When the transceiver circuit 10 includes a first matching network, both the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 may be used to transmit differential signals; or both the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 may be used to transmit single-ended signals; or the transmitting amplifier circuit 101 may be used to transmit differential signals and the receiving amplifier circuit 102 may be used to transmit single-ended signals.

[0236] When the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit differential signals, such as Figure 13a As shown, the first matching network 104 is coupled between the first end A of the first coil T1 of the first transformer T, the second end B of the first coil T1, and the first differential receiving input port RX_IN1 and the second differential receiving input port RX_IN2 of the receiving amplifier circuit 102.

[0237] The first matching network 104 can be, for example, a transmission line, an inductor, a resistor, a capacitor, or a second transformer.

[0238] In cases where the receiving amplifier circuit 102 is used to transmit differential signals, such as... Figure 13b As shown, the first matching network 104 includes a first matching device 1041 and a second matching device 1042; the first matching device 1041 is coupled between the first end A of the first coil T and the first differential receiving input port RX_IN1, and the second matching device 1042 is coupled between the second end B of the first coil T and the second differential receiving input port RX_IN2.

[0239] In this case, the first matching device 1041 and the second matching device 1042 may be, for example, transmission lines, inductors, resistors or capacitors.

[0240] In cases where the receiving amplifier circuit 102 is used to transmit differential signals, in other examples, such as Figure 13c As shown, the transceiver circuit 10 includes a first matching network 104, which includes a first matching device 1041 and a second matching device 1042. The first matching network 104 is a second transformer. The first matching device 1041 and the second matching device 1042 are both coils. It can be considered that the first matching device 1041 and the second matching device 1042 are the primary coil or the secondary coil of the second transformer, respectively.

[0241] The first matching device 1041 is coupled to the first end A and the second end B of the first coil T1; the second matching device 1042 is coupled between the first differential receiving input port RX_IN1 and the second differential receiving input port RX_IN2.

[0242] When the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit single-ended signals, such as Figure 13d As shown, the first matching network 104 is coupled between the second end B of the first coil T1 and the input port RX_IN of the receiving amplifier circuit 102.

[0243] In this case, the first matching network 104 may be, for example, a transmission line, inductor, resistor, capacitor, or transformer.

[0244] When the transmitting amplifier circuit 101 is used to transmit differential signals and the receiving amplifier circuit 102 is used to transmit single-ended signals, such as Figure 13e As shown, the first matching network 104 is coupled to the first terminal A of the first coil T1 of the first transformer T, the second terminal B of the first coil T1, and the input port RX_IN of the receiving amplifier circuit 102.

[0245] In this case, the first matching network 104 is a differential-to-single-ended matching network, for example, the first matching network 104 is a transformer.

[0246] refer to Figure 13a or Figure 13b Because the transceiver circuit 10 is in a high-frequency state, the impedance Z of the input port RX_IN of the receiving amplifier circuit 102 is... off,lnaThe impedance of the receiving amplifier circuit 102 is relatively low, which means that when the transmitting amplifier circuit 101 is working, the receiving amplifier circuit 102 will affect the transmitting amplifier circuit 101, increasing the insertion loss. Based on this, in this second embodiment, a first matching network 104 is added between the input port RX_IN of the receiving amplifier circuit 102 and the first coil T1. Through the impedance transformation characteristics of the first matching network 104, the impedance of the receiving amplifier circuit 102 connected to the first coil T1 can be directly transformed into a high impedance Z. off,RX This ensures that the receiving amplifier circuit 102 has a minimal impact on the transmitting amplifier circuit 101 at high frequencies, thereby reducing insertion loss.

[0247] Based on this, when the transmitting amplifier circuit 101 is working, due to the impedance Z of the receiving amplifier circuit 101... off,lna In the high-impedance state, the first transformer T can transform the load impedance of the input / output port RF_IO to the optimal impedance required by the transmitting amplifier circuit 101. When the receiving amplifier circuit 102 is working and the transmitting amplifier circuit 101 is not working, the impedance Z of the transmitting amplifier circuit 101 is... off,pa In the high-impedance state, the first transformer T transforms the load impedance of the input / output port RF_IO to impedance R. opt,1 Then, it is transformed through the first matching network 104 to the optimal impedance R required by the receiving amplifier circuit 102. opt,2 .

[0248] It is understandable that, since the receiving amplifier circuit 102 mainly optimizes noise and the transmitting amplifier circuit 101 mainly optimizes power and efficiency, the difference in the optimal impedance between the receiving amplifier circuit 102 and the transmitting amplifier circuit 101 is relatively large. However, in this second embodiment, due to the addition of the first matching network 104, the load impedance of the input / output port RF_IO can be matched to the optimal impedance required by the transmitting amplifier circuit 101 in the transmitting mode, and the load impedance of the input / output port RF_IO can be matched to the optimal impedance required by the receiving amplifier circuit 102 in the receiving mode. Therefore, this second embodiment can achieve simultaneous matching of the optimal impedances of the transmitting amplifier circuit 101 and the receiving amplifier circuit 102.

[0249] In some examples, such as Figure 14a As shown, the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T.

[0250] When the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T, the area of ​​the transceiver circuit 10 can be reduced, thereby lowering the chip manufacturing cost.

[0251] Considering that the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T, the first matching network 104 and the first transformer T may interfere with each other. Therefore, in some examples where the transceiver circuit 10 includes the first matching network 104; the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T; and the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit differential signals, or the transmitting amplifier circuit 101 is used to transmit differential signals and the receiving amplifier circuit 102 is used to transmit single-ended signals, the first matching network 104 is arranged in a figure-eight shape with four ports.

[0252] Because the figure-eight shape has good anti-interference characteristics, the coupling between the first matching network 104 and the first transformer T is very low, so that the first matching network 104 and the first transformer T do not affect each other.

[0253] Here, the first matching network 104 can be, for example, composed of one or more turns of figure-eight metal wire.

[0254] For example, such as Figure 14a As shown, the first matching network 104 consists of a loop of figure-eight shaped metal wires.

[0255] For example, in the case where the first matching network 104 includes a first matching device 1041 and a second matching device 1042, and the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T, such as... Figure 14b , Figure 14c and Figure 14d As shown, in some examples, the first matching device 1041 and the second matching device 1042 are both arranged in a figure-eight shape with two ports.

[0256] It should be noted that, Figure 14b The diagram illustrates a figure-eight structure with two ports formed by the first matching device 1041 and the second matching device 1042 when they are transmission lines, inductors, resistors, or capacitors.

[0257] Figure 14c and Figure 14d The diagram illustrates the structure of the first matching device 1041 and the second matching device 1042 forming a figure-eight shape with two ports when the first matching network 104 is the second transformer.

[0258] When the first matching device 1041 forms a figure-eight shape with two ports, the figure-eight shape has good anti-interference characteristics, resulting in low coupling between the first matching device 1041 and the first transformer T, thus ensuring that the first matching device 1041 and the first transformer T do not interfere with each other. Similarly, when the second matching device 1042 forms a figure-eight shape with two ports, the figure-eight shape also has good anti-interference characteristics, resulting in low coupling between the second matching device 1042 and the first transformer T, thus ensuring that the second matching device 1042 and the first transformer T do not interfere with each other.

[0259] When both the first matching device 1041 and the second matching device 1042 are located within the first coil T1 and the second coil T2 of the first transformer T, in some examples, such as Figure 15 As shown, the first matching device 1041 and the second matching device 1042 do not overlap. In other examples, such as Figure 14b , Figure 14c and Figure 14d As shown, a portion of the first matching device 1041 and a portion of the second matching device 1042 overlap.

[0260] Here, a portion of the first matching device 1041 and a portion of the second matching device 1042 overlap, which reduces the area occupied by the first matching network 104.

[0261] It should be noted that the first matching device 1041 and the second matching device 1042 may be composed of, for example, multiple layers of metal lines on a chip or packaging substrate.

[0262] Based on this, the intersecting portions of the first matching device 1041 can be constructed using metal wires of different layers, and these metal wires are connected together through vias in the insulating layer. Similarly, the intersecting portions of the second matching device 1042 can be constructed using metal wires of different layers, and these metal wires are connected together through vias in the insulating layer. When portions of the first matching device 1041 and the second matching device 1042 overlap, the overlapping portions can be achieved using metal wires of different layers.

[0263] In the case where the transceiver circuit 10 includes a first matching network 104; the first matching network 104 is located within the first coil T1 and the second coil T2 of the first transformer T, and the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 are used to transmit single-ended signals, such as Figure 14e As shown, in some examples, the first matching network 104 is arranged in a figure-eight shape with two ports.

[0264] Because the figure-eight shape has good anti-interference characteristics, the coupling between the first matching network 104 and the first transformer T is very low, so that the first matching network 104 and the first transformer T do not affect each other.

[0265] Here, the first matching network 104 may be composed of, for example, multiple layers of metal lines on a chip or packaging substrate.

[0266] In some examples, such as Figure 13a , Figure 13b , Figure 13c and Figure 13d As shown, the transceiver circuit 10 also includes a switch S; the switch S is coupled between the first matching network 104 and the input port RX_IN of the receiving amplifier circuit 102.

[0267] When the receiving amplifier circuit 102 is used to transmit differential signals, such as Figure 13a , Figure 13b and Figure 13c As shown, switch S is coupled between the first differential receive input port RX_IN1 and the second differential receive input port RX_IN2.

[0268] When the receiving amplifier circuit 102 is used to transmit a single-ended signal, such as Figure 13d and Figure 13e As shown, switch S is coupled between the input port RX_IN of the receiving amplifier circuit 102 and the ground terminal GND.

[0269] It should be noted that in transmit mode, switch S is on; in receive mode, switch S is off.

[0270] When the transceiver circuit 10 includes a switch S, in the transmit mode, the switch S is turned on. When the transceiver circuit 10 is in high-frequency operation, the impedance Z of the switch S is... sw,off and the impedance Z of the receiving amplifier circuit 101 off,lna The sum of these impedances results in a low impedance, approximately equal to the on-resistance of switch S. Through the impedance transformation characteristics of the first matching network 104, the impedance on this side of the receiving amplifier circuit 102 connected to the first coil T can be directly transformed into a high impedance Z. off,RX This ensures that the receiving amplifier circuit 102 has a minimal impact on the transmitting amplifier circuit 101 at high frequencies, thereby reducing insertion loss.

[0271] Example 3

[0272] The difference between Example 3 and Example 2 is that Example 3 adds a second matching network compared to Example 2.

[0273] like Figure 16a and Figure 16bAs shown, Embodiment 3 provides a transceiver circuit 10, which includes a first transformer T, a receiving amplifier circuit 102, a transmitting amplifier circuit 101, a voltage terminal VB, an input / output port RF_IO, a first matching network 104, and a second matching network 105.

[0274] The first transformer T includes a first coil T1 and a second coil T2 that are coupled to each other. The first coil T1 is coupled to the voltage terminal VB, the input port RX_IN of the receiving amplifier circuit 102, and the output port TX_OUT of the transmitting amplifier circuit 101, respectively. The second coil T2 is coupled to the input / output port RF_IO. The first matching network 104 is coupled between the input port RX_IN of the receiving amplifier circuit 102 and the first coil T, and the second matching network 105 is coupled between the output port TX_OUT of the transmitting amplifier circuit 101 and the first coil T.

[0275] It should be noted that the structure and connection relationship of the transmitting amplifier circuit 101 and the receiving amplifier circuit 102 can be referred to the above embodiment one, and will not be repeated here. The first matching network 104 can be referred to the above embodiment two, and will not be repeated here.

[0276] In some examples, when the transmitting amplifier circuit 101 is used to transmit differential signals, the second matching network 105 is coupled between the first end A of the first coil T1 of the first transformer T, the second end B of the first coil T1, and the first differential transmitting output port TX_OUT1 and the second differential transmitting output port TX_OUT2 of the transmitting amplifier circuit 101.

[0277] The second matching network 105 can be, for example, a transmission line, an inductor, a resistor, a capacitor, or a third transformer.

[0278] In cases where the transmitting amplifier circuit 101 is used to transmit differential signals, such as... Figure 16a As shown, the second matching network 105 includes a third matching device 1051 and a fourth matching device 1052; the third matching device 1051 is coupled between the first end A of the first coil T1 and the first differential transmit output port TX_OUT1, and the fourth matching device 1052 is coupled between the second end B of the first coil T1 and the second differential transmit output port TX_OUT2.

[0279] In this case, the third matching device 1051 and the fourth matching device 1052 may be, for example, transmission lines, inductors, resistors or capacitors.

[0280] In some other examples, when the transmitting amplifier circuit 101 is used to transmit differential signals, the transceiver circuit 10 includes a second matching network 105, which includes a third matching device 1051 and a fourth matching device 1052; the second matching network 105 is a third transformer; the third matching device 1051 and the fourth matching device 1052 are both coils; it can be considered that the third matching device 1051 and the fourth matching device 1052 are the primary coil or the secondary coil of the third transformer, respectively.

[0281] The third matching device 1051 is coupled to the first end A of the first coil T1 and the second end B of the first coil T1; the fourth matching device 1052 is coupled between the first differential transmit output port TX_OUT1 and the second differential transmit output port TX_OUT2.

[0282] When the transmitting amplifier circuit 101 is used to transmit single-ended signals, such as Figure 16b As shown, the second matching network 105 is coupled between the second end B of the first coil T1 and the output port TX_OUT of the transmitting amplifier circuit 101.

[0283] In this case, the second matching network 105 can be, for example, a transmission line, inductor, resistor, capacitor, or transformer.

[0284] In this third embodiment, a second matching network 105 is coupled between the output port TX_OUT of the transmitting amplifier circuit 101 and the first coil T. On the one hand, when the receiving amplifier circuit 102 is working and the transmitting amplifier circuit 101 is not working, the impedance Z of the transmitting amplifier circuit 101 is... off,pa In the high-impedance state, the impedance Z of the transmitting amplifier circuit 101 is... off,pa Adding the impedance of the second matching network 105 increases the impedance on the side of the transmitting amplifier circuit 101 connected to the first coil T1. This further reduces the impact of the transmitting amplifier circuit 101 on the receiving amplifier circuit 102 when it is operating, thus further reducing insertion loss. On the other hand, in transmit mode, the first transformer T transforms the load impedance of the input / output port RF_IO to impedance R. opt,3 Then, the impedance is transformed to the optimal impedance R required by the transmitting amplifier circuit 101 through the second matching network 105. opt,4 This makes it easier to match the optimal impedance required by the transmitting amplifier circuit 101.

[0285] In some examples, the second matching network 105 is located within the first coil T1 and the second coil T2 of the first transformer T.

[0286] It is understandable that, if the area enclosed by the first coil T1 and the second coil T2 is large enough, the first matching network 104 and the second matching network 105 can both be set within the first coil T1 and the second coil T2.

[0287] When the second matching network 105 is located within the first coil T1 and the second coil T2 of the first transformer T, the area of ​​the transceiver circuit 10 can be reduced.

[0288] Considering that the second matching network 105 is located within the first coil T1 and the second coil T2 of the first transformer T, the second matching network 105 and the first transformer T may interfere with each other. Therefore, in cases where the transceiver circuit 10 includes the second matching network 105, which is located within the first coil T1 and the second coil T2 of the first transformer T, and the transmitting amplifier circuit 101 is used to transmit differential signals, in some examples, the second matching network 105 is arranged in a figure-eight shape with four ports.

[0289] Because the figure-eight shape has good anti-interference characteristics, the coupling between the second matching network 105 and the first transformer T is very low, so that the second matching network 105 and the first transformer T do not affect each other.

[0290] Here, the second matching network 105 can be, for example, composed of one or more turns of figure-eight metal wire.

[0291] For example, the second matching network 105 consists of a loop of figure-eight shaped metal wires.

[0292] For example, in the case where the second matching network 105 includes a third matching device 1051 and a fourth matching device 1052, and the second matching network 105 is located within the first coil T1 and the second coil T2 of the first transformer T, in some examples, the third matching device 1051 and the fourth matching device 1052 are both arranged in a figure-eight shape with two ports.

[0293] When the third matching device 1051 forms a figure-eight shape with two ports, the figure-eight shape has good anti-interference characteristics, resulting in low coupling between the third matching device 1051 and the first transformer T, thus ensuring that the third matching device 1051 and the first transformer T do not interfere with each other. Similarly, when the fourth matching device 1052 forms a figure-eight shape with two ports, the figure-eight shape also has good anti-interference characteristics, resulting in low coupling between the fourth matching device 1052 and the first transformer T, thus ensuring that the fourth matching device 1052 and the first transformer T do not interfere with each other.

[0294] When both the third matching device 1051 and the fourth matching device 1052 are located within the first coil T1 and the second coil T2 of the first transformer T, in some examples, the third matching device 1051 and the fourth matching device 1052 do not overlap. In other examples, portions of the third matching device 1051 and portions of the fourth matching device 1052 overlap.

[0295] Here, a portion of the third matching device 1051 and a portion of the fourth matching device 1052 overlap, which reduces the area of ​​the second matching network 105.

[0296] It should be noted that the third matching device 1051 and the fourth matching device 1052 may be composed of, for example, multiple layers of metal lines on a chip or packaging substrate.

[0297] Based on this, the intersecting portions of the third matching device 1051 can be constructed using metal wires of different layers, and these metal wires are connected together through vias in the insulating layer. Similarly, the intersecting portions of the fourth matching device 1052 can be constructed using metal wires of different layers, and these metal wires are connected together through vias in the insulating layer. When portions of the third matching device 1051 and the fourth matching device 1052 overlap, the overlapping portions can be achieved using metal wires of different layers.

[0298] In some examples, when the transceiver circuit 10 includes a second matching network 105 located within the first coil T1 and the second coil T2 of the first transformer T, and the receiving amplifier circuit 102 is used to transmit single-ended signals, the second matching network 105 is arranged in a figure-eight shape with two ports.

[0299] Because the figure-eight shape has good anti-interference characteristics, the coupling between the second matching network 105 and the first transformer T is very low, so that the second matching network 105 and the first transformer T do not affect each other.

[0300] Based on the above embodiments one, two and three, in some examples, the transceiver circuit 10 may also include one or more of the following: phase shifter, frequency synthesizer, mixer, attenuator, and digital-to-analog / analog-to-digital converter.

[0301] When the transceiver circuit 10 includes a phase shifter, the first transformer T, the receiving amplifier circuit 102, the transmitting amplifier circuit 102, and the phase shifter in the transceiver circuit 10 constitute the radio frequency front-end circuit.

[0302] Figure 17 A transceiver circuit 10 based on a phased array architecture is provided in the embodiments of this application, such as... Figure 17As shown, the transceiver circuit 10 based on the phased array architecture includes multiple radio frequency front-end circuits 30, a power divider or combiner, a transmit input port TX_IN, and a receive output port RX_OUT. In some examples, the transmit input port TX_IN and the receive output port RX_OUT are combined into one input / output port. The transceiver circuit 10 may also include an antenna coupled to the radio frequency front-end circuit 30 (i.e., the antenna is coupled to the input / output port RF_IO coupled to the second coil T2 of the first transformer T), the radio frequency front-end circuit 30 is coupled to the power divider or combiner, and the power divider or combiner is coupled to the transmit input port TX_IN and the receive output port RX_OUT.

[0303] When the transceiver circuit 10 also includes a switch between the input port TX_IN of the transmit amplifier circuit 101 coupled in the transceiver circuit 10 and the output port RX_OUT of the receive amplifier circuit 102, the transmit amplifier circuit 101, the receive amplifier circuit 102, and the switch between the input port TX_IN of the transmit amplifier circuit 101 and the output port RX_OUT of the receive amplifier circuit 102 coupled in the transceiver circuit 10 constitute a bidirectional amplifier circuit.

[0304] In some examples, the wired communication system 150 or wireless communication system 160 described above may also include a self-loopback calibration system. This self-loopback calibration system can be applied to carrier and harmonic leakage calibration, nonlinear calibration, DPD (digital pre-distortion) calibration, etc. The transceiver circuit 10 described above can be incorporated into the self-loopback calibration system; that is, the self-loopback calibration system includes the transceiver circuit 10.

[0305] When the self-loop calibration system is working, it inputs a signal from the input port TX_IN of the transmitting amplifier circuit of the transceiver circuit 10 and detects the signal output from the output port RX_OUT of the receiving amplifier circuit of the transceiver circuit 10.

[0306] It should be understood that the transceiver circuit 10 includes, but is not limited to, the self-loopback calibration system of the communication system.

[0307] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transceiver circuit, characterized in that, It includes a first transformer, a receiving amplifier circuit, a transmitting amplifier circuit, voltage terminals, input and output ports, and a first matching network; The first transformer includes a first coil and a second coil coupled to each other; the first coil is coupled to the voltage terminal, and the two ends of the first coil are respectively coupled to the output port of the transmitting amplifier circuit; the first matching network is coupled between the input port of the receiving amplifier circuit and the two ends of the first coil. The second coil is coupled to the input / output port.

2. The transceiver circuit according to claim 1, characterized in that, The transceiver circuit also includes a switch; The switch is coupled between the first matching network and the input port of the receiving amplifier circuit.

3. The transceiver circuit according to claim 1 or 2, characterized in that, The first matching network is located within the first coil and the second coil of the first transformer.

4. The transceiver circuit according to claim 1 or 2, characterized in that, The transceiver circuit also includes a second matching network; The second matching network is coupled between the output port of the transmitting amplifier circuit and the first coil.

5. The transceiver circuit according to claim 4, characterized in that, The second matching network is located within the first coil and the second coil of the first transformer.

6. The transceiver circuit according to claim 1 or 2, characterized in that, The transceiver circuit also includes a ground terminal; the input / output port is a single-ended port, the first end of the second coil is coupled to the input / output port, and the second end of the second coil is coupled to the ground terminal; Alternatively, the input / output ports may include a first differential input / output port and a second differential input / output port, with a first end of the second coil coupled to the first differential input / output port and a second end of the second coil coupled to the second differential input / output port.

7. The transceiver circuit according to claim 6, characterized in that, The transceiver circuit also includes an antenna; The input / output port is a single-ended port, and the antenna is coupled to the input / output port; Alternatively, the input / output ports may include a first differential input / output port and a second differential input / output port, and the antenna may include a first antenna differential port and a second antenna differential port. The first differential input / output port is coupled to the first antenna differential port, and the second differential input / output port is coupled to the second antenna differential port.

8. The transceiver circuit according to claim 1 or 2, characterized in that, The output ports of the transmitting amplifier circuit include a first differential transmitting output port and a second differential transmitting output port; the first end of the first coil is coupled to the first differential transmitting output port, and the second end of the first coil is coupled to the second differential transmitting output port; And / or, the input ports of the receiving amplifier circuit include a first differential receiving input port and a second differential receiving input port; the first end of the first coil is coupled to the first differential receiving input port, and the second end of the first coil is coupled to the second differential receiving input port.

9. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a first matching network; the first matching network includes a first matching device and a second matching device. The first matching device is coupled between the first end of the first coil and the first differential receiving input port, and the second matching device is coupled between the second end of the first coil and the second differential receiving input port.

10. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a first matching network, which includes a first matching device and a second matching device; the first matching network is a second transformer; both the first matching device and the second matching device are coils. The first matching device is coupled to the first end of the first coil and the second end of the first coil; the second matching device is coupled between the first differential receive input port and the second differential receive input port.

11. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a first matching network; the first matching network is located within the first coil and the second coil of the first transformer; The first matching network is arranged in a figure-eight shape with four ports.

12. The transceiver circuit according to claim 11, characterized in that, The first matching network includes a first matching device and a second matching device; Both the first matching device and the second matching device are arranged in a figure-eight shape with two ports.

13. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a second matching network; the second matching network includes a third matching device and a fourth matching device; The third matching device is coupled between the first end of the first coil and the first differential transmit output port, and the fourth matching device is coupled between the second end of the first coil and the second differential transmit output port.

14. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a second matching network, which includes a third matching device and a fourth matching device; the second matching network is a third transformer; the third matching device and the fourth matching device are both coils. The third matching device is coupled to the first end of the first coil and the second end of the first coil; the fourth matching device is coupled between the first differential transmit output port and the second differential transmit output port.

15. The transceiver circuit according to claim 8, characterized in that, The transceiver circuit includes a second matching network; the second matching network is located within the first coil and the second coil of the first transformer; The second matching network is arranged in a figure-eight shape with four ports.

16. The transceiver circuit according to claim 15, characterized in that, The second matching network includes a third matching device and a fourth matching device; The third matching device and the fourth matching device are both arranged in a figure-eight shape with two ports.

17. The transceiver circuit according to claim 1 or 2, characterized in that, The transmitting amplifier circuit is a power amplifier.

18. The transceiver circuit according to claim 8, characterized in that, The input ports of the transmitting amplifier circuit include a first differential transmitting input port and a second differential transmitting input port; the transmitting amplifier circuit is a power amplifier; the transceiver circuit also includes a ground terminal and a first voltage bias terminal; The power amplifier includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The first terminal of the first transistor is coupled to the first end of the first coil, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the gate of the first transistor is coupled to the first voltage bias terminal. The second terminal of the second transistor is coupled to the ground terminal, and the gate of the second transistor is coupled to the first differential emitter input port; The first terminal of the third transistor is coupled to the second terminal of the first coil, the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, and the gate of the third transistor is coupled to the first voltage bias terminal. The second terminal of the fourth transistor is coupled to the ground terminal, and the gate of the fourth transistor is coupled to the second differential emitter input port; Wherein, the first electrode is the source and the second electrode is the drain; Alternatively, the first electrode can be the drain and the second electrode can be the source.

19. The transceiver circuit according to claim 1 or 2, characterized in that, The receiving amplifier circuit is a low-noise amplifier.

20. The transceiver circuit according to claim 8, characterized in that, The output ports of the receiving amplifier circuit include a first differential receiving output port and a second differential receiving output port; the transceiver circuit also includes a ground terminal and a second voltage bias terminal; the receiving amplifier circuit is a low-noise amplifier. The low-noise amplifier includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The first terminal of the fifth transistor is coupled to the ground terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the gate of the fifth transistor is coupled to the first terminal of the first coil. The second terminal of the sixth transistor is coupled to the first differential receive output port, and the gate of the sixth transistor is coupled to the second voltage bias terminal; The first terminal of the seventh transistor is coupled to the ground terminal, the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor, and the gate of the seventh transistor is coupled to the second terminal of the first coil. The second terminal of the eighth transistor is coupled to the second differential receive output port, and the gate of the eighth transistor is coupled to the second voltage bias terminal; Wherein, the first electrode is the source and the second electrode is the drain; Alternatively, the first electrode can be the drain and the second electrode can be the source.

21. The transceiver circuit according to claim 1 or 2, characterized in that, The first end of the first coil is coupled to the voltage terminal, and the second end of the first coil is coupled to the output port of the transmitting amplifier circuit and the input port of the receiving amplifier circuit, respectively.

22. The transceiver circuit according to claim 1 or 2, characterized in that, The transceiver circuit is integrated on a chip, and the first coil and the second coil of the first transformer are made of metal wires in the chip.

23. The transceiver circuit according to claim 22, characterized in that, The metal wires include those located in the rewiring arrangement.

24. The transceiver circuit according to claim 1 or 2, characterized in that, The first coil and the second coil of the first transformer in the transceiver circuit are integrated on the packaging substrate, and the transmitting amplifier circuit and the receiving amplifier circuit are integrated on the chip. The first coil and the second coil are made of metal wires in the package substrate.

25. The transceiver circuit according to claim 1 or 2, characterized in that, The transceiver circuit also includes one or more of the following: phase shifter, frequency synthesizer, mixer, attenuator, and digital-to-analog / analog-to-digital converter.

26. A communication system, characterized in that, Includes a circuit board and a transceiver circuit as described in any one of claims 1-25; The transceiver circuit is coupled to the circuit board.

27. The communication system according to claim 26, characterized in that, The communication system also includes a self-loopback calibration system; The self-loop calibration system includes the transceiver circuit.

28. An electronic device, characterized in that, Includes a processor and the communication system as described in claim 26 or 27; The processor and the communication system are coupled.

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