Display panel and display device

Abstract

The application discloses a display panel and a display device. Wherein, when the bias adjustment control signal is an effective pulse signal, the bias adjustment module is opened, and the bias adjustment module provides a bias adjustment signal for a driving transistor; the data refresh frequency of the first pixel circuit is a first frequency F1, the data refresh frequency of the second pixel circuit is a second frequency F2, and F1≠F2; the data refresh period of the first pixel circuit includes R1 picture refresh frames, and the data refresh period of the second pixel circuit includes R2 picture refresh frames; in the data refresh period of the first pixel circuit, the time length sum of the effective pulse of the bias adjustment control signal is Ws1, in the data refresh period of the second pixel circuit, the time length sum of the effective pulse of the bias adjustment control signal is Ws2; Ws1 / R1≠Ws2 / R2. The embodiment of the application is beneficial to realize the respective functions of the pixel circuits in the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the continuous development of display technology and the increasing demands of consumers for display panels, the functions integrated into display panels are becoming more and more numerous. In some scenarios, the pixel circuits of the same display panel are required to have different display functions. For example, displaying game screens and movie screens, as well as displaying text and time information, requires pixel circuits to have different functions.

[0003] Pixel circuits are a crucial component in display panels, playing a vital role in providing driving current to the light-emitting elements of the display panel. When different pixel circuits in a display panel require different display functions or effects, it is often necessary to differentiate the pixel circuits by region. Therefore, how to differentiate the pixel circuits according to their display functions or effects is a current research hotspot in this field. Summary of the Invention

[0004] This application provides a display panel and a display device, which can be used to differentiate the pixel circuits according to different requirements of the pixel circuits in the display panel, so as to realize the respective functions of the pixel circuits in the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] Pixel circuits and light-emitting elements;

[0007] The pixel circuit includes a driving module and a bias adjustment module;

[0008] The driver module includes driver transistors;

[0009] The control terminal of the bias adjustment module receives the bias adjustment control signal. When the bias adjustment control signal is a valid pulse signal, the bias adjustment module is turned on and provides the bias adjustment signal to the drive transistor.

[0010] The operation of the pixel circuit includes a first mode and a second mode. The pixel circuit operating in the first mode is called the first pixel circuit, and the pixel circuit operating in the second mode is called the second pixel circuit.

[0011] The data refresh frequency of the first pixel circuit is the first frequency F1, and the data refresh frequency of the second pixel circuit is the second frequency F2, where F1 ≠ F2.

[0012] The data refresh cycle of the first pixel circuit includes R1 frame refreshes, and the data refresh cycle of the second pixel circuit includes R2 frame refreshes, where R1≥1 and R2≥1.

[0013] During the data refresh cycle of the first pixel circuit, the total duration of the effective pulses of the bias adjustment control signal is Ws1, and during the data refresh cycle of the second pixel circuit, the total duration of the effective pulses of the bias adjustment control signal is Ws2; where...

[0014] Ws1 / R1≠Ws2 / R2.

[0015] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device including a display panel as described in the first aspect embodiment.

[0016] As described above, in the display panel and display device provided in this application embodiment, when the bias adjustment control signal is a valid pulse signal, the bias adjustment module is turned on, and the bias adjustment module provides a bias adjustment signal to the driving transistor, where Ws1 / R1≠Ws2 / R2. Because the bias adjustment signal is a signal received by the pixel circuit to adjust the bias state of the driving transistor, when the bias adjustment control signal is a valid pulse signal, the bias adjustment signal is transmitted to the driving transistor. The duration of the valid pulse signal affects the adjustment duration of the bias state of the driving transistor. If the first pixel circuit and the second pixel circuit have different functions, resulting in different bias states of the driving transistor, then different durations of the valid pulse signal of the bias adjustment control signal are needed to adjust the bias states of the driving transistors in the first pixel circuit and the second pixel circuit respectively, thereby optimizing the functions of each pixel circuit. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0018] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of another display panel provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0022] Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of yet another display panel provided in an embodiment of this application;

[0027] Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0032] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0033] This application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0034] One aspect of this application provides a display panel, which can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (micro LED) display panel, or other types of display panels. This embodiment does not impose any special limitations on this type of display panel.

[0035] refer to Figures 1 to 4 The display panel includes pixel circuitry and light-emitting elements 20.

[0036] The pixel circuit is used to drive the light-emitting element 20. The pixel circuit includes a driving module 110 and a bias adjustment module 114. The driving module 110 includes a driving transistor T0. The control terminal of the bias adjustment module 114 receives a bias adjustment control signal. When the bias adjustment control signal is a valid pulse signal, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a bias adjustment signal DVH to the driving transistor T0.

[0037] The operation of pixel circuit 10 includes a first mode and a second mode. The pixel circuit operating in the first mode is the first pixel circuit 101, and the pixel circuit operating in the second mode is the second pixel circuit 102. For ease of distinction, in the accompanying drawings of this application, the bias adjustment control signal received by the control terminal of the bias adjustment module 114 in the first pixel circuit 101 is labeled as the first bias adjustment control signal S14, and the bias adjustment control signal received by the control terminal of the bias adjustment module 114 in the second pixel circuit 102 is labeled as the second bias adjustment control signal S24.

[0038] In some cases, the functional requirements for the first pixel circuit 101 and the second pixel circuit 102 may be reflected in the difference in data refresh frequency. For example, the data refresh frequency of the first pixel circuit 101 is a first frequency F1, and the data refresh frequency of the second pixel circuit 102 is a second frequency F2, where F1 ≠ F2.

[0039] The data refresh cycle of the first pixel circuit 101 includes R1 screen refresh frames, and the data refresh cycle of the second pixel circuit 102 includes R2 screen refresh frames, where R1≥1 and R2≥1.

[0040] During the data refresh cycle of the first pixel circuit 101, the total duration of the effective pulses of the first bias adjustment control signal S14 is Ws1, and during the data refresh cycle of the second pixel circuit 102, the total duration of the effective pulses of the second bias adjustment control signal S24 is Ws2; wherein, Ws1 / R1≠Ws2 / R2.

[0041] In this embodiment, when the bias adjustment control signal is a valid pulse signal, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a bias adjustment signal DVH to the driving transistor T0, where Ws1 / R1 ≠ Ws2 / R2. Because the bias adjustment signal is a signal received by the pixel circuit to adjust the bias state of the driving transistor, when the bias adjustment control signal is a valid pulse signal, the bias adjustment signal DVH is transmitted to the driving transistor T0. The duration of the valid pulse signal affects the adjustment duration of the driving transistor's bias state. If the first pixel circuit 101 and the second pixel circuit 102 have different functions, resulting in different bias states of the driving transistors, then different durations of the valid pulse signals of the bias adjustment control signal are needed to adjust the bias states of the driving transistors in the first pixel circuit 101 and the second pixel circuit 102 respectively, thereby optimizing the functions of the different pixel circuits.

[0042] It should be noted that, as Figure 1 and Figure 2 As shown, the driving transistor T0 is a P-type transistor, where, Figure 1The bias adjustment module 114 is connected to the first terminal of the driving transistor T0. Figure 2 The bias adjustment module 114 is connected to the second terminal of the driving transistor T0. For example... Figure 3 and Figure 4 As shown, the driving transistor T0 is an N-type transistor, where, Figure 3 The bias adjustment module 114 is connected to the first terminal of the driving transistor T0. Figure 4 The bias adjustment module 114 is connected to the second terminal of the driving transistor T0. When the driving transistor T0 is a P-type transistor, during the light-emitting stage, the signal applied to the gate of the driving transistor T0 is the data signal Vdata, the signal applied to the first terminal is the first power supply signal PVDD, and the signal at the second terminal may be a relatively low potential. At this time, there may be a situation where the gate potential of the driving transistor T0 is higher than the potential of the second terminal. When the P-type driving transistor T0 is in the on state, there will be a reverse electric field between the gate and the second terminal, which will cause the carriers of the active layer of the driving transistor T0 to polarize, thereby causing the threshold voltage of the driving transistor T0 to shift, and thus affecting the generation of the driving current. In order to improve this phenomenon, the bias adjustment module 114 inputs a relatively high-level bias adjustment signal to the first or second terminal of the driving transistor T0, so that the potential of the first or second terminal is higher than the gate potential, thereby canceling the aforementioned threshold voltage shift problem. When the driving transistor T0 is an N-type transistor, the situation is similar. During the light-emitting stage, there may be a situation where the gate potential of the N-type driving transistor T0 is lower than the second electrode potential. At this time, a reverse electric field will also be formed, so the threshold voltage of the driving transistor T0 will be offset. Therefore, the bias adjustment module 114 inputs a relatively low-level bias adjustment signal to the first or second electrode of the driving transistor T0, so that the potential of the first or second electrode is lower than the gate potential, thereby canceling the aforementioned threshold voltage offset problem.

[0043] In some cases, the light-emitting element 20 driven by the first pixel circuit 101 can be used to play movies, games, and other images. In this case, the first pixel circuit 101 is required to have a high data refresh rate to ensure fast image refresh and improve user experience. The light-emitting element driven by the second pixel circuit 102 can be used to display text, time information, etc. In this case, the second pixel circuit 102 does not need to have a high data refresh rate. A lower data refresh rate is sufficient to meet the requirements.

[0044] In some embodiments, F1 > F2, Ws1 / R1 < Ws2 / R2.

[0045] In a display panel, the frame refresh rate is generally the frequency at which the smallest unit of image refresh, the subframe, changes. The data refresh rate, on the other hand, refers to the frequency at which the data signal Vdata is written to the gate of the driving transistor T0. Taking a panel with a frame refresh rate of 120Hz as an example, a data refresh rate of 60Hz means that one data refresh cycle includes one data write frame and one hold frame. A data write frame is a subframe in which the data signal Vdata is written to the gate of the driving transistor T0, and a hold frame is a subframe in which no data signal Vdata is written to the gate of the driving transistor T0. When the data refresh rate is 30Hz, it means that one data refresh cycle includes one data write frame and three hold frames, and so on. The data refresh rate of the first pixel circuit 101 is greater than the data refresh rate of the second pixel circuit 102. For example, the data refresh rate of the first pixel circuit 101 is 60Hz, and the data refresh rate of the second pixel circuit 102 is 30Hz, etc. This is just an example; in other cases, the data refresh rates of the first pixel circuit 101 and the second pixel circuit 102 can be set according to actual needs.

[0046] A higher data refresh rate means a higher frequency of gate potential change in the driving transistor T0. The bias problem of the driving transistor T0 is closely related to its gate potential during the light emission stage. When the gate potential of the driving transistor T0 changes at a high frequency, the driving transistor T0 will not have the same reverse electric field for a long time, meaning it will not be under the same bias condition for an extended period. However, when the gate potential of the driving transistor T0 changes at a low frequency, if a bias problem occurs, it may persist for a relatively long time. Therefore, a lower data refresh rate in the pixel circuit may lead to a more severe bias problem.

[0047] To address this technical issue, when F1 > F2, the data refresh rate of the second pixel circuit 102 is relatively low, resulting in a more severe bias problem (Ws1 / R1 < Ws2 / R2). This allows for a longer bias adjustment period for the second pixel circuit 102, enabling the correction of the more severe bias problem through a longer adjustment time. Conversely, the data refresh rate of the first pixel circuit 101 is higher, leading to a less severe bias problem. Therefore, the bias adjustment period for the first pixel circuit 101 can be appropriately shorter.

[0048] Optionally, in the first scenario, the effective pulse lengths of the data writing to the intra-frame and holding intra-frame offset adjustment control signals can be different at the same data refresh frequency; the effective pulse lengths of the data writing to the intra-frame offset adjustment control signals can be the same at different data refresh frequencies; and the effective pulse lengths of the holding intra-frame offset adjustment control signals can be the same at different data refresh frequencies.

[0049] In the second scenario, at the same data refresh frequency, the effective pulse lengths of the data writing to the intra-frame offset adjustment control signal and the holding intra-frame offset adjustment control signal can be the same. At different data refresh frequencies, the effective pulse lengths of the data writing to the intra-frame offset adjustment control signal can be different. At different data refresh frequencies, the effective pulse lengths of the holding intra-frame offset adjustment control signal can also be different.

[0050] Taking a panel with a frame refresh rate of 120Hz as an example, F1 = 60Hz, the data refresh rate of the first pixel circuit 101 is 60Hz, and one data refresh cycle of the first pixel circuit 101 may include one data write frame and one hold frame, R1 = 2. F2 = 30Hz, the data refresh rate of the second pixel circuit 102 is 30Hz, and one data refresh cycle of the second pixel circuit 102 may include one data write frame and three hold frames, R1 = 4.

[0051] For example, in the first case, when the data refresh rate is 60Hz or 30Hz, the effective pulse duration of the data writing intra-frame offset adjustment control signal is 5ms, and the effective pulse duration of the intra-frame offset adjustment control signal is 10ms. Then WS1 = 5 + 10 = 15ms, WS2 = 5 + 3 * 10 = 35ms, Ws1 / R1 = 15 / 2, Ws2 / R2 = 35 / 4, so Ws1 / R1 < Ws2 / R2.

[0052] For example, in the second scenario, when the data refresh rate is 60Hz, the effective pulse duration for writing data to the intra-frame offset adjustment control signal is 5ms, and the duration for holding the effective pulse duration of the intra-frame offset adjustment control signal is 5ms, then WS1 = 5 + 5 = 10ms. When the data refresh rate is 30Hz, the effective pulse duration for writing data to the intra-frame offset adjustment control signal is 10ms, and the duration for holding the effective pulse duration of the intra-frame offset adjustment control signal is 10ms, then WS2 = 10 + 3 * 10 = 40ms. Ws1 / R1 = 10 / 2, Ws2 / R2 = 10 / 4, therefore Ws1 / R1 < Ws2 / R2.

[0053] Therefore, in different situations, when F1 > F2, Ws1 / R1 < Ws2 / R2 applies.

[0054] It should be noted that the specific values ​​of the effective pulse length of the bias adjustment control signal in the above examples are merely examples and are not intended to limit this application.

[0055] In some embodiments, the R1 frame refreshes in the data refresh cycle of the first pixel circuit 101 include r1 data write frames and r2 hold frames, where r1 ≥ 1 and r2 > 0. The R2 frame refreshes in the data refresh cycle of the second pixel circuit include r3 data write frames and r4 hold frames, where r3 ≥ 1 and r4 > 0. The sum of the effective pulse lengths of the bias adjustment control signals in the r1 data write frames is Wr1, where Wr1 / r1 ≥ 0. The sum of the effective pulse lengths of the bias adjustment control signals in the r2 hold frames is Wr2, where Wr2 / r2 ≥ 0. The sum of the effective pulse lengths of the bias adjustment control signals in the r3 data write frames is Wr3, where Wr3 / r3 ≥ 0. The sum of the effective pulse lengths of the bias adjustment control signals in the r4 hold frames is Wr4, where Wr4 / r4 ≥ 0. At least two of Wr1 / r1, Wr2 / r2, Wr3 / r3, and Wr4 / r4 are not equal.

[0056] A data refresh cycle in a pixel circuit may include one or more data write frames and one or more hold frames. Because the data write frame writes the data signal Vdata to the gate of the driving transistor T0, involving changes in the grayscale signal, the gate acquisition capability of the driving transistor T0 is critical, thus requiring high stability from the driving transistor T0. Therefore, the data write frame may include a bias adjustment stage; that is, the bias adjustment control signal within the data write frame may contain effective pulses. This bias adjustment signal can then adjust the bias state within the driving transistor, eliminating threshold voltage offset and thus avoiding flickering during grayscale changes.

[0057] As previously mentioned, the hold frame data signal Vdata is not written to the gate of the driving transistor T0. However, when the display panel's data refresh rate is low, meaning there are many hold frames within a single data refresh cycle, the bias phenomenon in the driving transistor that remains in a hold frame for an extended period will become increasingly severe. If no bias adjustment phase is set in the hold frame, it will lead to a significant threshold voltage offset problem in the driving transistor T0. To avoid this phenomenon, a bias adjustment phase can be set in the hold frame; that is, the bias adjustment control signal within the hold frame can contain valid pulses.

[0058] It is understandable that R1=r1+r2, Ws1=Wr1+Wr2, R2=r3+r4, Ws2=Wr3+Wr4, and if at least two of Wr1 / r1, Wr2 / r2, Wr3 / r3, and Wr4 / r4 are not equal, then Ws1 / R1≠Ws2 / R2.

[0059] In some embodiments, Wr1 / r1≠Wr2 / r2, and / or, Wr3 / r3≠Wr4 / r4.

[0060] If the first pixel circuit 101 is designed to perform different functions in the data write frame and the hold frame, resulting in different bias states of the driving transistors of the first pixel circuit 101 in the data write frame and the hold frame, then different effective pulse signal durations of the bias adjustment control signal are required. For example, Wr1 / r1 ≠ Wr2 / r2. In this way, the bias states of the driving transistors of the first pixel circuit 101 in the data write frame and the hold frame can be adjusted separately, which is beneficial to optimizing the different functions of the first pixel circuit 101 in the data write frame and the hold frame.

[0061] If the second pixel circuit 102 is designed to perform different functions in the data write frame and the hold frame, resulting in different bias states of the driving transistors in the data write frame and the hold frame, then different effective pulse signal durations of the bias adjustment control signal are required. For example, Wr3 / r3 ≠ Wr4 / r4. In this way, the bias states of the driving transistors in the second pixel circuit 102 in the data write frame and the hold frame can be adjusted separately, which is beneficial to optimizing the different functions of the second pixel circuit 102 in the data write frame and the hold frame.

[0062] As previously described, during the data write frame, a data signal Vdata is written to the gate of the driving transistor T0, while during the hold frame, no data signal Vdata is written to the gate of the driving transistor T0. During the operation of the pixel circuit, before the data signal Vdata is written to the gate of the driving transistor T0, the gate of the driving transistor T0 generally needs to be reset. This resets the data signal from the previous frame to a fixed potential before writing the data signal Vdata, thus preventing interference from the previous frame's data signal to the current frame's data signal Vdata. Furthermore, for hold frames where no data signal needs to be written, the gate of the driving transistor T0 does not need to be reset. The gate potential of the driving transistor T0 during the hold frame remains the same as the gate potential after the data signal Vdata is written to the gate of the driving transistor T0 during the data write frame. In other words, the gate potential of the driving transistor T0 can change during the data write frame, but it can remain constant during the hold frame. Therefore, the bias phenomenon in the driving transistor that is in a hold frame for a long time will become increasingly severe.

[0063] Optionally, Wr1 / r1 < Wr2 / r2, and / or Wr3 / r3 < Wr4 / r4.

[0064] For the first pixel circuit 101, the bias problem in the holding frame is relatively more serious than that in the data writing frame, Wr1 / r1 < Wr2 / r2. This allows for a longer time to adjust the bias of the first pixel circuit 101 within the holding frame, which can correct the relatively serious bias problem through a relatively long time of bias adjustment.

[0065] For the second pixel circuit 102, the bias problem in the holding frame is relatively more serious compared to the data writing frame, Wr1 / r1 < Wr2 / r2. This allows for a longer time to adjust the bias of the second pixel circuit 102 within the holding frame, which can correct the relatively serious bias problem through a relatively long time of bias adjustment.

[0066] Optionally, F1 > F2, r2 < r4. That is, the smaller the data refresh frequency, the larger the number of hold frames can be included in a data refresh cycle.

[0067] Alternatively, r1 = r3, or r1 ≠ r3.

[0068] In some embodiments, Wr1 / r1≠Wr3 / r3, and / or, Wr2 / r2≠Wr4 / r4.

[0069] If the first pixel circuit 101 and the second pixel circuit 102 perform different functions in the data writing frame, resulting in different bias states of the driving transistors of the first pixel circuit 101 and the second pixel circuit 102 in the data writing frame, then different effective pulse signal durations of the bias adjustment control signal are required. For example, Wr1 / r1≠Wr3 / r3. In this way, the bias states of the driving transistors of the first pixel circuit 101 and the second pixel circuit 102 in the data writing frame can be adjusted respectively, which is beneficial to optimizing the different functions of the first pixel circuit 101 and the second pixel circuit 102 in the data writing frame.

[0070] If the first pixel circuit 101 and the second pixel circuit 102 perform different functions in the hold frame, resulting in different bias states of the driving transistors of the first pixel circuit 101 and the second pixel circuit 102 in the hold frame, then different effective pulse signal durations of the bias adjustment control signal are required. For example, Wr2 / r3 ≠ Wr4 / r4. In this way, the bias states of the driving transistors of the first pixel circuit 101 and the second pixel circuit 102 in the hold frame can be adjusted respectively, which is beneficial to optimizing the different functions of the first pixel circuit 101 and the second pixel circuit 102 in the hold frame.

[0071] In some embodiments, F1 > F2, Wr1 / r1 < Wr3 / r3; and / or, F1 > F2, Wr2 / r2 < Wr4 / r4.

[0072] As mentioned earlier, a higher data refresh rate means a higher frequency of gate potential change in the driving transistor T0. The bias problem of the driving transistor T0 is closely related to the gate potential of the driving transistor T0 during the light emission stage. When the gate potential change frequency of the driving transistor T0 is large, the driving transistor T0 will not have the same reverse electric field for a long time. That is, the driving transistor T0 will not be under the same bias problem for a long time. However, when the gate potential change frequency of the driving transistor T0 is small, if a bias problem occurs, the bias problem may exist for a relatively long time. Therefore, when the data refresh rate of the pixel circuit is low, the bias problem may be more serious.

[0073] To address this technical issue, when F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem, with Wr1 / r1 < Wr3 / r3. Therefore, the time for bias adjustment of the second pixel circuit 102 during the data write frame can be longer, allowing for a more thorough correction of the more severe bias problem. Conversely, the first pixel circuit 101 has a higher data refresh rate and a relatively milder bias problem, allowing for a shorter time for bias adjustment during the data write frame. And / or, when F1 > F2 and Wr2 / r2 < Wr4 / r4, the time for bias adjustment of the second pixel circuit 102 during the hold frame can be longer, allowing for a more thorough correction of the more severe bias problem. Conversely, the first pixel circuit 101 has a higher data refresh rate and a relatively milder bias problem, allowing for a shorter time for bias adjustment during the hold frame.

[0074] As mentioned earlier, the effective pulse length of the data written to the intra-frame offset adjustment control signal can be different for different pixel circuits.

[0075] In some embodiments, the data write frame in the data refresh cycle of the first pixel circuit 101 is a first data write frame, and in a first data write frame, the sum of the effective pulse lengths of the bias adjustment control signal is Wd1. The data write frame in the data refresh cycle of the second pixel circuit 102 is a second data write frame, and in a second data write frame, the sum of the effective pulse lengths of the bias adjustment control signal is Wd2. Wherein, Wd1≠Wd2.

[0076] In some embodiments, F1 > F2, Wd1 < Wd2.

[0077] Because a lower data refresh rate in the pixel circuit can exacerbate bias problems, a solution is to address this issue. When F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (Wd1 < Wd2). This allows for a longer bias adjustment period within the second data write frame, effectively correcting the more severe bias problem. Conversely, the first pixel circuit 101 has a higher data refresh rate and a less severe bias problem, allowing for a shorter bias adjustment period within the first data write frame.

[0078] In some embodiments, the number of valid pulses of the bias adjustment control signal in the first data write frame and the second data write frame can be adjusted, and / or the duration of a single valid pulse of the bias adjustment control signal in the first data write frame and the second data write frame can be adjusted so that Wd1≠Wd2.

[0079] For example, a first data write frame includes xd1 valid pulses of bias adjustment control signals, where xd1 ≥ 1; wherein the duration of at least one valid pulse of the bias adjustment control signal is Wde1. A second data write frame includes xd2 valid pulses of bias adjustment control signals, where xd2 ≥ 1; wherein the duration of at least one valid pulse of the bias adjustment control signal is Wde2. Where xd1 ≠ xd2, and / or Wde1 ≠ Wde2, thus making Wd1 ≠ Wd2.

[0080] In some embodiments, F1 > F2, xd1 < xd2; and / or, F1 > F2, Wde1 < Wde2.

[0081] Because a lower data refresh rate in the pixel circuit can exacerbate bias problems, a solution is to address this issue. When F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (xd1 < xd2). This allows for multiple bias adjustments to the second pixel circuit 102 within the second data write frame, effectively correcting the more severe bias problem through a relatively larger number of adjustments. Conversely, the first pixel circuit 101 has a higher data refresh rate and a less severe bias problem, allowing for fewer bias adjustments within the first data write frame. Alternatively, when F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (Wde1 < Wde2). This allows for a longer duration of a single bias adjustment within the second data write frame, effectively correcting the more severe bias problem through a longer adjustment period. Since the data refresh rate of the first pixel circuit 101 is relatively high, the bias problem is relatively milder. Therefore, the time length of a single bias adjustment of the first pixel circuit 101 within the first data writing frame can be appropriately shorter.

[0082] For example, a data write frame may contain one or more valid pulses of bias adjustment control signals.

[0083] For example, F1 = 60Hz, F2 = 30Hz, xd1 = 2, xd2 = 3, Wde1 = Wde2 = 5ms.

[0084] For example, F1 = 60 Hz, F2 = 30 Hz, xd1 = xd2 = 2, Wde1 = 5 ms, Wde2 = 10 ms.

[0085] Of course, the values ​​in the above examples are merely examples and are not intended to limit this application.

[0086] In some embodiments, F1 > F2, and 1 / 3 ≤ xd1 / xd2 < 1. That is, the maximum number of bias adjustments to the second pixel circuit 102 within the second data write frame can be three times the number of bias adjustments to the first pixel circuit 101 within the first data write frame.

[0087] In some embodiments, F1 > F2, and 1 / 3 ≤ Wde1 / Wde2 < 1. That is, the maximum duration of a single bias adjustment of the second pixel circuit 102 within the second data write frame can be three times the duration of a single bias adjustment of the first pixel circuit 101 within the first data write frame.

[0088] Understandably, for the first pixel circuit 101 and the second pixel circuit 102, the bias adjustment in the data writing frame needs to address the bias problem of the pixel circuits in the data writing frame. However, the duration of the non-light-emitting phase within the data writing frame is limited. If xd1 / xd2 or Wde1 / Wde2 is too small, the bias problem of the first pixel circuit 101 in the first data writing frame may not be resolved. Optionally, F1 > F2, 1 / 2 ≤ xd1 / xd2 < 1, and / or 1 / 2 ≤ Wde1 / Wde2 < 1, to effectively address the bias problems of both the first pixel circuit 101 in the first data writing frame and the second pixel circuit 102 in the second data writing frame.

[0089] As mentioned earlier, the effective pulse length of different hold-frame bias adjustment control signals corresponding to different pixel circuits can be different.

[0090] In some embodiments, the holding frame of the data refresh cycle of the first pixel circuit 101 is a first holding frame, in which the sum of the effective pulse durations of the bias adjustment control signal is Wh1. The holding frame of the data refresh cycle of the second pixel circuit 102 is a second holding frame, in which the sum of the effective pulse durations of the bias adjustment control signal is Wh2. Wherein, Wh1 ≠ Wh2.

[0091] In some embodiments, F1 > F2, Wh1 < Wh2.

[0092] Because a lower data refresh rate in the pixel circuit can exacerbate bias problems, a solution is to address this issue. When F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (Wh1 < Wh2). This allows for a longer bias adjustment period for the second pixel circuit 102 within the second hold frame, enabling the correction of the more severe bias problem through a longer adjustment time. Conversely, the first pixel circuit 101 has a higher data refresh rate and a less severe bias problem, allowing for a shorter bias adjustment period within the first hold frame.

[0093] In some embodiments, the number of valid pulses of the bias adjustment control signal in the first hold frame and the second hold frame, and / or the duration of a single valid pulse of the bias adjustment control signal in the first hold frame and the second hold frame, can be adjusted such that Wh1≠Wh2.

[0094] For example, a first hold frame includes xh1 valid pulses of bias adjustment control signals, where xh1 ≥ 1; wherein the duration of at least one valid pulse of the bias adjustment control signal is Whe1. A second hold frame includes xh2 valid pulses of bias adjustment control signals, where xh2 ≥ 1; wherein the duration of at least one valid pulse of the bias adjustment control signal is Whe2. Where xh1 ≠ xh2, and / or Whe1 ≠ Whe2, such that Wh1 ≠ Wh2.

[0095] In some embodiments, F1 > F2, xh1 < xh2; and / or, F1 > F2, Whe1 < Whe2.

[0096] Because a lower data refresh rate in the pixel circuit can exacerbate bias problems, a solution is to address this issue. When F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (xh1 < xh2). This allows for multiple bias adjustments to the second pixel circuit 102 within the second hold frame, effectively correcting the more severe bias problem through a relatively larger number of adjustments. Conversely, the first pixel circuit 101 has a higher data refresh rate and a less severe bias problem, allowing for fewer bias adjustments to be made within the first hold frame. Alternatively, when F1 > F2, the second pixel circuit 102 has a lower data refresh rate and a more severe bias problem (Whe1 < Whe2). This allows for a longer duration of a single bias adjustment within the second hold frame, effectively correcting the more severe bias problem through a longer adjustment period. Since the data refresh rate of the first pixel circuit 101 is relatively high, the bias problem is relatively milder. Therefore, the time length of a single bias adjustment of the first pixel circuit 101 within the first holding frame can be appropriately shorter.

[0097] In some embodiments, F1 > F2, and 1 / 3 ≤ xh1 / xh2 < 1. That is, the maximum number of bias adjustments to the second pixel circuit 102 within the second holding frame can be three times the number of bias adjustments to the first pixel circuit 101 within the first holding frame.

[0098] In some embodiments, F1 > F2, and 1 / 3 ≤ Whe1 / Whe2 < 1. That is, the maximum duration of a single bias adjustment of the second pixel circuit 102 within the second holding frame can be three times the duration of a single bias adjustment of the first pixel circuit 101 within the first holding frame.

[0099] Understandably, for the first pixel circuit 101 and the second pixel circuit 102, the bias adjustment in the holding frame needs to address the bias problem of the pixel circuits in the holding frame. However, the duration of the non-light-emitting phase within the holding frame is limited. If xh1 / xh2 or Whe1 / Whe2 is too small, the bias problem of the first pixel circuit 101 in the first holding frame may not be resolved. Optionally, F1 > F2, 1 / 2 ≤ xh1 / xh2 < 1, and / or 1 / 2 ≤ Whe1 / Whe2 < 1, to ensure that the bias problems of the first pixel circuit 101 in the first holding frame and the second pixel circuit 102 in the second holding frame are both effectively resolved.

[0100] In some embodiments, for at least one of the first pixel circuit 101 and the second pixel circuit 102, multiple effective pulses of bias adjustment control signals may be included during the data refresh cycle of the pixel circuit. As time increases, the bias problem may become more severe. To address this problem, such as... Figure 5 As shown, taking the effective pulse of the bias adjustment control signal as low level as an example, the duration of the effective pulse of the bias adjustment control signal can be gradually increased.

[0101] In some embodiments, the display panel can be divided into zones to display frequencies. For example, such as Figure 6 As shown, the display panel may include a first display area A1 and a second display area A2, with a first pixel circuit 101 located in the first display area A1 and a second pixel circuit 102 located in the second display area A2.

[0102] The data refresh frequency of the first pixel circuit 101 is a first frequency F1, and the data refresh frequency of the second pixel circuit is a second frequency F2, where F1 ≠ F2. The first display area A1 and the second display area A2 can be displayed based on different refresh frequencies.

[0103] For example, if F1 > F2, the first display area A1 can display game screens, movie screens, etc. at a higher refresh rate, while the second display area A2 can display text, time information, etc. at a lower refresh rate.

[0104] In other embodiments, the display panel may display data in a time-division and frequency-division manner. The display panel may include a first data refresh phase and a second data refresh phase, with the first mode being the first data refresh phase and the second mode being the second data refresh phase. The data refresh frequency of the first data refresh phase is a first frequency F1, and the data refresh frequency of the second data refresh phase is a second frequency F2.

[0105] The same pixel circuit can be displayed in time-sharing and frequency-sharing modes. For example... Figure 7As shown, during the first data refresh phase, the pixel circuits of the display panel can all be the first pixel circuit 101, and during the second data refresh phase, the pixel circuits of the display panel can all be the second pixel circuit 102.

[0106] In some embodiments, such as Figures 1 to 4 As shown, the pixel circuit includes a data writing module 111, which provides a data signal Vdata to the driving transistor T0. The screen refresh frame is either a data writing frame or a hold frame; in a data writing frame, the data writing module 111 writes the data signal Vdata to the gate of the driving transistor T0. In a hold frame, the data writing module 111 does not write the data signal Vdata to the gate of the driving transistor T0.

[0107] In some embodiments, such as Figures 1 to 4 As shown, the pixel circuit includes a data writing module 111; the data writing module 111 is connected to the first pole (i.e., node N2) of the driving transistor T0; the bias adjustment module 114 is connected to the first pole (i.e., node N2) or the second pole (i.e., node N3) of the driving transistor T0.

[0108] The working process of the display panel includes a data writing stage and a bias adjustment stage;

[0109] During the data writing phase, the data writing module 111 is turned on, and the bias adjustment module 114 is turned off. The data writing module 111 provides the data signal Vdata to the driving transistor T0. During the bias adjustment phase, the bias adjustment module 114 is turned on, and the data writing module 111 is turned off. The bias adjustment module 114 provides the bias adjustment signal DVH to the driving transistor T0.

[0110] Optionally, in this embodiment, the control terminal of the data writing module 111 in the first pixel circuit 101 receives a scan signal S11, which controls the opening and closing of the data writing module 111. The control terminal of the bias adjustment module 114 in the first pixel circuit 101 receives a bias adjustment signal S14, which controls the opening and closing of the bias adjustment module 114. The control terminal of the data writing module 111 in the second pixel circuit 102 receives a scan signal S21, which controls the opening and closing of the data writing module 111. The control terminal of the bias adjustment module 114 in the second pixel circuit 102 receives a bias adjustment signal S24, which controls the opening and closing of the bias adjustment module 114.

[0111] In other embodiments, such as Figure 8 or Figure 9As shown, the bias adjustment module 114 is multiplexed as a data writing module. The operation of the display panel includes a data writing stage and a bias adjustment stage; during the data writing stage, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a data signal Vdata to the driving transistor T0; during the bias adjustment stage, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a bias adjustment signal DVH to the driving transistor T0.

[0112] In this embodiment, the bias adjustment module 114 can transmit both the bias adjustment signal DVH to the driving transistor T0 and the data signal Vdata to the driving transistor T0.

[0113] Optionally, in this embodiment, the control terminal of the bias adjustment module 114 in the first pixel circuit 101 receives a bias adjustment signal S14, which controls the opening and closing of the bias adjustment module 114 in the first pixel circuit 101. Under the control of the first valid pulse of the bias adjustment signal S14, the bias adjustment module 114 in the first pixel circuit 101 is turned on to provide a bias adjustment signal DVH to the driving transistor T0; under the control of the second valid pulse of the bias adjustment signal S14, the bias adjustment module 114 in the first pixel circuit 101 is turned on to provide a data signal Vdata to the driving transistor T0. The control terminal of the bias adjustment module 114 in the second pixel circuit 102 receives a bias adjustment signal S24, which controls the opening and closing of the bias adjustment module 114 in the second pixel circuit 102. Under the control of the first effective pulse of the bias adjustment signal S24, the bias adjustment module 114 in the second pixel circuit 102 is turned on to provide the bias adjustment signal DVH to the driving transistor T0; under the control of the second effective pulse of the bias adjustment signal S24, the bias adjustment module 114 in the second pixel circuit 102 is turned on to provide the data signal Vdata to the driving transistor T0.

[0114] It should be noted that, as Figure 8 As shown, the driving transistor T0 is a P-type transistor, and the bias adjustment module 114 is connected to the first terminal of the driving transistor T0. Figure 9 As shown, the driving transistor T0 is an N-type transistor, and the bias adjustment module 114 is connected to the first terminal of the driving transistor T0.

[0115] In some embodiments, such as Figures 1 to 4 ,as well as Figure 8 , Figure 9As shown, the pixel circuit may further include a reset module 113, an initialization module 117, a light emission control module 115, and a compensation module 112. The reset module 113 is used to provide a reset signal Vref to the driving transistor T0; the initialization module 117 is used to provide an initialization signal Vini to the driving transistor T0; the light emission control module 115 is used to selectively allow the light-emitting element 20 to enter the light emission stage; the compensation module 112 is connected between the gate and the second terminal (i.e., node N3) of the driving transistor T0.

[0116] Optionally, the light-emitting control module 115 includes a first light-emitting control module 1151 and a second light-emitting control module 1152. The first light-emitting control module 1151 is connected to the first power signal terminal and the first terminal of the driving transistor T0 (e.g., ...). Figure 1 and Figure 2 (as shown) or the second pole (such as) Figure 3 and Figure 4 Between (as shown), a first power signal PVDD is provided to the driving transistor T0, and the second light-emitting control module 1152 is connected to the first terminal of the driving transistor T0 (as shown). Figure 3 and Figure 4 (as shown) or the second pole (such as) Figure 1 and Figure 2 The light-emitting control module 115 (as shown) is positioned between the light-emitting control module 115 and the light-emitting element 20 to selectively allow driving current to enter the light-emitting element 20. Since the on / off state of the light-emitting control module 115 controls whether the light-emitting element emits light, and there is a process of the light-emitting element being turned on and off within a subframe cycle, the on / off state of the light-emitting control module 115 generally needs to be consistent with the frequency of the subframe. Therefore, the frequency change of the control signal of the light-emitting control module 115 is different from the change of the data refresh frequency. In this embodiment, the control signal of the light-emitting control module 115 in the first pixel circuit 101 is EM1, and the control signal of the light-emitting control module 115 in the second pixel circuit 102 is EM2.

[0117] Optionally, the data writing module 111 may include a data writing transistor T1. In the first pixel circuit 101, the gate of the data writing transistor T1 is used to receive a control signal S11; in the second pixel circuit 102, the gate of the data writing transistor T1 is used to receive a control signal S12.

[0118] Optionally, the bias adjustment module 114 may include a transistor T4. In the first pixel circuit 101, the gate of the transistor T4 is used to receive the bias adjustment control signal S14; in the second pixel circuit 102, the gate of the transistor T4 is used to receive the bias adjustment control signal S24.

[0119] Optionally, the compensation module 112 may include a compensation transistor T2. In the first pixel circuit 101, the gate of the compensation transistor T2 is used to receive the control signal S12; in the second pixel circuit 102, the gate of the compensation transistor T2 is used to receive the control signal S22.

[0120] Optionally, the reset module 113 may include a reset transistor T3. In the first pixel circuit 101, the gate of the reset transistor T3 is used to receive the control signal S13; in the second pixel circuit 102, the gate of the reset transistor T3 is used to receive the control signal S23.

[0121] Optionally, the initialization module 117 may include an initialization transistor T7. In the first pixel circuit 101, the gate of the initialization transistor T7 is used to receive the control signal S15; in the second pixel circuit 102, the gate of the initialization transistor T7 is used to receive the control signal S25.

[0122] Optionally, the first light-emitting control module 1151 includes a first light-emitting control transistor T5, and the second light-emitting control module 1152 includes a second light-emitting control transistor T6. In the first pixel circuit 101, the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to receive a control signal EM1; in the second pixel circuit 102, the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to receive a control signal EM2.

[0123] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of this application are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0124] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 10 , Figure 10This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 The provided display device 1000 includes a display panel 100, which can be the display panel described in any of the foregoing embodiments. Figure 10 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0125] Based on the above description, the display panel and display device provided in this application include a pixel circuit and a light-emitting element 20. The pixel circuit includes a driving module 110 and a bias adjustment module 114. The driving module 110 includes a driving transistor T0. The control terminal of the bias adjustment module 114 receives a bias adjustment control signal. When the bias adjustment control signal is a valid pulse signal, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a bias adjustment signal DVH to the driving transistor T0.

[0126] The operation of the pixel circuit 10 includes a first mode and a second mode. The pixel circuit operating in the first mode is the first pixel circuit 101, and the pixel circuit operating in the second mode is the second pixel circuit 102.

[0127] The data refresh frequency of the first pixel circuit 101 is the first frequency F1, and the data refresh frequency of the second pixel circuit 102 is the second frequency F2, where F1 ≠ F2.

[0128] The data refresh cycle of the first pixel circuit 101 includes R1 screen refresh frames, and the data refresh cycle of the second pixel circuit 102 includes R2 screen refresh frames, where R1≥1 and R2≥1.

[0129] During the data refresh cycle of the first pixel circuit 101, the total duration of the effective pulses of the first bias adjustment control signal S14 is Ws1, and during the data refresh cycle of the second pixel circuit 102, the total duration of the effective pulses of the second bias adjustment control signal S24 is Ws2; wherein, Ws1 / R1≠Ws2 / R2.

[0130] When the bias adjustment control signal is a valid pulse signal, the bias adjustment module 114 is turned on, and the bias adjustment module 114 provides a bias adjustment signal DVH to the driving transistor T0, where Ws1 / R1 ≠ Ws2 / R2. Because the bias adjustment signal is a signal received by the pixel circuit to adjust the bias state of the driving transistor, when the bias adjustment control signal is a valid pulse signal, the bias adjustment signal DVH is transmitted to the driving transistor T0. The duration of the valid pulse signal affects the adjustment duration of the driving transistor's bias state. If the first pixel circuit 101 and the second pixel circuit 102 have different functions, resulting in different bias states of the driving transistors, then different durations of the valid pulse signals of the bias adjustment control signal are needed to adjust the bias states of the driving transistors in the first pixel circuit 101 and the second pixel circuit 102 respectively, thereby optimizing the functions of each pixel circuit.

[0131] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a bias adjustment module; The driving module includes a driving transistor; The control terminal of the bias adjustment module receives a bias adjustment control signal. When the bias adjustment control signal is a valid pulse signal, the bias adjustment module is turned on, and the bias adjustment module provides a bias adjustment signal to the driving transistor. The operation of the pixel circuit includes a first mode and a second mode. The pixel circuit operating in the first mode is the first pixel circuit, and the pixel circuit operating in the second mode is the second pixel circuit. The display panel includes a first display area and a second display area, wherein the first pixel circuit is located in the first display area and the second pixel circuit is located in the second display area; The data refresh frequency of the first pixel circuit is a first frequency F1, and the data refresh frequency of the second pixel circuit is a second frequency F2, where F1 ≠ F2; The data refresh cycle of the first pixel circuit includes R1 frame refreshes, and the data refresh cycle of the second pixel circuit includes R2 frame refreshes, where R1≥1 and R2≥1. Within the data refresh cycle of the first pixel circuit, the total duration of the effective pulses of the bias adjustment control signal is Ws1; within the data refresh cycle of the second pixel circuit, the total duration of the effective pulses of the bias adjustment control signal is Ws2; wherein... Ws1 / R1≠Ws2 / R2; The screen refresh frame includes a data write frame and a hold frame; The display panel must satisfy at least one of the following: At different data refresh frequencies, the effective pulse length of the bias adjustment control signal written into the frame is the same; or, At different data refresh frequencies, the effective pulse length of the offset adjustment control signal within the hold frame is the same.

2. The display panel according to claim 1, characterized in that, F1 > F2, Ws1 / R1 < Ws2 / R2.

3. The display panel according to claim 1, characterized in that, The R1 frame refreshes in the data refresh cycle of the first pixel circuit include r1 data write frames and r2 hold frames, where r1≥1 and r2>0; The R2 frame refresh cycles in the data refresh cycle of the second pixel circuit include r3 data write frames and r4 hold frames, where r3≥1 and r4>0; The sum of the effective pulse lengths of the bias adjustment control signal in the r1 data write frames is Wr1, and Wr1 / r1≥0; The sum of the effective pulse lengths of the bias adjustment control signal in the r2 hold frames is Wr2, and Wr2 / r2≥0; The sum of the effective pulse lengths of the bias adjustment control signal in the r3 data write frames is Wr3, and Wr3 / r3≥0; The sum of the effective pulse lengths of the bias adjustment control signal in the r4 hold frames is Wr4; where Wr4 / r4≥0; where... At least two of Wr1 / r1, Wr2 / r2, Wr3 / r3, and Wr4 / r4 are not equal.

4. The display panel according to claim 3, characterized in that, Wr1 / r1≠Wr2 / r2, and / or, Wr3 / r3≠Wr4 / r4.

5. The display panel according to claim 4, characterized in that, Wr1 / r1 < Wr2 / r2, and / or, Wr3 / r3 < Wr4 / r4.

6. The display panel according to claim 5, characterized in that, F1 > F2, r2 < r4.

7. The display panel according to claim 3, characterized in that, Wr1 / r1≠Wr3 / r3, and / or, Wr2 / r2≠Wr4 / r4.

8. The display panel according to claim 7, characterized in that, F1 > F2, Wr1 / r1 < Wr3 / r3; and / or, F1>F2, Wr2 / r2<Wr4 / r4.

9. The display panel according to claim 7, characterized in that, The data write frame in the data refresh cycle of the first pixel circuit is the first data write frame. In one first data write frame, the total duration of the effective pulses of the bias adjustment control signal is Wd1. The data write frame in the data refresh cycle of the second pixel circuit is the second data write frame. In one second data write frame, the sum of the effective pulse durations of the bias adjustment control signal is Wd2; where, Wd1≠Wd2.

10. The display panel according to claim 9, characterized in that, F1>F2,Wd1<Wd2。 11. The display panel according to claim 9, characterized in that, A first data write frame includes xd1 valid pulses of bias adjustment control signals, where xd1 ≥ 1; wherein, the duration of at least one valid pulse of bias adjustment control signal is Wde1; A second data write frame includes xd2 valid pulses of bias adjustment control signals, where xd2 ≥ 1; where... The effective pulse duration of at least one bias adjustment control signal is Wde2; where, xd1≠xd2, and / or Wde1≠Wde2.

12. The display panel according to claim 11, characterized in that, F1 > F2, xd1 < xd2; and / or, F1 > F2, Wde1 < Wde2.

13. The display panel according to claim 11, characterized in that, F1>F2, 1 / 3≤xd1 / xd2<1.

14. The display panel according to claim 11, characterized in that, F1>F2, 1 / 3≤Wde1 / Wde2<1.

15. The display panel according to claim 7, characterized in that, The holding frame of the data refresh cycle of the first pixel circuit is the first holding frame. In one first holding frame, the total time length of the effective pulses of the bias adjustment control signal is Wh1. The holding frame of the data refresh cycle of the second pixel circuit is the second holding frame. In one second holding frame, the total duration of the effective pulses of the bias adjustment control signal is Wh2; wherein, Wh1 ≠ Wh2.

16. The display panel according to claim 15, characterized in that, F1 > F2, Wh1 < Wh2.

17. The display panel according to claim 15, characterized in that, A first hold frame includes xh1 valid pulses of bias adjustment control signals, where xh1 ≥ 1; wherein the duration of at least one valid pulse of bias adjustment control signal is Whe1; A second hold frame includes xh2 valid pulses of bias adjustment control signals, where xh2 ≥ 1; wherein, the duration of at least one valid pulse of the bias adjustment control signal is Whe2; wherein... xh1≠xh2, and / or Whe1≠Whe2.

18. The display panel according to claim 17, characterized in that, F1 > F2, xh1 < xh2; and / or, F1 > F2, Whe1 < Whe2.

19. The display panel according to claim 18, characterized in that, F1>F2, 1 / 3≤xh1 / xh2<1.

20. The display panel according to claim 18, characterized in that, F1>F2, 1 / 3≤Whe1 / Whe2<1.

21. The display panel according to claim 1, characterized in that, The pixel circuit includes a data writing module; The data writing module is used to provide data signals to the driving transistor; The screen refresh frame is a data write frame or a hold frame; In the data writing frame, the data writing module writes a data signal to the gate of the driving transistor; During the holding frame, the data writing module does not write data signals to the gate of the driving transistor.

22. The display panel according to claim 1, characterized in that, The pixel circuit includes a data writing module; The data writing module is connected to the first electrode of the driving transistor; The bias adjustment module is connected to the first or second terminal of the driving transistor; The operation of the display panel includes a data writing stage and a bias adjustment stage; During the data writing phase, the data writing module is turned on, the bias adjustment module is turned off, and the data writing module provides a data signal to the driving transistor. During the bias adjustment phase, the bias adjustment module is turned on, the data writing module is turned off, and the bias adjustment module provides a bias adjustment signal to the driving transistor.

23. The display panel according to claim 1, characterized in that, The bias adjustment module is reused as a data writing module; The operation of the display panel includes a data writing stage and a bias adjustment stage; During the data writing phase, the bias adjustment module is activated, and the bias adjustment module provides a data signal to the driving transistor; During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module provides a bias adjustment signal to the driving transistor.

24. The display panel according to claim 1, characterized in that, The pixel circuit also includes a reset module, an initialization module, a light emission control module, and a compensation module; The reset module is used to provide a reset signal to the driving transistor; The initialization module is used to provide initialization signals to the driving transistor; The light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting stage; The compensation module is connected between the gate and the second electrode of the driving transistor.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1-24.

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