An overcurrent protection circuit for a transistor

Abstract

The application discloses a kind of transistor overcurrent protection circuit, there are two protection mechanisms: inverter peak current limit and starting ability limit. Among them, inverter peak current limit ensures that when driving multiple devices or starting devices with large current, the inverter will not stop working directly, but wait for the device to start completely in the loop again;Starting ability limit is a further protection measure for the pneumatic capacity of the inverter based on the inverter peak current limit.

Description

Technical Field

[0001] This invention relates to the field of overcurrent protection technology, and more particularly to an overcurrent protection circuit for a transistor. Background Technology

[0002] Inverters, as a common type of DC-to-AC converter, utilize many transistors in their DC-AC energy conversion. These transistors require overcurrent protection circuits to prevent irreversible damage to the inverter itself should a connected device malfunction or short circuit occur. However, for devices connecting multiple devices or those requiring significant starting current, such protection circuits may prevent the devices from starting properly.

[0003] Most common inverters currently available do not have built-in transistor hardware protection; instead, they rely on software monitoring of the output current to adjust the transistor control signal. Additionally, for scenarios involving multiple connected devices, it's possible to avoid triggering overcurrent protection by starting each device individually, but this requires manual intervention.

[0004] This software-based approach to detecting output current feedback control signals carries certain risks. When the monitored signal is abnormal or interfered with, the software can malfunction and cause the transistors to explode. To ensure the normal startup of multiple devices, manual intervention is required to power them on one by one. However, this method cannot be used when the device is a single motor or other load. Summary of the Invention

[0005] The purpose of this invention is to provide a solution to the problems in the prior art.

[0006] To achieve the objectives of this invention, the technical solution adopted is as follows:

[0007] An overcurrent protection circuit for a transistor includes an inverter peak current limiting circuit. One end of the inverter peak current limiting circuit is electrically connected to one end of a first resistor, a device initialization protection circuit, and one end of an inverter start-up capability limiting circuit. One end of the inverter peak current limiting circuit has a first interface electrically connected to a logic gate circuit. The other end of the inverter peak current limiting circuit is electrically connected to the other end of the inverter start-up capability limiting circuit, and the other end of the inverter peak current limiting circuit has a second interface. The other end of the first resistor is electrically connected to the inverter peak current limiting circuit, the device initialization protection circuit, and the inverter start-up capability limiting circuit. The inverter start-up capability limiting circuit includes a capacitor charging / discharging circuit and a D flip-flop triggering circuit.

[0008] Furthermore, the inverter peak current limiting circuit includes a first optocoupler, the first pin of which is electrically connected to one end of a fourth resistor, the other end of which is electrically connected to one end of a second resistor, one end of a third capacitor, one end of a third resistor, the eighth pin of a first comparator, and an inverter start-up capability limiting circuit. The other end of the third resistor is electrically connected to the second pin of the first optocoupler and the first pin of the first comparator. The third pin of the first optocoupler is electrically connected to one end of the first capacitor and ground. The other end of the first capacitor is electrically connected to one end of a fifth resistor, the cathode of a second diode, and the fourth pin of the first optocoupler. The other end of the fifth resistor is electrically connected to the other end of the first resistor and the inverter start-up capability limiting circuit. The anode of the second diode is electrically connected to one end of the first resistor and a device initialization protection circuit. The fourth pin of the first comparator is grounded. The third pin of the first comparator is electrically connected to the other end of the second resistor and one end of a ninth resistor, the other end of the ninth resistor is grounded. The second pin of the first comparator is electrically connected to one end of the eighth resistor and one end of a seventh resistor, the other end of the eighth resistor is grounded. The other end of the seventh resistor is electrically connected to the inverter start-up capability limiting circuit. The other end of the third capacitor is grounded.

[0009] Furthermore, a second interface is provided at the other end of the seventh resistor, and a first interface is provided at the anode of the second diode.

[0010] Furthermore, the ninth resistor is a variable resistor.

[0011] Furthermore, the capacitor charging and discharging circuit includes a second optocoupler. The first pin of the second optocoupler is electrically connected to one end of the thirteenth resistor. The other end of the thirteenth resistor is electrically connected to one end of the eighteenth resistor, one end of the twelfth resistor, and the inverter peak current limiting circuit. The other end of the eighteenth resistor is electrically connected to the second pin of the second optocoupler and the seventh pin of the second comparator. The third pin of the second optocoupler is electrically connected to one end of the fifth capacitor and ground. The other end of the fifth capacitor is electrically connected to one end of the fourteenth resistor, the fourth pin of the second optocoupler, and the trigger circuit. The other end of the fourteenth resistor is electrically connected to the trigger circuit. The fifth pin of the second comparator is electrically connected to the other end of the twelfth resistor and one end of the twentieth resistor. The other end of the twentieth resistor is grounded. The sixth pin of the second comparator is electrically connected to one end of the seventeenth resistor, one end of the nineteenth resistor, and the positive terminal of the sixth capacitor. The negative terminal of the sixth capacitor and the other end of the nineteenth resistor are grounded. The other end of the seventeenth resistor is electrically connected to the cathode of the fifth diode. The anode of the fifth diode is electrically connected to the inverter peak current limiting circuit.

[0012] Furthermore, the anode of the fifth diode is provided with a second interface.

[0013] Furthermore, the twentieth resistor is a variable resistor.

[0014] Furthermore, the D flip-flop triggering circuit includes a D flip-flop. The first pin of the D flip-flop is electrically connected to the anode of the sixth diode. The cathode of the sixth diode is electrically connected to the cathode of the fourth diode, one end of the fifteenth resistor, and the capacitor charging / discharging circuit. The third pin of the D flip-flop is electrically connected to one end of the eleventh resistor and the collector of the second transistor. The base of the second transistor is electrically connected to the other end of the fifteenth resistor. The emitter of the second transistor is electrically connected to the seventh pin, fifth pin, and fourth pin of the D flip-flop, the emitter of the first transistor, one end of the fourth capacitor, and ground. The collector of the first transistor is electrically connected to the sixth pin of the D flip-flop and one end of the tenth resistor. The base of the first transistor is electrically connected to one end of the sixteenth resistor and the other end of the fourth capacitor. The other end of the sixteenth resistor is provided with a reset pin. The fourteenth pin of the D flip-flop, the other end of the eleventh resistor, and the other end of the tenth resistor are all electrically connected to the other end of the first resistor, the capacitor charging / discharging circuit, and the inverter peak current limiting circuit. The anode of the fourth diode is electrically connected to one end of the first resistor.

[0015] Furthermore, the anode of the fourth diode is provided with a first interface.

[0016] Furthermore, the device initialization protection circuit includes a third diode. The anode of the third diode is electrically connected to one end of the first resistor and the inverter peak current limiting circuit. The cathode of the third diode is electrically connected to the anode of the first diode, the positive terminal of the second capacitor, and one end of the sixth resistor. The cathode of the first diode is electrically connected to the other end of the first resistor, the inverter peak current limiting circuit, and the inverter start-up capability limiting circuit. The negative terminal of the second capacitor and the other end of the sixth resistor are grounded.

[0017] Compared with the prior art, the advantages of the present invention are as follows:

[0018] It can improve the starting capability of the load without overcurrent in the transistor; it does not require software intervention for regulation, and the transistor is overcurrent protected by limiting the inverter's peak current and starting capability through the circuit; it provides two protection mechanisms for better overcurrent protection; in the event of an actual equipment failure, it can promptly and effectively disconnect the electrical connection between the inverter and the faulty equipment, thereby ensuring the safety of the inverter. Attached Figure Description

[0019] Figure 1 This is a diagram of a transistor overcurrent protection circuit.

[0020] Figure 2 This is a circuit diagram for limiting the peak current of an inverter.

[0021] Figure 3 Circuit diagram for limiting inverter startup capability;

[0022] Figure 4 Initialize the protection circuit diagram for the device;

[0023] Figure 5 This is a screenshot of the truth table from the manual for a D flip-flop. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes an overcurrent protection circuit for a transistor according to the present invention:

[0025] This design incorporates two protection mechanisms:

[0026] I. Inverter Peak Current Limitation. The inverter output current is cut off the instant it exceeds a set threshold. Since there is an inductor on the inverter's H-bridge, the current across it changes gradually. If the output current subsequently returns below the threshold, the inverter continues to operate normally; otherwise, this process is repeated. This design limits the inverter's output current to a set threshold while ensuring that the inverter does not stop working directly when driving multiple devices or devices with high initial current during startup. Instead, it continuously cycles, waiting for the devices to fully start. The number of cycles, i.e., the inverter's startup capability, is controlled by the following protection mechanism.

[0027] II. Start-up Capacity Limitation. As mentioned above, the inverter limits the peak current without stopping the output to ensure the connected equipment starts up gradually. However, if this continues for an extended period, it indicates that the connected equipment is overloaded, making normal startup difficult, or that the equipment has malfunctioned. In this case, the start-up capacity limiting circuit will completely cut off the inverter output. The inverter will not resume operation without manual reset. The start-up capacity threshold is adjustable and can be adjusted according to actual conditions.

[0028] Its circuit structure and principle are as follows:

[0029] I. Inverter Peak Current Limiting Circuit

[0030] like Figure 2 As shown, IBUS is the sampled value of the current on the H-bridge (inverter output); U2 is a comparator of model LM393; R7, R8 and R2, R9 are the voltage divider resistors for the two input terminals of the comparator, where R9 is an adjustable resistor; C3 is the filter capacitor for the power input terminal of the comparator; U1 is an optocoupler of model TLP785; R3 is a pull-up resistor, R4 is a current-limiting resistor on the input side of the optocoupler; R5 is a pull-up resistor on the output side of the optocoupler, C1 is a filter capacitor; D2 is a diode; R1 is a pull-up resistor;

[0031] Principle: The H-bridge has an inductor, and the current flowing through it changes gradually, not instantaneously. The value on the IBUS pin reflects the magnitude of the current in the H-bridge, i.e., the magnitude of the inverter's output current.

[0032] The IGBT pins are connected to external logic gates to control the on / off state of the IGBTs (Insulated Gate Bipolar Transistors) on the H-bridge. The logic can be summarized as follows: when the pin is high, the IGBT can be turned on by the CPU. When the pin is low, the IGBT is not turned on, and the inverter stops outputting.

[0033] Pin 3 of comparator U2 serves as the reference voltage, which is the set peak current threshold. Its magnitude can be changed via adjustable resistor R9. Pin 2 represents the IBU voltage after resistor division. When the current in the H-bridge exceeds the set threshold (i.e., the voltage at pin 2 is greater than the voltage at pin 3), the comparator outputs a low level. At this time, optocoupler U1 conducts, the IGBT pin is connected to ground, and the output is low, stopping the inverter's output. When the current in the H-bridge falls below the set threshold, the comparator outputs a high level, the optocoupler deconducts, the IGBT pin is pulled high through resistor R1, and the inverter resumes output. Diode D2 is used to prevent the voltage on the optocoupler output side from affecting subsequent circuitry.

[0034] The logic of this circuit is as follows: Under normal operating conditions, the inverter maintains output. When the inverter output current exceeds a set threshold, the inverter is temporarily stopped from outputting, and then restarted once the output current drops below the threshold. If a large current still occurs at this time, this process is repeated.

[0035] II. Inverter Start-up Capability Limiting Circuit

[0036] like Figure 3 As shown, this circuit consists of two parts.

[0037] Part 1: D5 is a diode, C6 is a 22μF / 50V electrolytic capacitor; R17, R19 and R12, R20 are the voltage divider resistors for the two input terminals of the comparator, where R20 is an adjustable resistor; U2 is the other channel of the LM393 comparator; R18 is a pull-up resistor, R13 is a current-limiting resistor; U4 is a TLP785 optocoupler, R14 is a pull-up resistor on the output side of the optocoupler, and C5 is a filter capacitor.

[0038] Principle: Pin 5 of comparator U2 serves as the reference voltage, which is the set startup capability threshold. Its value can be changed via adjustable resistor R19. When the inverter has output, IBUS charges the capacitor through resistor R17; when the inverter stops outputting, the capacitor discharges through resistor R19. The resistance of resistor R17 is much smaller than that of R19, ensuring that the capacitor charging time is shorter than the capacitor discharging time.

[0039] Under normal operating conditions, the voltage at pin 6 of U2 is the value obtained by subtracting the voltage drop across diode D5 from IBUS and then dividing the voltage across the resistor. Even when the capacitor is fully charged, its voltage is still lower than the threshold voltage. At this time, the comparator outputs a high level, optocoupler U4 is not conducting, and node Uh is at a high level (the output voltage of optocoupler U4).

[0040] When the inverter output current exceeds the set peak value, the IBUS voltage increases, capacitor C6 charges further, and the voltage value of "pin 6" gradually rises. Due to the presence of the peak current limiting circuit, the increased IBUS voltage will only exist for a moment, and the capacitor charging takes time (determined by the values ​​of resistor R17 and capacitor). Therefore, the voltage of "pin 6" will not exceed the set threshold, and node Uh remains high.

[0041] Only when the inverter outputs peak power for a certain period of time, i.e., the peak current limiting circuit cycles a certain number of times, will the voltage of capacitor C6 exceed the set threshold. At this time, the comparator outputs a low level, optocoupler U4 conducts, and node Uh is at a low level. Adjusting the start-up capability threshold controls how many cycles are needed before the protection action is triggered.

[0042] Part Two: Pin CPU_FW is the manual reset pin; under normal conditions, the CPU outputs a high level. U3 is a D flip-flop of model MC14013B. R15 and R16 are current-limiting resistors. R10 and R11 are pull-up resistors. V1 and V2 are transistors of model MMBT4401. D4 and D6 are diodes. The truth table for U3 is as follows: Figure 5 ;

[0043] Principle: The Data and Reset pins of the D flip-flop are kept at a low level in the design.

[0044] ①In the initial state, the Data and Reset pins are 0, and the Set pin is pulled high by R10. At this time, the flip-flop pin Q outputs a high level.

[0045] ② Under normal operating conditions, the CPU outputs a high level to the CPU_FW pin, which turns on transistor V1 and sets the SET pin to a low level. At this time, the flip-flop does not activate, and pin Q still outputs a high level.

[0046] ③ When the Uh voltage is high, transistor V2 is turned on, and pin CLK is set to low; when the Uh voltage jumps to low, V2 is not turned on, and pin CLK is pulled up to high by R11. At this time, CLK has a rising edge, and the Data, Reset, and Set pins are all low, and the flip-flop pin Q will maintain a low output level.

[0047] ④ When the trigger pin Q is low, the IGBT pin is pulled low. At this time, the IGBTs on the H-bridge are simultaneously turned off, and the inverter stops outputting.

[0048] ⑤ The CPU sends a reset signal, that is, it outputs a low level to the CPU_FW pin, the transistor V1 is not turned on, and the SET pin is pulled up to a high level. At this time, the flip-flop pin Q outputs a high level, the flip-flop returns to its normal state, and the H-bridge returns to its original normal working state.

[0049] The logic of this circuit is as follows: During normal operation or when the inverter experiences a short-term peak output, this protection circuit will not activate. When the inverter experiences a prolonged peak output, the protection circuit will activate, controlling the inverter to stop outputting, and the inverter will not resume output unless a reset signal is provided by the CPU. Furthermore, the duration of the inverter's sustained peak output can be adjusted by regulating the startup capability threshold.

[0050] III. Equipment Initialization Protection Circuit

[0051] like Figure 4 As shown, the IGBT pins are connected to external logic gate circuits to control the on / off state of all IGBT transistors; R1 is a pull-up resistor, R6 is a capacitor discharge resistor; D1 and D3 are diodes; C2 is a 22μF / 50V electrolytic capacitor.

[0052] Principle: During system initialization, the 5V power supply charges capacitor C2 through resistor R1, causing the IGBT voltage at the pin to rise slowly and remain at a low level for a period of time, preventing the inverter from outputting power. This design ensures that the inverter does not malfunction during system initialization.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made by those skilled in the art to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An overcurrent protection circuit for a transistor, comprising an inverter peak current limiting circuit, characterized in that: One end of the inverter peak current limiting circuit is electrically connected to one end of the first resistor (R1), the equipment initialization protection circuit, and one end of the inverter start-up capability limiting circuit. One end of the inverter peak current limiting circuit has a first interface (IGBT), which is electrically connected to a logic gate circuit. The other end of the inverter peak current limiting circuit is electrically connected to the other end of the inverter start-up capability limiting circuit, which has a second interface (IBUS). The other end of the first resistor (R1) is electrically connected to the inverter peak current limiting circuit, the equipment initialization protection circuit, and the inverter start-up capability limiting circuit. The inverter start-up capability limiting circuit includes a capacitor charging / discharging circuit and a D flip-flop triggering circuit. The inverter peak current limiting circuit includes a first optocoupler (U1). The first pin of the first optocoupler (U1) is electrically connected to one end of a fourth resistor (R4). The other end of the fourth resistor (R4) is electrically connected to one end of a second resistor (R2), one end of a third capacitor (C3), one end of the third resistor (R3), the eighth pin of a first comparator (U2A), and the inverter start-up capability limiting circuit. The other end of the third resistor (R3) is electrically connected to the second pin of the first optocoupler (U1) and the first pin of the first comparator (U2A). The third pin of the first optocoupler (U1) is electrically connected to one end of the first capacitor (C1) and ground. The other end of the first capacitor (C1) is electrically connected to one end of a fifth resistor (R5), the cathode of a second diode (D2), and the first optocoupler (U1). The four-pin connector has the following terminals: the other end of the fifth resistor (R5) is electrically connected to the other end of the first resistor (R1) and the inverter start-up capability limiting circuit; the anode of the second diode (D2) is electrically connected to one end of the first resistor (R1) and the device initialization protection circuit; the fourth pin of the first comparator (U2A) is grounded; the third pin of the first comparator (U2A) is electrically connected to the other end of the second resistor (R2) and one end of the ninth resistor (R9), with the other end of the ninth resistor (R9) grounded; the second pin of the first comparator (U2A) is electrically connected to one end of the eighth resistor (R8) and one end of the seventh resistor (R7), with the other end of the eighth resistor (R8) grounded; the other end of the seventh resistor (R7) is electrically connected to the inverter start-up capability limiting circuit; and the other end of the third capacitor (C3) is grounded.

2. The overcurrent protection circuit for a transistor as described in claim 1, characterized in that: The other end of the seventh resistor (R7) is provided with a second interface (IBUS), and the anode of the second diode (D2) is provided with a first interface (IGBT).

3. The overcurrent protection circuit for a transistor as described in claim 1, characterized in that: The ninth resistor (R9) is a variable resistor.

4. The overcurrent protection circuit for a transistor as described in claim 1, characterized in that: The capacitor charging and discharging circuit includes a second optocoupler (U4). The first pin of the second optocoupler (U4) is electrically connected to one end of the thirteenth resistor (R13). The other end of the thirteenth resistor (R13) is electrically connected to one end of the eighteenth resistor (R18), one end of the twelfth resistor (R12), and the inverter peak current limiting circuit. The other end of the eighteenth resistor (R18) is electrically connected to the second pin of the second optocoupler (U4) and the seventh pin of the second comparator (U2B). The third pin of the second optocoupler (U4) is electrically connected to one end of the fifth capacitor (C5) and ground. The other end of the fifth capacitor (C5) is electrically connected to one end of the fourteenth resistor (R14), the fourth pin of the second optocoupler (U4), and the D flip-flop trigger. In the circuit, the other end of the fourteenth resistor (R14) is electrically connected to the D flip-flop trigger circuit. The fifth pin of the second comparator (U2B) is electrically connected to the other end of the twelfth resistor (R12) and one end of the twentieth resistor (R20). The other end of the twentieth resistor (R20) is grounded. The sixth pin of the second comparator (U2B) is electrically connected to one end of the seventeenth resistor (R17), one end of the nineteenth resistor (R19), and the positive terminal of the sixth capacitor (C6). The negative terminal of the sixth capacitor (C6) and the other end of the nineteenth resistor (R19) are grounded. The other end of the seventeenth resistor (R17) is electrically connected to the cathode of the fifth diode (D5). The anode of the fifth diode (D5) is electrically connected to the inverter peak current limiting circuit.

5. The overcurrent protection circuit for a transistor as described in claim 4, characterized in that: The fifth diode (D5) has a second interface (IBUS) at its anode.

6. The overcurrent protection circuit for a transistor as described in claim 4, characterized in that: The twentieth resistor (R20) is a variable resistor.

7. The overcurrent protection circuit for a transistor as described in claim 1, characterized in that: The D flip-flop trigger circuit includes a D flip-flop (U3). The first pin of the D flip-flop (U3) is electrically connected to the anode of the sixth diode (D6). The cathode of the sixth diode (D6) is electrically connected to the cathode of the fourth diode (D4), one end of the fifteenth resistor (R15), and the capacitor charging / discharging circuit. The third pin of the D flip-flop (U3) is electrically connected to one end of the eleventh resistor (R11) and the collector of the second transistor (V2). The base of the second transistor (V2) is electrically connected to the other end of the fifteenth resistor (R15). The emitter of the second transistor (V2) is electrically connected to the seventh pin, fifth pin, and fourth pin of the D flip-flop (U3), and the emitter of the first transistor (V1). The collector of the first transistor (V1) is electrically connected to the sixth pin of the D flip-flop (U3) and one end of the tenth resistor (R10). The base of the first transistor (V1) is electrically connected to one end of the sixteenth resistor (R16) and the other end of the fourth capacitor (C4). The other end of the sixteenth resistor (R16) is set as the reset pin (CPUFW). The fourteenth pin of the D flip-flop (U3), the other end of the eleventh resistor (R11), and the other end of the tenth resistor (R10) are all electrically connected to the other end of the first resistor (R1), the capacitor charging and discharging circuit, and the inverter peak current limiting circuit. The anode of the fourth diode (D4) is electrically connected to one end of the first resistor (R1).

8. The overcurrent protection circuit for a transistor as described in claim 7, characterized in that: The anode of the fourth diode (D4) is provided with the first interface (IGBT).

9. The overcurrent protection circuit for a transistor as described in claim 1, characterized in that: The device initialization protection circuit includes a third diode (D3). The anode of the third diode (D3) is electrically connected to one end of the first resistor (R1) and the inverter peak current limiting circuit. The cathode of the third diode (D3) is electrically connected to the anode of the first diode (D1), the positive terminal of the second capacitor (C2), and one end of the sixth resistor (R6). The cathode of the first diode (D1) is electrically connected to the other end of the first resistor (R1), the inverter peak current limiting circuit, and the inverter start-up capability limiting circuit. The negative terminal of the second capacitor (C2) and the other end of the sixth resistor (R6) are grounded.

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