Storage device, memory system, and operating method thereof

Abstract

A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to, during programming of a first physical page, disable a bit line bias function to free the bias latch to replace one of N page latches to perform program verification of a memory state, free one of the N page latches to cache program data for one of N logical pages of a second physical page, and store the program data for the one of the N logical pages of the second physical page in the freed page latch during programming of the first physical page.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese application No. 202210028189.X, filed on January 11, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to storage devices, memory systems, and methods of operating thereof. Background Technology

[0004] In non-volatile storage devices, written data is first quickly stored in a cache latch and then moved to a data latch. During a single programming operation of writing data to the physical memory cell array of the storage device, only one page of data can be transferred from the cache latch to the data latch. Thus, when more than one page of data is written to the physical memory cell array via programming, it is necessary to wait for the programming to complete and then move the page data from the cache latch to the data latch individually. Therefore, the process of writing data to the memory cell array is inefficient and cannot provide continuous programming. Summary of the Invention

[0005] In one aspect, a storage device includes a storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2^N bit of data. NOne of the following levels, where N is an integer greater than 1. The storage device further includes peripheral circuitry coupled to the memory cell array and configured to: sequentially and respectively perform first programming and second programming on the memory cell array in the first physical page and the second physical page in a cache-programmed manner; and during the first programming and the second programming, program at least a selected row of the memory cells based on N logical pages of the first physical page and the second physical page. The peripheral circuitry includes page buffers respectively coupled to bit lines. Each page buffer includes a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path. The main latch is configured to store first non-physical page information, the bias latch is configured to store second non-physical page information, and the (N-1) data latches and cache latches are configured to: during the programming of the N logical pages of the first physical page and the second physical page, act as N page latches to temporarily store programming data to be written into the N logical pages. The peripheral circuitry is further configured to: during the programming of the first physical page, disable the bit line bias function to release the bias latch in place of one of the N page latches to perform programming verification of the memory state; release one of the N page latches to cache the programming data of one logical page of the N logical pages of the second physical page; and during the programming of the first physical page, store the programming data of the one logical page of the N logical pages of the second physical page in the released page latch.

[0006] In some embodiments, the peripheral circuitry is further configured to: during the programming of the first physical page and the second physical page, employ an incremental step pulse programming (ISPP) programming method to program the first to the second physical pages. (N-M) The memory states are programmed, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

[0007] In some implementations, the peripheral circuitry is further configured to reduce the step increment of the programming voltage after the bit line bias function is disabled.

[0008] In some implementations, the second non-physical page information includes voltage bias information for the corresponding bit line.

[0009] In some embodiments, the peripheral circuit is further configured to: in 2 N The bitline bias function is disabled after the programming verification in the third-to-last memory state of the memory states.

[0010] In some implementations, the first non-physical page information includes verification information and programming information.

[0011] In some implementations, each storage cell is configured to correspond to 2 bits of data. 3 One of the three levels. The peripheral circuitry is also configured to program the selected row of the memory cell based on the three logical pages of the first physical page and the second physical page; and the two data latches and the cache latch are configured to act as three page latches during the programming process of the three logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the three logical pages.

[0012] In some implementations, each memory cell is configured to correspond to 2 bits of data. 4 One of the voltage levels. The peripheral circuitry is also configured to program a selected row of the memory cell based on the four logical pages of the first physical page and the second physical page; and the three data latches and the cache latch are configured to act as four page latches during the programming process of the four logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the four logical pages.

[0013] In some implementations, the bias latch is configured to store voltage bias information for the corresponding bit line.

[0014] In some embodiments, the storage device further includes a three-dimensional NAND flash memory device.

[0015] On the other hand, a method for programming a storage device is provided. The storage device includes a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2^N bit of data. NOne of the following levels, where N is an integer greater than 1. The peripheral circuitry includes multiple page buffers respectively coupled to bit lines. The method includes: storing N logical pages of a first physical page corresponding to the current first programming in the N page latches, wherein the N page latches include (N-1) data latches in the page buffers and cache latches coupled to the data path; storing first non-physical page information in a main latch in the page buffers; storing second non-physical page information in a bias latch in the page buffers; during programming of the first physical page, disabling bit line biasing to release the bias latch to replace one of the N page latches to perform programming verification of the memory state; releasing one of the N page latches to cache the programming data of one logical page of the N logical pages of the second physical page; and during programming of the first physical page, storing the programming data of the one logical page of the N logical pages of the second physical page in the released page latch.

[0016] In some embodiments, the method further includes: during the programming of the first physical page and the second physical page, using an incremental step pulse programming (ISPP) programming method to program the first to the second physical page. (N-M) Programming of memory states.

[0017] In some implementations, the programming voltage step increment is reduced after the bit line bias function is disabled.

[0018] In some implementations, the second non-physical page information includes voltage bias information for the corresponding bit line.

[0019] In some implementations, in 2 N The bitline bias function is disabled after the programming verification in the third-to-last memory state of the memory states.

[0020] In some implementations, the first non-physical page information includes verification information and programming information.

[0021] In some embodiments, the method further includes: programming a selected row of the storage unit based on three logical pages of the first physical page and the second physical page, wherein two data latches and the cache latch are configured to act as three page latches during the programming process of the three logical pages of the first physical page and the second physical page to temporarily store programming data to be written into the three logical pages.

[0022] In some embodiments, the method further includes: programming a selected row of the storage unit based on four logical pages of the first physical page and the second physical page, wherein three data latches and the cache latch are configured to act as four page latches during the programming process of the four logical pages of the first physical page and the second physical page to temporarily store programming data to be written into the four logical pages.

[0023] In another aspect, a storage system includes a storage device. The storage device includes a storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2^N bit of data. N One of the following levels, where N is an integer greater than 1. The storage system further includes peripheral circuitry coupled to the storage cell array and configured to: sequentially and respectively perform first programming and second programming on the storage cell array in the first physical page and the second physical page in a cache programming manner; and during the first programming and the second programming, program at least a selected row of the storage cells based on N logical pages of the first physical page and the second physical page. The peripheral circuitry includes page buffers coupled to bit lines, each page buffer including a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path. The main latch is configured to store first non-physical page information, the bias latch is configured to store second non-physical page information, and the (N-1) data latches and cache latches are configured to: during the programming of the N logical pages of the first physical page and the second physical page, act as N page latches to temporarily store programming data to be written into the N logical pages. The peripheral circuitry is further configured to: during programming of the first physical page, disable bit-line biasing to release the bias latch in place of one of the N page latches to perform programming verification of the memory state; release one of the N page latches to cache programming data for one logical page of the N logical pages of the second physical page; and during programming of the first physical page, store the programming data of the one logical page of the N logical pages of the second physical page in the released page latch. The storage system also includes a storage controller coupled to the storage device and configured to control the operation of the storage device.

[0024] In some embodiments, the peripheral circuitry is further configured to: during the programming of the first physical page and the second physical page, employ an incremental step pulse programming (ISPP) programming method to program the first to the second physical pages. (N-M)Programming of memory states. Attached Figure Description

[0025] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate some aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0026] Figure 1 This is a schematic diagram illustrating the writing of data into a non-volatile storage device according to some embodiments of the present disclosure;

[0027] Figure 2 This is a block diagram of a system having a non-volatile storage device according to some embodiments of the present disclosure;

[0028] Figure 3A This is a schematic diagram of a memory card according to some embodiments of the present disclosure;

[0029] Figure 3B This is a schematic diagram of a solid-state drive (SSD) according to some embodiments of the present disclosure;

[0030] Figure 4 This is a block diagram of a non-volatile memory device including a memory cell array and peripheral circuitry, according to some embodiments of the present disclosure;

[0031] Figure 5 This is a block diagram of a page buffer in programming operations according to some embodiments of this disclosure;

[0032] Figure 6 It is a state encoding table in which user data is not encoded and converted in the page latch according to some embodiments of this disclosure;

[0033] Figure 7 It is an encoding state table that encodes and converts programming data of temporarily stored logical pages according to some embodiments of this disclosure.

[0034] Figure 8 This is an encoding state table according to some embodiments of this disclosure, when the LV3 programming verification is passed and the function of the master latch DS changes;

[0035] Figure 9 It is an encoding status table after LV5 programming verification has been passed, according to some embodiments of this disclosure;

[0036] Figure 10 It is an encoding status table after LV6 programming verification has been passed, according to some embodiments of this disclosure;

[0037] Figure 11This is a schematic flowchart of a programming method for a non-volatile storage device according to some embodiments of the present disclosure;

[0038] Figure 12 It is an encoding state table that encodes and converts programming data of temporarily stored logical pages according to some embodiments of this disclosure.

[0039] Figure 13 It is an encoding status table after LV4 programming verification has been passed, according to some embodiments of this disclosure;

[0040] Figure 14 This is an encoding status table according to some embodiments of this disclosure, when the LV5 programming verification is passed and the function of the master latch DS changes;

[0041] Figure 15 It is an encoding status table after LV6 programming verification has been passed, according to some embodiments of this disclosure;

[0042] Figure 16 It is an encoding state table that encodes and converts programming data of temporarily stored logical pages according to some embodiments of this disclosure.

[0043] Figure 17 This is an encoding status table according to some embodiments of this disclosure, when the LV7 programming verification is successful and the function of the master latch DS changes;

[0044] Figure 18 It is an encoding status table after LV11 programming verification has been passed, according to some embodiments of this disclosure;

[0045] Figure 19 This is an encoding state table according to some embodiments of this disclosure, when the LV13 programming verification is passed and the function of the master latch DS changes;

[0046] Figure 20 It is an encoding status table after LV14 programming verification has been passed, according to some embodiments of this disclosure;

[0047] Figure 21 It is an encoding state table that encodes and converts programming data of temporarily stored logical pages according to some embodiments of this disclosure.

[0048] Figure 22 It is an encoding status table after LV8 programming verification has been passed, according to some embodiments of this disclosure;

[0049] Figure 23 It is an encoding status table after LV12 programming verification has been passed, according to some embodiments of this disclosure;

[0050] Figure 24 This is an encoding state table according to some embodiments of this disclosure, when the LV13 programming verification is passed and the function of the master latch DS changes;

[0051] Figure 25 It is an encoding status table after LV14 programming verification has been passed, according to some embodiments of this disclosure;

[0052] Figure 26 This is the encoding status table when LV5 programming verification is passed and bitline offset function is disabled;

[0053] Figure 27 It is an encoding status table after LV6 programming verification has been passed, according to some embodiments of this disclosure;

[0054] Figure 28 This is a schematic flowchart of a programming method for a non-volatile storage device according to some embodiments of the present disclosure;

[0055] Figure 29 This is an encoding state table according to some embodiments of this disclosure, when LV13 programming verification is passed and bit line offset function is disabled; and

[0056] Figure 30 It is an encoding status table after LV14 programming verification has been passed, according to some embodiments of this disclosure;

[0057] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0058] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "one," or "this" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0059] In non-volatile storage devices, written data is first quickly stored in a cache latch and then moved to a data latch. A schematic diagram of data writing in a non-volatile storage device is shown below. Figure 1As shown, the period during which programming data for one logical page (page 3) of the second physical page is moved to the data latch is hidden during the first programming process. That is, during the first programming process of writing data to the physical array of flash memory, only the programming data for one of the three logical pages of the second physical page can be moved from the cache latch to the data latch. Thus, when the number of physical pages programmed into the physical array is greater than one physical page, it is necessary to wait for the programming to finish before the programming data for the other two logical pages in the second physical page are moved from the cache latch to the data latch separately. This makes writing data to the memory cell array inefficient and the programming discontinuous. The solution provided in this disclosure allows the programming data for various logical pages required for the second programming to be temporarily stored in the page latch during the first programming period, and therefore eliminates or reduces the waiting time at the start of the second programming, thereby improving the continuity between programming processes.

[0060] Figure 2 A block diagram of an exemplary system 200 having a non-volatile storage device according to some embodiments of the present disclosure is shown. System 200 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 2 As shown, system 200 may include host 208 and memory system 202 having one or more non-volatile memory devices 204 and controller 206. The non-volatile memory device 204 includes a memory cell array and a multi-page buffer. Host 208 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 208 may be configured to send data to or receive data from non-volatile memory device 204.

[0061] The non-volatile storage device 204 can be any non-volatile storage device disclosed herein. According to some embodiments, a controller 206 is coupled to the non-volatile storage device 204 and the host 208 and is configured to control the non-volatile storage device. The controller 206 can manage data stored in the non-volatile storage device and communicate with the host 208. In some embodiments, the controller 206 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or for use in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0062] In some embodiments, controller 206 is designed to operate in a high duty cycle environment within an SSD or embedded multimedia card (eMMC) for data storage and enterprise storage in mobile devices such as smartphones, tablets, and laptops. Controller 206 can be configured to control the operation of non-volatile storage device 204, such as read, erase, and program operations. Controller 206 can also be configured to manage various functions regarding data stored or to be stored in non-volatile storage device 204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 206 is also configured to process error correction codes (ECC) for data read from or written to non-volatile storage device 204. Controller 206 can also perform any other suitable functions, such as formatting non-volatile storage device 204. For example, controller 206 can communicate with external devices (e.g., host 208) according to specific communication protocols. For example, controller 206 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc. Controller 206 can specifically be composed of the following: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic unit, discrete hardware circuitry, or a combination thereof, as well as other suitable hardware, firmware, and / or software.

[0063] The controller 206 and one or more non-volatile storage devices 204 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 202 can be implemented and packaged into different types of electronic terminal products. Figure 3AIn one example shown, controller 206 and non-volatile storage device 204 can be integrated into memory card 302. Memory card 302 may include PC cards (PCMCIA), CF cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 302 may also include a connection between memory card 302 and a host computer (e.g., Figure 2 The host 208 in the memory card connector 304 is coupled to it. In such a way... Figure 3B In another example shown, controller 206 and multiple non-volatile storage devices 204 can be integrated into SSD 306. SSD 306 may also include interfaces for connecting SSD 306 to a host computer (e.g., Figure 2 The SSD connector 308 is coupled to the host 208 in the memory card 302. In some embodiments, the storage capacity and / or operating speed of the SSD 306 is greater than that of the memory card 302.

[0064] Figure 4 A block diagram of a non-volatile memory device (e.g., non-volatile memory device 204) including a memory cell array 401 and peripheral circuitry 400 according to some embodiments of the present disclosure is shown. The peripheral circuitry 400 includes a page buffer / amplifier sensor 404, a column decoder / bit line (BL) driver 406, a row decoder / word line (WL) driver 408, a voltage generator 410, control logic 412, a register 414, an interface 416, and a data bus 418. It should be understood that in some examples, according to some embodiments of the present disclosure, additional peripheral circuitry (not shown) may also be included.

[0065] Page buffer / sensor amplifier 404 can be configured to read data from memory cell array 401 and program (write) data to memory cell array 401 according to control signals from control logic 412. In one example, page buffer / sensor amplifier 404 can store programming data (write data, also referred to herein as a "data page") in a logical page of a physical page to be programmed into memory cell array 401. As described in detail below and consistent with the scope of this disclosure, in programming operations, page buffer / sensor amplifier 404 may include multiple page buffers, each coupled to a bit line. Each page buffer includes N-1 data latches and cache latches coupled to the data path for temporarily storing N-bit data segments received from data bus 418 and for caching the N-bit data segments via the corresponding bit line to the corresponding selected memory device via cache programming.

[0066] The column decoder / bit line (BL) driver 406 can be configured to be controlled by control logic 412 to select one or more NAND memory strings by applying bit line voltages generated from voltage generator 410. The row decoder / word line (WL) driver 408 can also be configured to drive word lines using word line voltages generated from voltage generator 410. Voltage generator 410 can be configured to be controlled by control logic 412 and generate word line voltages (e.g., read voltage, programming voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 401.

[0067] See Figure 4 The peripheral circuitry 400 is configured to perform a first programming process and a second programming process on the memory cell array 401 sequentially through the first physical page and the second physical page, respectively, using a cache programming method. During the first / second programming process, the selected rows of memory cells are programmed based on the N logical pages of the first / second physical page. In some embodiments, user data is transmitted to the page buffer / sensor amplifier 404 via the data bus 418. The page buffer / sensor amplifier 404 is configured to convert the user data into programming data based on preset rules for programming into each logical page of the selected row of the memory cell. During the ongoing first programming operation, the programming data in the N logical pages of the first physical page can be temporarily stored in the page buffer / sensor amplifier 404.

[0068] Figure 5 A detailed block diagram of a page buffer / sensor amplifier 404 during programming operations according to some embodiments of the present disclosure is shown. In some embodiments, the page buffer / sensor amplifier 404 includes a plurality of page buffer circuits 502. Each page buffer circuit 502 is coupled to a corresponding bit line in the bit line BL. In other words, each page buffer circuit 502 can be coupled to a corresponding column of memory cells (e.g., a string of memory cells) via the corresponding bit line BL and is configured to temporarily store data of the selected memory cell during programming operations. Programming data in N logical pages of the first physical page / second physical page of the row of memory cells will be programmed. In some embodiments, the page buffer circuit 502 is also configured to: support data from the data bus 418 (… Figure 4 The received user data (as shown in the diagram) is preprocessed and converted into selected programming data for N logical pages of the first physical page / second physical page in the storage cell row.

[0069] like Figure 5As shown, each page buffer circuit 502 may include (N-1) data latches (D1 to Dn-1) 508 and a cache latch (DC) 506 coupled to the data path. The (N-1) data latches 508 and the cache latch 506 serve as an N-page latch to temporarily store programming data to be written to the N logical pages during a programming process of the first physical page / second physical page.

[0070] Each page buffer circuit 502 may also include multiple storage units for storing non-physical page information. Non-physical page information refers to information in a physical page other than the programming data of a logical page, and it differs from, for example, the programming data of an N logical page. Non-physical page information can be used during the programming process to assist in implementing the data programming process of physical pages; it is generally not temporarily stored in the data latch. For example... Figure 5 As shown, in some embodiments, page buffer circuit 502 includes a main latch (DS) 512 configured to store verification information and programming information, and a bias latch (DL) 510 configured to store bias voltage information corresponding to bit lines BL. Each page buffer circuit 502 may also include a bias circuit 504. The bias circuit 504 is coupled to each bit line BL and configured to apply bit line voltages to selected rows of memory cells coupled to each bit line BL during programming operations.

[0071] In some embodiments of this disclosure, the non-volatile storage device includes: a storage cell array having storage cells arranged in rows and columns. Each storage cell is configured to correspond to 2 N bits of data (e.g., 3 bits of data). N One of the voltage levels; and the peripheral circuitry is coupled to the memory cell array and configured to: perform a first programming process and a second programming process on the memory cell arrays on the first physical page and the second physical page respectively in a cache programming manner, and during the first programming process / second programming process, program the row of the selected memory cell based on the three logical pages of the first physical page / second physical page, wherein the three logical pages are the next page (LP), the middle page (MP), and the previous page (UP).

[0072] The peripheral circuitry includes multiple page buffers, each coupled to a bit line. Each page buffer includes a main latch DS, two data latches D1 and D2, and a cache latch DC coupled to the data path. The main latch DS is configured to store first non-physical page information; the two data latches D1 and D2 and the cache latch DC are used as three page latches to temporarily store programming data to be written to the three logical pages during the programming process of the first physical page / second physical page.

[0073] The peripheral circuitry is also configured to: during the programming of the first physical page, when the first to the second... (N-M) When the programming operation for the first memory state is completed, the programming operation will affect the corresponding second memory state. (N-M) The programming verification operation is performed on the memory state. And in the 2nd... (N-M) If the programming verification of each memory state passes, a non-target verification is performed on the main latch, thereby ensuring that the first to second memory states stored in the main latch are valid. (N-M) The identifier corresponding to the memory state is the 2nd (N-M) +1 to 2 N Each memory state corresponds to a different identifier, and at least one of the N page latches is released to cache the programming data of at least one logical page among the N logical pages of the second physical page. Furthermore, during the programming of the first physical page, the programming data of one logical page among the N logical pages of the second physical page is stored in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2) (e.g., for TLC, N=3, M=1). In some embodiments, the non-volatile memory device includes a three-dimensional NAND flash memory device.

[0074] In some embodiments of this application, the peripheral circuitry is further configured to: use the Incremental Step Pulse Programming (ISPP) programming method to program the first to second physical pages when programming the first physical page / second physical page. (N-M) Each memory state is programmed. In some implementations, for example, for TLC, N=3, M=1, the peripheral circuitry is also configured to: during programming of the first physical page / second physical page, use the Incremental Step Pulse Programming (ISPP) programming method to program the first to second physical pages. 2 Each memory state is used to perform programming operations.

[0075] In some implementations, each memory cell has eight memory states (levels) and can therefore be set to 2 corresponding to three bits of data. 3 One of the voltage levels. Each memory state can correspond to one of the threshold voltage (Vth) ranges for the memory cell. On the other hand, each memory state can correspond to one of the two voltage levels in the selected row of the memory cell to be stored. 3 One of the three bits of data.

[0076] In some implementations, see Figure 6 , Figure 6 This is a state encoding table for temporarily storing user data in a page latch, according to some embodiments of this application. An example of binary encoding for a one-to-one mapping between eight memory states (LV0 to LV7) and eight segments is shown.

[0077] Each segment of the three-bit data can be composed of three-bit binary codes, and these three-bit binary codes are derived from three logical pages, namely the low page LP, the middle page MP, and the high page UP.

[0078] As can be seen, the three page latches store the programming data of the low, middle and high logical pages in sequence. Page latch D1 stores the low page LP, page latch D2 stores the middle page MP, and page latch DC stores the high page UP.

[0079] In some implementations, memory state LV1 may correspond to a segment with code 011. In some implementations, memory state LV7 may correspond to another segment with code 101. Figure 7 This is an encoding state table, according to some embodiments of this disclosure, showing the encoding and conversion of programming data for logical pages stored in page latches according to preset rules. After encoding and conversion, such as... Figure 7 As shown, LV1 is encoded from 011 to 001, where code 011 represents LP / MP / UP in sequence. The encoding order of other memory states is also LP / MP / UP. LV2 is encoded from 001 to 101, LV3 is encoded from 000 to 011, LV4 is encoded from 010 to 000, LV5 is encoded from 110 to 010, LV6 is encoded from 100 to 100, and LV7 is encoded from 101 to 110.

[0080] In some implementations, the peripheral circuitry is also configured to: [address 2] N The second of the memory states N-1 Before performing programming verification on a memory state, the programming data corresponding to one of the N logical pages of the first physical page is stored in at least one of the N page latches.

[0081] And in relation to 2 N The second of the memory states N-1 After the memory state is verified by programming, the programming data of one logical page out of the N logical pages of the second physical page is stored in at least one of the N page latches.

[0082] In some implementations, before performing programming verification on the fourth memory state LV3 of the eight memory states, DC may store programming data for one of the three logical pages of the first physical page (current UP). D1 may store programming data for the corresponding logical page of the first physical page (current LP). D2 may store programming data for the corresponding logical page of the first physical page (current MP). After performing programming verification on the fourth memory state LV3 of the eight memory states, programming data for one of the three logical pages of the second physical page is stored in three page latches. See reference... Figure 8 For more details, please visit [website / platform name].

[0083] In some implementations, the peripheral circuitry is also configured to: [address 2] N The second of the memory states N-1 After the programming verification of each memory state is performed, a non-target verification is performed on the main latch. That is, the first to second states stored in the main latch DS are... (N-1) The identifier corresponding to each memory state is different from that of the 2nd. (N-1) +1 to 2 N An identifier corresponding to each memory state. In some implementations, reference is made to... Figure 8 After the programming verification of the fourth memory state out of the eight memory states is completed (i.e., the fourth memory state LV3 has been verified), the main latch DS stores the identifiers corresponding to the first through fourth memory states. These identifiers are different from the identifiers corresponding to the fifth through eighth memory states. That is, the identifiers of memory states that have been programmed and verified in the main latch are different from the identifiers of memory states that have not been programmed and verified. When DS is 1, it indicates that the memory state has passed programming verification; when DS is 0, it indicates that the memory state has failed programming verification. LV3 programming verification passed (LV3 passed) means that the segment corresponding to memory states LV0~LV3 has been written into the three page latches. All binary codes in LV0~LV3 can be updated to 1. The encoded state table is as follows: Figure 8 As shown. At this point, four memory states, LV4, LV5, LV6, and LV7, have not yet been programmed and verified. Since each bit of each logical page has two possible states, 0 and 1, the physical unit consisting of two page latches has four possible states (2...). 2=4). Since the identifier for memory states that failed programming verification in the main latch DS used for non-target verification is 0, the combination of two page latches and the main latch DS used for non-target verification can have codes 000, 001, 010, and 011, representing LV4, LV5, LV6, and LV7 respectively. In other words, after LV3 programming verification passes, only two page latches and the main latch DS used for non-target verification are needed to distinguish between the four memory states of LV4, LV5, LV6, and LV7. Therefore, after LV3 programming verification passes, the page latch DC can be released, allowing the released page latch to cache the programming data of the lower page LP of the second physical page. The encoded state table is as follows: Figure 8 As shown.

[0084] In some implementations, each page buffer also includes a bias latch configured to store voltage bias information for the corresponding bit line.

[0085] In some embodiments, the peripheral circuitry is further configured to: cause the first to second latches stored in the main latch to... (N-M) The identifier corresponding to the memory state is the 2nd (N-M) +1 to 2 N After the identifiers corresponding to the memory states become distinct, the bit lines are floated during programming to dump the first non-physical page information in the main latch. In some implementations, the first non-physical page information includes verification information and programming information. After successful LV3 programming verification, the main latch DS is used to identify memory states that have passed programming verification and those that have not. Therefore, the first non-physical page information in the original main latch DS can no longer be stored. Floating the bit lines during programming releases the bias latch to dump the first non-physical page information in the main latch.

[0086] In some implementations, after LV5 programming verification passes, it means that the segments corresponding to memory states LV0~LV5 in the three page latches have been written, and two memory states, LV6 and LV7, have not yet passed verification. Since each logical page's bit has two possible states, 0 and 1, the main latch DS and page latch D2 can form codes 00 and 01, respectively, representing the memory states LV6 and LV7 that failed programming verification. Therefore, after LV5 programming verification passes, page latch D1 can be released, allowing the released page latch to buffer the middle page MP of the next physical page. The encoded state table is as follows. Figure 9 As shown.

[0087] In some implementations, the peripheral circuitry is further configured to: [address 2] NAfter programming verification is performed on the second-to-last (second from the back) memory state in a set of memory states, N page latches are released, allowing the N page latches to cache the programming data for each of the N logical pages of the second physical page. In some implementations, after programming verification of the second-to-last memory state of the 8th memory state (i.e., the 7th memory state (LV6) has been verified), three page latches are released, allowing the three page latches to cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 10 As shown, when the LV6 programming verification passes, i.e., DS is 1, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the upper page UP of the second physical page. At this point, all three page latches are released to store all programming data of each page in the three logical pages of the second physical page. At this time, page latch D1 caches the programming data of the lower page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, and page latch DC caches the programming data of the upper page MP of the second physical page. Then, whether DS is 1 can be used to determine whether LV7 programming verification has passed. If DS is 1, it indicates that LV7 programming verification has passed, and the data from LV0 to LV7 has been written to the selected memory cell, and the first programming is complete. At this point, the programming data of the three logical pages to be written in the second programming has been cached in the three page latches. This allows direct entry into the second programming process. If DS is 0, the programming verification fails. Because the three page latches cache the programming data for each of the three logical pages (next LP, next MP, and next UP) of the second physical page after LV6 programming verification, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0088] Based on the non-volatile storage device provided in the above embodiments of this application, a programming method for the non-volatile storage device is also provided in the embodiments of this application. The non-volatile storage device includes a storage cell array and peripheral circuitry; the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2-bit N-bit data segment. NOne of the following levels, where N is an integer greater than 1. The peripheral circuitry includes multiple page buffers respectively coupled to the bit lines. The method includes: storing N logical pages of the first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffers and a cache latch coupled to the data path. During the first programming of the first physical page, when the 1st to 2nd... (N-M) When the programming operation for the first memory state is completed, for the second... (N-M) The programming operation corresponding to each memory state is used to perform a programming verification operation. When the second memory state is used... (N-M) The programming verification of the memory states passed, enabling the main latch to store the first to second states. (N-M) The identifier corresponding to each memory state is different from that of the second one. (N-M) +1 to 2 N The system identifies the memory state and releases at least one of the N page latches to cache the programming data of at least one logical page among the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2). Furthermore, before performing a second programming of the second physical page in cached programming mode after the first programming, during the first programming of the first physical page, the programming data of one logical page among the N logical pages of the second physical page is stored in the released page latch.

[0089] Figure 11 This is a schematic flowchart illustrating an embodiment of a programming method for a non-volatile memory device provided in some embodiments of this application. For example... Figure 11 As shown, the programming method includes the following steps:

[0090] Step S101: Store the N logical pages of the first physical page corresponding to the current first programming in N page latches, wherein the N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path.

[0091] After storing the programming data of the three logical pages LP, MP, and UP in the page latches, the programming data stored in the page latches is encoded according to preset rules to obtain the binary codes corresponding to different memory states. This can be found in [reference needed]. Figure 7 .

[0092] Step S102: Store the first non-physical page information in the main latch in the page buffer. Here, the first non-physical page information includes verification information and programming information.

[0093] In step S101, each memory cell is configured to correspond to a 2-bit data segment in one of the eight memory states.3 One of the three levels. After performing programming verification on the fourth memory state out of eight memory states, the programming data corresponding to one of the three logical pages of the first physical page is stored in at least one of the three page latches. In some embodiments, before performing programming verification on the fourth memory state LV3 out of eight memory states, DC may store the programming data of one of the three logical pages of the first physical page (current UP) corresponding to the current first programming. D1 may store the programming data of the corresponding logical page of the first physical page (current LP). D2 may store the programming data of the corresponding logical page of the first physical page (current MP). And after programming verification on the fourth memory state out of eight memory states, the programming data of one of the three logical pages of the second physical page is stored in at least one of the three page latches. In some embodiments, refer to Figure 8 After verifying the programming of the fourth memory state LV3 out of the eight memory states, the programming data of one of the three logical pages of the second physical page is stored in at least one of the three page latches.

[0094] Step S103: During the first programming of the first physical page, when the 1st to the 2nd (N-M) When the programming operation for the memory state is completed, execute the operation with the second memory state. (N-M) The programming verification operation corresponds to each memory state.

[0095] In the second (N-M) If the programming verification of each memory state passes, then the first to second states stored in the main latch are enabled. (N-M) The identifier corresponding to each memory state is different from that of the 2nd. (N-M) +1 to 2 N The identifier corresponding to each memory state is used to cache the programming data of at least one logical page among the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

[0096] Furthermore, before and during the first programming of the first physical page, before the second programming of the second physical page, and after the first programming of the second physical page in the cache programming mode, the programming data of one of the N logical pages of the second physical page is stored in a released page latch.

[0097] In step S103 above, taking TLC as an example, N=3, M=1, the first programming / second programming is performed on the first physical page / second physical page, including using the Incremental Step Pulse Programming (ISPP) method to perform programming operations on the first to fourth memory states.

[0098] In some embodiments of this application, in relation to 2 N The second of the memory states N-1 Before performing programming verification on each memory state, the programming data of the corresponding logical page among the N logical pages of the first physical page is stored in at least one of the N page latches. And for 2... N The second of the memory states N-1 After programming verification is performed on each memory state, the programming data of one logical page from the N logical pages of the second physical page is stored in at least one of the N page latches. In some embodiments, before performing programming verification on the fourth memory state LV3 of the eight memory states, DC may store the programming data of one logical page (current UP) from the three logical pages of the first physical page. D1 may store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 may store the programming data of the corresponding logical page (current MP) of the first physical page. After programming verification on the fourth memory state LV3 of the eight memory states, the programming data of one logical page from the three logical pages of the second physical page is stored in three page latches. See also... Figure 8 To obtain details.

[0099] In some embodiments of this application, in relation to 2 N The second of the memory states N-1 After the programming verification of each memory state is performed, the main latch DS performs a non-target verification. That is, the first to second memory states stored in the main latch DS are compared with the target states. (N -1) The identifier corresponding to each memory state is different from that of the 2nd. (N-1) +1 to 2 N An identifier corresponding to each memory state. Specifically, such as... Figure 8As shown, after the programming verification of the fourth memory state out of eight memory states (i.e., the fourth memory state LV3 has been verified), the identifiers corresponding to the first to fourth memory states stored in the main latch DS are different from the identifiers corresponding to the fifth to eighth memory states. That is, the identifiers of memory states that have been programmed and verified in the main latch are different from the identifiers of memory states that have not passed programming verification. When DS is 1, it indicates that the programming verification of the memory state has passed, and when DS is 0, it indicates that the programming verification of the memory state has failed. Passing LV3 programming verification (LV3 passed) means that the segments corresponding to memory states LV0~LV3 have been written into the three page latches. That is, all binary codes in LV0~LV3 can be updated to 1. The encoding state table is as follows: Figure 8 As shown. At this point, four memory states, LV4, LV5, LV6, and LV7, have not yet been programmed and verified. Since each bit of each logical page has two possible states, 0 and 1, the physical unit consisting of two page latches has four possible states (2...). 2 =4). Since the identifier for memory states that failed programming verification in the main latch DS used for non-target verification is 0, the combination of two page latches and the main latch DS used for non-target verification can have codes 000, 001, 010, and 011, representing LV4, LV5, LV6, and LV7, respectively. In other words, after LV3 programming verification passes, only two page latches and the main latch DS used for non-target verification are needed to distinguish between the four memory states of LV4, LV5, LV6, and LV7. Therefore, after LV3 programming verification passes, the page latch DC can be released, allowing the released page latch to cache the programming data of the lower page LP of the second physical page. The encoded state table is as follows: Figure 8 As shown.

[0100] In some embodiments of this application, in the second (N-M) If the programming verification of each memory state passes, then the first to second states stored in the main latch are enabled. (N-M) The identifier corresponding to the memory state is the 2nd (N-M) +1 to 2 N The identifiers corresponding to each memory state are different, including: in the case of 2 N The second of the memory states N-1 After the programming verification of each memory state is performed, the main latch performs a non-target verification. The non-target verification causes the first to second memory states stored in the main latch to be affected. N-1 The identifier corresponding to each memory state is different from that of the 2nd. (N-1) +1 to 2 N The identifier corresponding to each memory state. See [link to documentation] for details. Figure 8After the programming verification of the fourth memory state out of eight memory states (i.e., memory state LV3 has been verified), the main latch DS performs a non-target verification. Non-target verification causes the identifiers corresponding to memory states 1 through 4 stored in the main latch to be different from the identifiers corresponding to memory states 5 through 8. When DS is 1, it indicates that the memory state has passed programming verification, and when DS is 0, it indicates that the memory state has failed programming verification.

[0101] In some embodiments of this application, after the main latch performs non-target verification, the bit lines are floated during programming to dump the first non-physical page information in the main latch. Since the non-target verification after LV3 programming verification is successful, the main latch is used to identify the memory states that have been programmed and verified as well as the memory states that have not yet been programmed and verified. Therefore, it cannot continue to store the first non-physical page information in the original main latch DS. Floating the bit lines during programming after the non-target verification of the main latch can release the bias latch to dump the first non-physical page information in the main latch.

[0102] In some embodiments of this application, in relation to 2 N After programming verification of the penultimate memory state out of the eight memory states, N page latches are released, allowing these N page latches to cache the programming data for each of the N logical pages of the second physical page. In some implementations, after programming verification of the penultimate memory state out of the eight memory states (i.e., the seventh memory state (LV6) has been verified), three of these page latches are released, allowing these three page latches to cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 10As shown, when the programming verification for LV6 passes (i.e., DS is 1), page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, thereby further releasing page latch DC to cache the programming data of the upper page UP of the second physical page. At this point, all three page latches are released so that all programming data of each page can be stored in the three logical pages of the second physical page. At this time, page latch D1 caches the programming data of the lower page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, and page latch DC caches the programming data of the upper page MP of the second physical page. After this, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it indicates that the LV7 programming verification has passed, and the data from LV0 to LV7 has been written to the selected memory cell. Programming ends. At this point, the programming data of the three logical pages to be written in the second programming is already in the page latches, so the second programming process can be directly entered. If DS is 0, the programming verification cannot continue.

[0103] In some embodiments of this application, after the peripheral circuitry included in the non-volatile memory device stores the programming data of three logical pages in three page latches, it performs encoding conversion on the programming data of the logical pages stored in the page latches according to preset rules. For example... Figure 12 As shown, the obtained Figure 6 The encoding is converted into an encoding state table, and each memory state before encoding conversion includes a three-bit binary code, respectively from LP / MP / UP. After encoding conversion, LV1 is encoded from 011 to 001, where 011 comes from LP / MP / UP in sequence. Similarly, the encoding order of other memory states is LP / MP / UP, LV2 is encoded from 001 to 101, LV3 is encoded from 000 to 011, LV4 is encoded from 010 to 000, LV5 is encoded from 110 to 010, LV6 is encoded from 100 to 100, and LV7 is encoded from 101 to 110. In some implementations, DC can store the programming data of one of the three logical pages of the first physical page (current UP), D1 can store the programming data of the corresponding logical page of the first physical page (current LP), and D2 can store the programming data of the corresponding logical page of the first physical page (current MP). LV4 programming verification passed (LV4 passed) means that the segments corresponding to the memory states LV0 to LV4 in the three page latches have all been written. That is, all binary codes from LV0 to LV4 can be updated to 1 because they are no longer needed in the first programming operation. The encoding state table is as follows: Figure 13As shown. At this point, three memory states, LV5, LV6, and LV7, remain unprogrammed but verified. Since each bit of each logical page has two possible states, 0 and 1, the physical unit includes two page latches and has four possible states (2... 2 =4). Excluding code 11, which is the same as the programmed and verified memory state, the remaining codes 00, 10, and 01 can represent LV5, LV6, and LV7, respectively.

[0104] In other words, after successful LV4 programming verification, only two page latches are needed to distinguish between LV5, LV6, and LV7 memory states. Therefore, after successful LV4 programming verification, page latch DC can be released. The programming data of the current previous page (UP) is replaced by the programming data of the next page (LP) of the second physical page.

[0105] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N After performing programming verification on the third-to-last memory state in a memory state, a non-target verification is performed on the main latch. This non-target verification causes the first to second memory states stored in the main latch to be related to the programmable state. N The identifiers corresponding to the -2 memory states are different from the 2nd one. N -1 to 2 N Each memory state corresponds to an identifier. In some implementations, after the programming verification of the third-to-last (third from the back) memory state out of eight memory states (i.e., the sixth memory state (LV5) has been verified), the master latch DS performs the following non-target verification: the identifiers corresponding to the first through sixth memory states stored in the master latch are different from the identifiers corresponding to the seventh and eighth memory states. When DS is 1, it indicates that the programming verification of that memory state has passed; when DS is 0, it indicates that the programming verification of that memory state has failed. Figure 14 As shown, it can be updated Figure 13 The binary encoding. That is, all data bits in LV5 can be updated to 1 because they are no longer needed in the current first programming operation. For example... Figure 14As shown, DS is 1 at this point, indicating that LV5 programming verification has passed. At this time, the main latch DS and page latch D2 can form codes 00 and 01, representing LV6 and LV7 respectively. In other words, after LV5 programming verification passes, only one page latch and the main latch DS for non-target verification are needed to distinguish between the LV6 and LV7 memory states. Therefore, after LV5 programming verification passes, page latch D1 can be released to cache the programming data of the next page LP of the second physical page, thereby further releasing page latch DC to cache the programming data of the middle page MP of the second physical page. That is, the next LP can be passed from DC to D1, and the programming data of the next MP can be cached in DC. It should be noted that when the main latch DS is performing target verification, the status bit of the programming verification being performed is 1, and the other status bits are 0.

[0106] Because the non-target verification performed after LV5 verification passed, the identifiers corresponding to the 1st to 6th memory states stored in the main latch are different from those corresponding to the 7th and 8th memory states. Therefore, the first non-physical page information in the original main latch DS can no longer be stored. After the non-target verification of the main latch DS, the bit lines are floated during programming to release the bias latch DL and dump the first non-physical page information in the main latch DS.

[0107] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N After programming verification is performed in the penultimate memory state of the first memory state, N page latches are released, allowing the N page latches to cache the programming data for each of the N logical pages of the second physical page. In some implementations, after programming verification in the penultimate memory state of the eighth memory state (i.e., the seventh memory state (LV6) has been verified), three of these page latches are released, allowing the three page latches to cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 15As shown, when the LV6 programming verification passes and DS is 1, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the upper page UP of the second physical page. At this point, all three page latches are released to store all programming data of each page in the three logical pages of the second physical page. At this time, page latch D1 caches the programming data of the lower page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, and page latch DC caches the programming data of the upper page MP of the second physical page. After this, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it indicates that the LV7 programming verification has passed, and the data from LV0 to LV7 has been written to the selected memory cell, and the first programming ends. At this point, the programming data of the three logical pages to be written in the second programming has been cached in the three page latches, thus allowing direct entry into the second programming process. If DS is 0, programming verification cannot proceed. Because the three page latches after LV6 programming verification can cache the programming data for each of the three logical pages (next LP, next MP, and next UP) of the second physical page, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, a second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0108] Based on a non-volatile storage device according to some embodiments of this application, a programming method for a non-volatile storage device is provided. The programming method includes the following steps.

[0109] Step S201: Store the N logical pages of the first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path.

[0110] After the programming data of the three logical pages LP, MP, and UP are stored in the page latches, the programming data stored in the page latches is encoded and converted according to preset rules to obtain binary data corresponding to different memory states. More details are as follows... Figure 12 As shown.

[0111] Step S202: Store the first non-physical page information in the bias latch in the page buffer. Here, the first non-physical page information includes verification information and programming information.

[0112] Step S203: During the first programming of the first physical page, when the 1st to the 2nd (N-M)When the programming operation for the memory state is completed, execute the operation with the second memory state. (N-M) Programming verification corresponding to each memory state. If for the second... (N-M) If the programming verification of each memory state passes, then the first to second states stored in the main latch will be enabled. (N-M) The identifier corresponding to each memory state is different from that of the second one. (N-M) +1 to 2 N The identifier corresponding to each memory state is used to release at least one of the N page latches to cache the programming data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2); and before and during the first programming of the first physical page in the cache programming of the second physical page after the second programming of the first programming, the programming data of one logical page of the N logical pages of the second physical page is stored in a released page latch.

[0113] In step S203 above, taking TLC as an example, N=3, M=1, the first programming / second programming is performed on the first physical page / second physical page, including using the Incremental Step Pulse Programming (ISPP) programming method to program the first to second physical pages. 2 Programming of memory states.

[0114] In some implementations, in the second (N-M) If the programming verification of each memory state passes, then the first to second states stored in the main latch are synchronized. (N-M) The identifier corresponding to the memory state is the 2nd (N-M) +1 to 2 N Each memory state has a different identifier, including:

[0115] In the case of 2 N After the programming verification of the third-to-last memory state in the memory state sequence, the main latch performs a non-target verification. The non-target verification causes the first to second memory states stored in the main latch to be... N The identifiers corresponding to the -2 memory states are different from the 2nd one. N -1 to 2 N The identifier corresponding to each memory state. Specifically, refer to... Figure 14 After the programming verification of the third-to-last memory state out of eight memory states (i.e., the third-to-last memory state LV5 has been verified), the main latch DS performs a non-target verification, which makes the identifiers corresponding to the first through sixth memory states stored in the main latch different from the identifiers corresponding to the seventh and eighth memory states. When DS is 1, it indicates that the programming verification of the memory state has passed, and when DS is 0, it indicates that the programming verification of the memory state has failed.

[0116] In some implementations, after the main latch performs a non-target verification, the bit lines are floated during programming to dump the first non-physical page information in the main latch. Since the non-target verification performed after LV3 programming verification passes, the main latch is used to identify memory states that have passed programming verification and memory states that have not passed programming verification. Therefore, the first non-physical page information in the original main latch DS can no longer be stored. After the non-target verification of the main latch DS, the bit lines are floated during programming to release the bias latch DL to dump the first non-physical page information in the main latch DS.

[0117] In some embodiments of this application, in relation to 2 N After the programming verification is performed in the penultimate memory state of the memory states, N page latches are released, so that the N page latches cache the programming data of each logical page in the N logical pages of the second physical page.

[0118] In some implementations, after programming verification of the penultimate memory state of the 8th memory state (i.e., the 7th memory state (LV6) has been verified), three of these page latches are released so that these three page latches cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 15 As shown, when the programming verification for LV6 passes (i.e., DS is 1), page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the previous page UP of the second physical page. At this point, all three page latches are released to store all programming data for each page in the three logical pages of the second physical page. Page latch D1 caches the programming data of the next page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, and page latch DC caches the programming data of the previous page MP of the second physical page. After this, whether DL is 1 can be used to determine if LV7 has passed the programming verification. If DS is 1, it indicates that the LV7 programming verification has passed, and the data from LV0 to LV7 has been written to the selected memory cell, and the first programming operation is complete. At this point, the programming data for the three logical pages to be written in the second programming step has been cached in the three page latches, allowing direct entry into the second programming process. If DS is 0, programming verification cannot continue.

[0119] In some embodiments, a non-volatile memory device is also provided, comprising a memory cell array and peripheral circuitry. The memory cells in the memory cell array are arranged in rows and columns. Each memory cell is configured to correspond to a single N-bit data segment (e.g., four-bit data). N One of the voltage levels. The peripheral circuitry is coupled to the memory cell array. The peripheral circuitry is configured to: sequentially and respectively perform first and second programming on the memory cell arrays on the first and second physical pages in a cache programming manner; and during the first / second programming, program the selected row of the memory cell based on the four logical pages of the first / second physical page. The four logical pages are the next page (LP), middle page (MP), previous page (UP), and extra page (XP).

[0120] The peripheral circuitry includes multiple page buffers coupled to bit lines. Each page buffer includes a main latch DS, three data latches D1, D2, and D3, and a buffer coupled to a data path latch DC. The main latch DS is configured to store first non-physical page information; the three data latches D1, D2, and D3, and a cache latch DC are used for the four logical pages of the first physical page / second physical page, serving as four page latches to temporarily store programming data to be written to the four logical pages during a single programming operation. The peripheral circuitry is also configured to: during the programming of the first physical page, when the first to second... (N-M) When the programming operation for the first memory state is completed, for the second... (N-M) Perform a programming verification operation on the programming operation corresponding to each memory state. On the second... (N-M) If the programming verification of each memory state passes, the first to second states stored in the main latch will be... (N-M) The identifier corresponding to each memory state is different from that of the second one. (N-M) +1 to 2 N The identifier corresponding to each memory state, and at least one of the four page latches used to cache programming data for at least one of the four logical pages of the second physical page, are released. Furthermore, during the programming of the first physical page, the programming data for one of the four logical pages of the second physical page is stored in the released page latch.

[0121] In some implementations, each memory cell has 16 memory states (levels) and is therefore set to correspond to 244 bits of data. 4 One of the levels. Each memory state can correspond to one of the two levels of the memory cell. 4 One of the threshold voltage (Vth) ranges. On the other hand, each memory state can correspond to one of the two values ​​in the selected row of the memory cell to be stored.4 One of the four-bit data. In some implementations, the programming data of the logical page stored in the page latch is encoded according to a preset rule to obtain a code corresponding to different memory states. Specifically, see Figure 16 This illustrates an example of binary encoding that shows a one-to-one mapping between 16 memory states (LV0 to LV15) and 16 segments after encoding conversion. Each segment in the four-bit data can include a four-bit binary code. The four-bit binary codes are derived from four logical pages. The four logical pages are low page LP, middle page MP, high page UP, and extra page XP. It can be seen that the four page latches sequentially store the programming data of the four logical pages: page latch D1 stores low page LP, page latch D2 stores middle page MP, page latch D3 stores high page UP, and page latch DC stores extra page XP. After encoding conversion, as shown... Figure 16 As shown, LV1 is encoded as 0001, where 0001 comes sequentially from LP / MP / UP / XP respectively. Similarly, the encoding order of other memory status bits is LP / MP / UP / XP, LV2 is encoded as 1001, and so on, LV7 is encoded as 1011, LV8 is encoded as 0000, and LV15 is encoded as 1110.

[0122] In some embodiments of this application, the peripheral circuit is configured to: in response to 2 N The second of the memory states N-1 Before performing programming verification on each memory state, the programming data of the corresponding logical page among the N logical pages of the first physical page is stored in at least one of the N page latches; and for the 2 N The second of the memory states N-1 After the memory state is verified by programming, the programming data of one logical page out of the N logical pages of the second physical page is stored in at least one of the N page latches.

[0123] In some implementations, before performing programming verification on the 8th memory state LV7 out of 16 memory states, DC may store programming data for one of the four logical pages of the first physical page (current XP). D1 may store programming data for the corresponding logical page of the first physical page (current LP), D2 may store programming data for the corresponding logical page of the first physical page (current MP), and D3 may store programming data for the corresponding logical page of the first physical page (current UP). After programming verification on the 8th memory state LV7 out of 16 memory states, programming data for one of the four logical pages of the second physical page is stored in the four page latches. See reference... Figure 17 To obtain details.

[0124] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N The second of the memory states N-1 After the programming verification of each memory state, the main latch performs a non-target verification. That is, the first to second states stored in the main latch DS are then verified. (N-1) The identifier corresponding to each memory state is different from that of the second one. (N-1) +1 to 2 N The identifier corresponding to each memory state. Specifically, refer to... Figure 17 After the programming verification of the 8th memory state out of 16 memory states (i.e., the 8th memory state LV7 has been verified), the identifiers corresponding to the 1st to 8th memory states stored in the main latch DS are different from the identifiers corresponding to the 9th to 16th memory states. That is, the identifiers of memory states that have passed programming verification in the main latch are different from the identifiers of memory states that have not passed programming verification. When DS is 1, it indicates that the programming verification of the memory state has passed, and when DS is 0, it indicates that the programming verification of the memory state has failed.

[0125] At this point, the main latch DS and page latches D1, D2, and D3 can form codes 0000, 0001, 0010, 0011, 0100, 0101, 0110, and 0111, representing LV8 to LV15 respectively. In other words, after LV3 programming verification passes, only three page latches and the main latch DS for non-target verification are needed to distinguish these eight memory states from LV8 to LV15. Therefore, after LV7 programming verification passes, the page latch DC can be released to cache the programming data of the lower page LP of the second physical page. The encoding state table is as follows: Figure 17 As shown. At this time, when DS is 1, it indicates that the LV7 programming verification has passed, and the page latch DC can be released to cache the programming data of the lower page LP of the second physical page.

[0126] Since the non-target verification passed after LV7 programming verification, the main latch is used to identify memory states that passed programming verification and memory states that failed programming verification. Therefore, the first non-physical page information in the original main latch DS can no longer be stored. After the non-target verification of the main latch DS, the bit lines are floated during programming to free the bias latch, thereby dumping the first non-physical page information in the main latch DS.

[0127] In some embodiments of this application, LV11 programming verifies that the segments corresponding to memory states LV0 to LV11 in the four page latches have all been written. At this time, four memory states LV12, LV13, LV14, and LV15 remain unprogrammed and unverified.

[0128] Since each bit in each logical page has two possible states, 0 and 1, the two page latches have four possible states (2^35 - 1^45). 2 =4). In non-target verification, all unprogrammed and unverified state bits of DS are 0, and the state bits of DS are only 1 after the programming and verification of the state bits are successful.

[0129] At this point, the main latch DS and page latches D2 and D3 can form codes 000, 001, 010, and 011, representing LV12 to LV15 respectively. In other words, after LV11 programming verification passes, only two page latches and the main latch DS for non-target verification are needed to distinguish these four memory states from LV12 to LV15. Therefore, after LV11 programming verification passes, page latch D1 can be released to cache the programming data of the lower page LP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoded state table is as follows... Figure 18 As shown.

[0130] Similarly, after LV13 programming verification passes, two memory states, LV14 and LV15, remain unverified. During non-target verification, all unprogrammed and unverified state bits of DS are 0, and after successful programming verification, the state bits of DS are 1. At this point, the main latch DS and page latch D3 can form codes 00 and 01, representing LV14 and LV15 respectively. In other words, after LV13 programming verification passes, only one page latch D3 and the main latch DS for non-target verification are needed to distinguish between the two memory states, LV14 and LV15. Therefore, after LV13 programming verification passes, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the high page UP of the second physical page, and the encoded state table is as follows. Figure 19 As shown.

[0131] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N After the programming verification of the penultimate memory state in the memory state, N page latches are released, so that these N page latches cache the programming data of each of the N logical pages of the second physical page.

[0132] In some implementations, after the penultimate memory state of the 16 memory states has been programmed and verified (i.e., the 15th memory state (LV14) has been verified), four of the ten page latches are released, such that these four page latches cache the programming data for each of the four logical pages of the second physical page (next LP, next MP, next UP, next XP).

[0133] like Figure 20 As shown, when the LV14 programming verification passes, i.e., DS is 1, page latch D3 can be released to cache the programming data of the high page UP of the second physical page. Consequently, page latch DC is further released to cache the programming data of the previous page XP of the second physical page. At this point, all four page latches are released to store all programming data for each page in the four logical pages of the second physical page. At this time, page latch D1 caches the programming data of the next page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, page latch D3 caches the programming data of the previous page UP of the second physical page, and page latch DC caches the programming data of the extra page XP of the second physical page.

[0134] After this, the status of DS (Distribution System) can be used to determine whether LV15 has passed the programming verification. If DS is 1, it indicates that the LV15 programming verification has passed, and the data from LV0 to LV15 has been written into the memory cell array, and the first programming is complete. At this point, the programming data for the four logical pages to be written in the second programming has been cached in the four page latches, allowing direct entry into the second programming process. If DS is 0, the programming verification cannot proceed.

[0135] In some embodiments of this application, after the peripheral circuitry included in the non-volatile memory device stores the programming data of four logical pages in four page latches, it transforms the programming data of the logical pages in the code according to a preset rule, and obtains... Figure 21 The table shown is a code status table after code conversion. For example... Figure 21 As shown, the data encoding for LV1 is 0001, where 0001 comes sequentially and respectively from LP / MP / UP / XP. Similarly, the encoding order for other memory states is LP / MP / UP / XP, LV2 is encoded as 1001, and so on, with LV8 encoded as 1110 and LV15 encoded as 1100.

[0136] In some implementations, before performing programming verification on LV8 of the 16 memory states, DC can store programming data for one of the four logical pages of the first physical page (current XP), D1 can store programming data for the corresponding logical page of the first physical page (current LP), D2 can store programming data for the corresponding logical page of the first physical page (current MP), and D3 can store programming data for the corresponding logical page of the first physical page (current UP). LV8 programming verification passed (LV8 passed) means that the segments corresponding to memory states LV0~LV8 in the four page latches have been completely written. At this time, there are still 7 memory states LV9, LV10, LV11 to LV15 that have not been programmed and have not been verified. Since each bit of each logical page has two possible states, 0 and 1, the three page latches have 8 possible states (2^3 + ... 3 =8). Excluding code 111, which is the same as the programmed and verified memory state, there are 7 other codes that can represent LV9, LV10, LV11 to LV15 respectively. In other words, after successful LV8 programming verification, only three page latches are needed to distinguish these 7 memory states (LV9, LV10, LV11 to LV15). Therefore, after successful LV8 programming verification, page latch DC can be released to store the programming data of the lower page LP of the second physical page in the released page latch. The encoded state table is as follows: Figure 22 As shown.

[0137] Similarly, after LV12 programming verification is successful, LV13, LV14, and LV15 memory states remain unprogrammed and unverified. Since each bit in a logical page has two possible states, 0 and 1, the page latch can have four possible states (2^35 - 1^45). 2 =4). Excluding code 11, which is the same as the programmed and verified memory state, the remaining three codes 00, 01, and 10 can represent LV13, LV14, and LV15, respectively.

[0138] In other words, after LV12 programming verification passes, only two page latches are needed to distinguish between the three memory states: LV13, LV14, and LV15. Therefore, after LV12 programming verification passes, page latch D1 can be released, allowing it to cache the programming data of the lower page LP of the second physical page. Consequently, page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoded status table is as follows... Figure 23 As shown.

[0139] In some embodiments of this application, the peripheral circuitry is further configured to perform a non-target verification after performing programming verification on the third-to-last memory state out of 16 memory states. The non-target verification causes the first to second memory states stored in the main latch to be... N The identifiers corresponding to the -2 memory states are different from the 2nd one. N -1 to 2 N The identifiers correspond to the memory states. In some implementations, after the programming verification of the third-to-last memory state out of the 16 memory states (i.e., the 14th memory state (LV3) has been verified), the main latch DS performs a non-target verification. Non-target verification causes the identifiers corresponding to the 1st through 14th memory states stored in the main latch to differ from the identifiers corresponding to the 15th and 16th memory states. When DS is 1, it indicates that the programming verification of the memory state has passed, and when DS is 0, it indicates that the programming verification of the memory state has failed. Figure 23 The binary encoding shown can be as follows Figure 24 The update shown allows all data bits in LV13 to be updated to 1 because they are no longer needed in the current first programming operation. Figure 24 As shown, at this point, the main latch DS and page latch D3 can form codes 01 and 00, representing LV14 and LV15 respectively. In other words, only one page latch D3 and one main latch DS used for performing non-target verification can distinguish between the two memory states LV14 and LV15. Therefore, after the LV13 programming verification passes, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Thus, page latch DC caches the programming data of the upper page UP of the second physical page. That is, the next MP can be passed from DC to D2, and the programming data of the next UP can be cached in DC.

[0140] Because the non-target verification performed after LV13 verification passed, the identifiers corresponding to memory states 1 through 14 stored in the main latch are different from those corresponding to memory states 15 and 16. Therefore, the first non-physical page information in the original main latch DS can no longer be stored. After the non-target verification is performed in the main latch DS, the bit lines are floated during programming to release the bias latch DL and dump the first non-physical page information in the main latch DS.

[0141] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N After the programming verification of the penultimate memory state in the memory state, N page latches are released, so that these N page latches cache the programming data of each of the N logical pages of the second physical page.

[0142] In some implementations, after the programming verification of the penultimate memory state of the 16 memory states (i.e., the 15th memory state (LV14) has been verified), four page latches are released so that these four page latches cache the programming data of each of the four logical pages (next LP, next MP, next UP, next XP) of the second physical page.

[0143] like Figure 25 As shown, when the LV14 programming verification passes and DS is 1, page latch D3 can be released to cache the programming data of the previous page UP of the second physical page, thereby further releasing page latch DC to cache the programming data of the additional page XP of the second physical page. At this time, all four page latches are released to store all the programming data of the four logical pages of the second physical page. At this time, page latch D1 caches the programming data of the next page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, page latch D3 caches the programming data of the previous page UP of the second physical page, and page latch DC caches the programming data of the additional page XP of the second physical page.

[0144] After this, the status of DS (Distribution System) can be used to determine whether LV15 has passed the programming verification. If DS is 1, it indicates that the LV15 programming verification has passed, and the data from LV0 to LV15 has been written to the selected memory cells, and the first programming is complete. At this point, the programming data for the four logical pages to be written in the second programming is cached in the four page latches, allowing direct entry into the second programming process. If DS is 0, the programming verification cannot proceed.

[0145] This disclosure also provides a non-volatile memory device. The non-volatile memory device includes a memory cell array and peripheral circuitry. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to correspond to a 2-bit data segment. 3 One of the voltage levels. The peripheral circuitry is configured to: sequentially and respectively perform first programming and second programming on the memory cell arrays of the first and second physical pages in a cache programming manner; and during the first / second programming, program the selected row of the memory cell based on the three logical pages of the first / second physical page. The three logical pages are the next page (LP), the middle page (UP), and the high page (UP).

[0146] The peripheral circuitry includes multiple page buffers, each coupled to a bit line. Each page buffer includes a main latch, a bias latch DL, (N-1) data latches, and a cache latch coupled to the data path. The bias latch is configured to store second non-physical page information. The (N-1) data latches and the cache latch are used to perform a single programming operation on N logical pages of the first physical page / second physical page, and temporarily store programming data to be written to the N page latches of the N logical pages (e.g., for TLC, N=3).

[0147] The peripheral circuitry is configured to: disable the bit line bias function, release the bias latch to replace one of the N page latches during the programming of the first physical page for programming verification of the memory state; and release one of the N page latches to cache the programming data of one logical page among the N logical pages of the second physical page. Furthermore, during the programming of the first physical page, the programming data of one logical page among the N logical pages of the second physical page is stored in the released page latch. In some embodiments, the non-volatile memory device includes a three-dimensional NAND flash memory device.

[0148] In some embodiments of this application, the peripheral circuitry is further configured to: during the programming of the first physical page / second physical page, use the ISPP programming method to program the first to second physical pages. (N-M) Programming of memory states.

[0149] In some embodiments of this application, the second non-physical page information includes voltage bias information of the corresponding bit line.

[0150] In some embodiments of this application, the peripheral circuit is further configured to: in response to 2 N The second of the memory states N-1 Before performing programming verification on memory state +1, the programming data of the corresponding logical page among the N logical pages of the first physical page is stored in at least one of the page latches. In some implementations, before performing programming verification on the fifth memory state LV4 out of eight memory states, DC may store the programming data of one logical page (current UP) of the three logical pages of the first physical page, D1 may store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 may store the programming data of the corresponding logical page (current MP) of the second physical page.

[0151] Execution of programming data on different logical pages stored in page latches Figure 12 After the same encoding conversion shown, and in the case of 2 N The second of the memory states N-1After programming verification of +1 memory states, one logical page from the N logical pages of the second physical page is stored in the N pages of at least one of these latches. That is, after successful LV4 programming verification, page latch DC is released, causing the released page latch to cache the programming data of the lower page LP of the second physical page. The encoding state table is as follows: Figure 13 As shown.

[0152] In some embodiments of this application, the peripheral circuit is further configured to: in 2 N The bitline bias function is disabled after programming verification of the third-to-last memory state out of eight memory states. In some implementations, the bitline bias function is disabled after programming verification of the third-to-last memory state LV5 out of eight memory states. Figure 26 This is an encoding state table after the bit line bias function is disabled, as provided in some embodiments of this application. It can be seen that the bias latch DL is in an idle state after the bit line bias function is disabled, and can be used to replace the page latch for memory state programming verification. Then, the page latch D1 can be released to cache the programming data of the next page LP of the second physical page, thereby further releasing the page latch DC to cache the programming data of the middle page MP of the second physical page.

[0153] In some embodiments of this application, the peripheral circuitry is further configured to reduce the step increment of the programming voltage after the bit line bias function is disabled. Since the bit line bias function itself is used to reduce the distribution width of the threshold voltage of the memory cell, it can be compensated for by reducing the step increment of the programming voltage after the bit line bias function is disabled. In this way, the page latch can be replaced by a bias latch without affecting the function of the non-volatile memory device.

[0154] In some embodiments of this application, the master latch DS is configured to store verification information and programming information.

[0155] In some embodiments of this application, the peripheral circuit is further configured to: in 2 N After programming verification in the penultimate memory state of the memory state, N page latches are released, allowing the data latches to cache each of the N logical pages of the next physical page.

[0156] In some implementations, after verifying the penultimate memory state out of eight (i.e., the seventh memory state (LV6) has been verified), three of these page latches are released, allowing these three page latches to cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. The encoding state table is as follows: Figure 27As shown. After the LV6 programming verification passes, there is still a memory state LV7 that fails the programming verification. Since each bit of each logical page has two possible states, 0 and 1, the latch has 2 possible states (2^32 - 1^32). 1 =2). In other words, after LV6 programming verification passes, only one bias latch DL is needed to determine whether LV7 programming verification passes. Therefore, after LV6 programming verification passes, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, thereby further releasing page latch DC to cache the programming data of the upper page UP of the second physical page.

[0157] At this point, the three page latches are released so that all programming data for each page is stored in the three logical pages of the second physical page. Page latch D1 caches the programming data for the next page (LP) of the second physical page, page latch D2 caches the programming data for the middle page (MP) of the second physical page, and page latch DC caches the programming data for the previous page (MP) of the second physical page.

[0158] After this, the value of DL can be used to determine whether LV7 has passed the programming verification. If DL is 1, it indicates that the LV7 programming verification has passed, meaning that the data from LV0 to LV7 has been written to the selected memory location, and the first programming step is complete. At this point, the programming data for the three logical pages to be written in the second programming step is cached in the page latch, allowing direct entry into the second programming process. If DL is 0, the programming verification has failed.

[0159] Based on the non-volatile storage device provided by the above embodiments of this application, a programming method for the non-volatile storage device is also provided. The non-volatile storage device includes a storage cell array and peripheral circuitry. The storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2-bit N-bit data segment. NOne of the levels, where N is an integer greater than 1. The peripheral circuitry includes multiple page buffers, each coupled to a bit line. The method includes: storing N logical pages of a first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffers and a cache latch coupled to the data path. Second non-physical page information is stored in a bias latch in the page buffers. During the programming of the first physical page, the bit line bias function is disabled to release the bias latch in place of one of the N page latches for memory state programming verification, and one of these N page latches is released. During the first programming of the first physical page, after the first programming in cache programming and before the second programming of the second physical page, and during the first programming of the first physical page, the programming data of one of the N logical pages in the page is stored in the released page latch.

[0160] Figure 28 These are schematic flowcharts illustrating some implementations of programming methods for non-volatile memory devices. For example... Figure 28 As shown, the programming method includes the following steps:

[0161] Step S301: Store the N logical pages of the first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path. After storing the programming data of the three logical pages LP, MP, and UP in the page latches, perform encoding conversion on the page data stored in the data latches according to preset rules to obtain binary codes corresponding to different memory states, such as... Figure 12 As shown in more detail below.

[0162] In step S301 above, each memory cell is configured to correspond to a 3-bit data segment in one of the 8 memory states. 3 One of the three logic pages of the first physical page (current UP) can be stored by DC before programming verification in the fifth memory state LV4 of the eight memory states. D1 can store the programming data of the corresponding logic page of the first physical page (current LP), and D2 can store the programming data of the corresponding logic page of the first physical page (current MP). Subsequently, the programming data of the different logic pages temporarily stored in the page latches is ANDed with the data in the latch. Figure 12 The same encoding conversion is performed. After successful LV4 programming verification, the page latch DC is released, allowing the released page latch to cache the programming data of the lower page LP of the second physical page. The encoding status table can be found in [link to table]. Figure 13 .

[0163] Step S302: Store the second non-physical page information in the bias latch in the page buffer. The second non-physical page information includes the voltage bias information of the corresponding bit line.

[0164] Step S303: During the programming of the first physical page, the bit-line bias function is disabled to release the bias latch in place of one of the N page latches to perform programming verification of the memory state, and one of the N page latches is released. Before the second programming of the second physical page after the first programming in cache programming and during the first programming of the first physical page, the programming data of one of the N logical pages is stored in the released page latch.

[0165] In step S303 above, first programming / second programming is performed on the first physical page / second physical page, including using the Incremental Step Pulse Programming (ISPP) programming method to program the first to second physical pages. (N-M) Each memory state is programmed to perform programming operations.

[0166] In step S303 above, disabling the bit line offset function includes: on 2 N After programming verification in the third-to-last memory state of the memory states, disable the bit line bias function. Specifically, refer to... Figure 26 After verifying the programming of the penultimate memory state LV5 out of the eight memory states, the bit line bias function is disabled. Figure 26 This application provides an encoding state table after disabling the bit line bias function in some embodiments. It can be seen that the bias latch DL is idle after the bit line bias function is disabled and can be used in place of the page latch for memory state identification. Then, the page latch D1 can be released to cache the programming data of the next page LP of the second physical page, thereby further releasing the page latch DC to cache the programming data of the middle page MP of the second physical page.

[0167] In some embodiments of this disclosure, the programming voltage step increment is reduced after the bit line bias function is disabled. Since the bit line bias function itself is designed to reduce the distribution width of the threshold voltage of the memory cell, its disabling can be compensated for by reducing the programming voltage step increment. In this way, the page latch can be replaced by a bias latch without affecting the functionality of the non-volatile memory device.

[0168] In some embodiments of this application, in relation to 2 N After the programming verification is performed in the penultimate memory state of the memory states, N page latches are released, so that the N page latches cache the programming data of each logical page in the N logical pages of the second physical page.

[0169] In some implementations, after programming verification of the penultimate memory state of the 8th memory state (i.e., the 7th memory state (LV6) has been verified), three of these page latches are released, allowing them to cache the programming data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. The encoded state table is as follows: Figure 27 As shown. After the LV6 programming verification passes, there is still a memory state LV7 that fails the programming verification. Since each bit of each logical page has two possible states, 0 and 1, a latch has two possible states (2... 1 =2).

[0170] In other words, after LV6 programming verification passes, only one bias latch DL is needed to determine whether LV7 programming verification passes. Therefore, after LV6 programming verification passes, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Consequently, page latch DC is further released to cache the programming data of the upper page UP of the second physical page.

[0171] At this point, the three page latches are released so that all programming data for each page is stored in the three logical pages of the second physical page. Page latch D1 caches the programming data for the next page (LP) of the second physical page, page latch D2 caches the programming data for the middle page (MP) of the second physical page, and page latch DC caches the programming data for the previous page (MP) of the second physical page.

[0172] Then, the value of DL (Level 7) can be used to determine whether LV7 has passed the programming verification. If DL is 1, it indicates that the LV7 programming verification has passed, meaning that the corresponding segments from LV0 to LV7 have been written to the selected memory cells, and the first programming operation is complete. At this point, the programming data for the three logical pages to be written in the second programming operation is already cached in the page latches, allowing direct entry into the second programming process. If DL is 0, the programming verification has failed. Since the three page latches can cache the programming data for each of the three logical pages (next LP, next MP, and next UP) of the second physical page after the programming verification of LV6, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0173] In some embodiments of this application, another non-volatile memory device is also provided. In this non-volatile memory device, the peripheral circuitry stores the programming data of four logic pages in four page latches. Then, the programming data of the logic pages stored in the page latches is encoded and converted according to a preset method to obtain the desired result. Figure 21 The encoding status table shown.

[0174] In some embodiments of this application, before performing LV8 programming verification in 16 memory states, DC can store programming data for one of the four logical pages of the first physical page (current XP), D1 can store programming data for the corresponding logical page of the first physical page (current LP), D2 can store programming data for the corresponding logical page of the first physical page (current MP), and D3 can store programming data for the corresponding logical page of the first physical page (current UP). After the LV8 programming verification is successful, the page latch DC is released, causing the released page latch to cache the programming data of the lower page LP of the second physical page. The encoding state table is as follows: Figure 22 As shown. Therefore, after the LV12 programming verification passes, page latch D1 is released to cache the programming data of the lower page LP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoding status table is as follows. Figure 23 As shown.

[0175] In some embodiments of this application, the peripheral circuit is further configured to: in 2 N The bitline bias function is disabled after programming verification in the third-to-last memory state of the memory states.

[0176] In some implementations, after programming verification of the penultimate memory state LV13 out of 16 memory states, the bit-line bias function is disabled to release the bias latch DL to replace one of the four page data latches in the memory for programming verification of the memory state, and to release one of the four page latches to cache the programming data of one of the four logical pages of the second physical page. Furthermore, during programming of the first physical page, the programming data of one of the four logical pages of the second physical page is stored in the released page latch.

[0177] Figure 29This application provides an encoding state table after disabling the bit line bias function in some embodiments. It can be seen that the bias latch DL is idle after the bit line bias function is disabled, and therefore can be used in place of one of the four page latches for programming verification of the memory state. Therefore, page latch D2 can be further released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the upper page UP of the second physical page.

[0178] In some embodiments of this application, the peripheral circuitry is further configured to reduce the step increment of the programming voltage after the bit line bias function is disabled. Since the bit line bias function itself is designed to reduce the distribution width of the threshold voltage of the memory cell, this can be compensated for by reducing the step increment of the programming voltage after the bit line bias function is disabled. In this way, one page latch of the data latch can be replaced by a bias latch, and the function of the non-volatile memory device remains unaffected.

[0179] In some embodiments of this application, in relation to 2 N After the programming verification is performed in the penultimate memory state of the memory states, N page latches are released, so that the N page latches cache the programming data of each logical page in the N logical pages of the second physical page.

[0180] In some implementations, after the penultimate memory state of the 16 memory states has been programmed and verified (i.e., the 15th memory state (LV14) has been verified), four of these page latches are released, such that these four page latches cache the programming data for each of the four logical pages of the second physical page (next LP, next MP, next UP, next XP).

[0181] Encoding status table as follows Figure 30 As shown. After the programming verification of LV14 passed, there is another memory state, LV15, that failed the programming verification. Since each bit of each logical page has two possible states, 0 and 1, a latch has two possible states (2... 1 =2). In other words, after LV6 programming verification passes, only one bias latch DL is needed to determine whether LV7 programming verification passes. Therefore, after LV14 programming verification passes, page latch D3 can be released to cache the programming data of the previous page UP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the additional page XP of the second physical page.

[0182] At this point, the four page latches are released to store all programming data for each page in the four logical pages of the second physical page. Page latch D1 caches the programming data for the next page (LP) of the second physical page, page latch D2 caches the programming data for the middle page (MP) of the second physical page, page latch D3 caches the programming data for the previous page (UP) of the second physical page, and page latch DC caches the programming data for the extra page (XP) of the second physical page. Then, whether DL is 1 can be used to determine if LV15 has passed programming verification. If DL is 1, it indicates that LV15 programming verification has passed, meaning that the segments corresponding to LV0~LV15 have been written to the selected memory locations, and the first programming is complete. At this point, the programming data for the four logical pages to be written in the second programming is cached in the four page latches, allowing direct entry into the second programming process.

[0183] If DL is 0, the programming validation fails, and the programming validation is determined to continue.

[0184] Some embodiments of this application provide solutions that can temporarily store programming data for various logical pages required for the second programming in a page latch during the first programming phase. That is, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without requiring a data loading window.

[0185] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance provided herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0186] The breadth and scope of this disclosure should not be limited by any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

[0187] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically described in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

Claims

1. A storage device, comprising: A storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2^N bit data. N One of the levels, where N is an integer greater than 1; and Peripheral circuitry, coupled to the memory cell array, is configured as follows: The memory cell arrays in the first physical page and the second physical page are sequentially programmed and respectively programmed using cache programming. During the first and second programming, at least the selected rows of the memory cells are programmed based on N logical pages of the first and second physical pages. The peripheral circuitry includes page buffers coupled to bit lines, each page buffer comprising: Bias latches, (N-1) data latches, and cache latches coupled to the data path. The bias latch is configured to store second non-physical page information, and the (N-1) data latches and cache latches are configured to act as N page latches during the programming of the N logical pages of the first physical page and the second physical page, to temporarily store programming data to be written into the N logical pages. The peripheral circuit is further configured as follows: During the programming of the first physical page, the bit line bias function is disabled to release the bias latch in place of one of the N page latches to perform programming verification of the memory state. Release one of the N page latches to cache the programming data of one of the N logical pages of the second physical page; and During the programming of the first physical page, the programming data of one of the N logical pages of the second physical page is stored in the released page latch.

2. The storage device according to claim 1, wherein, The peripheral circuit is also configured to: During the programming of the first physical page and the second physical page, the Incremental Step Pulse Programming (ISPP) programming method is used to program the first to the second physical page. (N-M) The memory states are programmed, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

3. The storage device according to claim 1, wherein, The peripheral circuit is also configured to: After disabling the bit line bias function, reduce the step increment of the programming voltage.

4. The storage device according to claim 1, wherein, The second non-physical page information includes the voltage bias information of the corresponding bit line.

5. The storage device according to claim 1, wherein, The peripheral circuit is also configured to: In 2 N The bitline bias function is disabled after programming verification in the third-to-last memory state of the memory states.

6. The storage device according to claim 1, wherein, Each page buffer includes a main latch configured to store first non-physical page information, wherein the first non-physical page information includes verification information and programming information.

7. The storage device according to claim 1, wherein Each storage unit is configured to correspond to 2 bits of data. 3 One of the levels; The peripheral circuitry is further configured to program the selected row of the memory cell based on three logical pages of the first physical page and the second physical page; and The two data latches and the cache latch are configured to function as three page latches during the programming process of the three logical pages of the first physical page and the second physical page, to temporarily store programming data to be written into the three logical pages.

8. The storage device according to claim 1, wherein Each storage unit is configured to correspond to a single four-bit data segment. 4 One of the levels; The peripheral circuitry is further configured to program the selected row of the memory cell based on four logical pages of the first physical page and the second physical page; and The three data latches and the cache latch are configured to function as four page latches during the programming process of the four logical pages of the first physical page and the second physical page, to temporarily store programming data to be written into the four logical pages.

9. The storage device according to claim 1, wherein, The bias latch is configured to store voltage bias information for the corresponding bit line.

10. The storage device of claim 1, further comprising a three-dimensional NAND flash memory device.

11. A method for programming a storage device, wherein, The storage device includes a memory cell array and peripheral circuitry coupled to the memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to correspond to a 2^N bit data. N One of the level values, where N is an integer greater than 1; wherein the peripheral circuitry includes multiple page buffers respectively coupled to the bit lines; wherein the method includes: The N logical pages of the first physical page corresponding to the current first programming are stored in N page latches, wherein the N page latches include (N-1) data latches in the page buffer and cache latches coupled to the data path; The second non-physical page information is stored in the bias latch in the page buffer; During the programming of the first physical page, the bit line bias function is disabled to release the bias latch in place of one of the N page latches to perform programming verification of the memory state. Release one of the N page latches to cache the programming data of one of the N logical pages of the second physical page; and During the programming of the first physical page, the programming data of one of the N logical pages of the second physical page is stored in the released page latch.

12. The method of claim 11, further comprising: During the programming of the first physical page and the second physical page, the Incremental Step Pulse Programming (ISPP) programming method is used to program the first to the second physical page. (N-M) The memory states are programmed, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

13. The method according to claim 11, wherein, After disabling the bit line bias function, reduce the step increment of the programming voltage.

14. The method according to claim 11, wherein, The second non-physical page information includes the voltage bias information of the corresponding bit line.

15. The method according to claim 11, wherein, In 2 N The bitline bias function is disabled after the programming verification in the third-to-last memory state of the memory states.

16. The method of claim 11, further comprising: The first non-physical page information in the main latch is stored in the page buffer, wherein the first non-physical page information includes verification information and programming information.

17. The method of claim 11, further comprising: The selected row of the storage unit is programmed based on the three logical pages of the first physical page and the second physical page, wherein two data latches and the cache latch are configured to act as three page latches during the programming process of the three logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the three logical pages.

18. The method of claim 11, further comprising: The selected row of the storage unit is programmed based on the four logical pages of the first physical page and the second physical page, wherein three data latches and the cache latch are configured to act as four page latches during the programming process of the four logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the four logical pages.

19. A memory system comprising: Storage device, including: A storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a 2^N bit data. N One of the levels, where N is an integer greater than 1; and Peripheral circuitry, coupled to the memory cell array, is configured as follows: The memory cell arrays in the first physical page and the second physical page are sequentially programmed and respectively programmed using cache programming. During the first and second programming, at least the selected rows of the memory cells are programmed based on N logical pages of the first and second physical pages. The peripheral circuitry includes page buffers coupled to bit lines, each page buffer comprising: Bias latches, (N-1) data latches, and cache latches coupled to the data path. The bias latch is configured to store second non-physical page information, and the (N-1) data latches and cache latches are configured to act as N page latches during the programming of the N logical pages of the first physical page and the second physical page, to temporarily store the programming data to be written into the N logical pages. The peripheral circuit is further configured as follows: During the programming of the first physical page, the bit line bias function is disabled to release the bias latch in place of one of the N page latches to perform programming verification of the memory state. Release one of the N page latches to cache the programming data of one of the N logical pages of the second physical page; and During the programming of the first physical page, the programming data of one logical page out of the N logical pages of the second physical page is stored in the released page latch; and A memory controller, which is coupled to the storage device and configured to control the operation of the storage device.

20. The memory system of claim 19, wherein, Each page buffer includes a main latch, and the main latch is coupled to the data path and configured to store first non-physical page information, wherein the peripheral circuitry is further configured to: During the programming of the first physical page and the second physical page, the Incremental Step Pulse Programming (ISPP) programming method is used to program the first to the second physical page. (N-M) The memory states are programmed, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

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