Planarization method, trench isolation structure and chip

Abstract

The present application belongs to the field of microelectronics technology, and particularly relates to a planarization method, a channel isolation structure and a chip; a preset channel structure, i.e., a ninth channel isolation structure (099), is pretreated through an in-situ steam generation (ISSG) process, i.e., a third film construction step (300) is processed, a target medium or polysilicon is consumed by a preset proportion, so as to eliminate the sharp corners and residue flaws caused by the loading effect (LE) in the chemical mechanical polishing (CMP) planarization process; a sixth isolation structure (106) can be implemented by using an oxide-nitride-oxide (ONO) multilayer structure, and the (polysilicon) residue on the current medium layer is simultaneously removed; the inline monitoring index and the data retention (DRT) characteristics and yield rate (YR) of the finished product are effectively improved, and the present application is particularly suitable for the scene that there is a difference in pattern density in the shallow trench isolation (STI) structure, i.e., the first working area and the second working area.