Successive approximation register analog-to-digital converter with adaptive current or voltage parameter adjustment

Abstract

This application relates to successive approximation register analog-to-digital converters with adaptive current or voltage parameter adjustment. Systems and methods relate to a successive approximation analog-to-digital converter (SAR ADC). In one aspect, a method includes sampling an input voltage by a sampling and digital-to-analog conversion (DAC) circuit to obtain a sampled voltage. The method also includes determining states of a plurality of bits corresponding to the sampled voltage by a comparator coupled to a set of storage circuits. The comparator has a current parameter or a voltage parameter adjusted based on a conversion margin. Adjustment of the current parameter or the voltage parameter affects a speed of determining the states of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, a SAR ADC is configured to perform the method.

Description

Technical Field

[0001] This disclosure generally relates to communication systems, including (but not limited to) communication systems that include a successive approximation register analog-to-digital converter (SAR ADC). Background Technology

[0002] Recent advancements in communication and computing devices demand high data rates. For example, network switches, routers, hubs, or any communication device can exchange data at high speeds (e.g., 1 Mbps to 100 Gbps) to stream data in real time or process large volumes of data seamlessly. To efficiently process data in the digital domain, the amplitude or voltage of a signal can be represented by multiple bits, and signals can be exchanged between two or more communication devices via cable or wireless media. For example, a 1.2V signal can be represented as a byte (B), such as 00010110, and a 1.3V signal can be represented as a B, such as 00011001. To convert the voltage of an input signal into corresponding bits, some communication devices implement a SAR ADC. For example, a SAR ADC can determine multiple bits corresponding to an input signal through successive approximations. Variations in process technology, voltage, and temperature (PVT) can affect the speed, accuracy, and / or precision of a SAR ADC. Summary of the Invention

[0003] In one aspect, an apparatus is described. The apparatus includes: a digital-to-analog converter (DAC) circuit, a comparator circuit coupled to the DAC circuit, a set of storage circuitry coupled to the comparator circuit and the DAC circuit, and control circuitry coupled to the comparator circuit. The set of storage circuitry is configured to store a plurality of bits corresponding to an input voltage. The control circuitry is configured to adjust a bias current used in the comparator circuit, a threshold voltage used in the comparator circuit, or a supply voltage used in the comparator circuit in response to a conversion margin.

[0004] On the other hand, a device is described. The device includes a receiver. The receiver includes an analog-to-digital converter (ADC) circuit. The ADC circuit includes a comparator and a processor. The processor is configured to determine a conversion margin and use the conversion margin to adjust the current or voltage used in the comparator.

[0005] On the other hand, a method is described. The method includes: sampling an input voltage via a comparator coupled to a digital-to-analog converter; determining the state of a plurality of bits corresponding to the input voltage via the comparator coupled to a set of storage circuits, wherein the comparator has a current parameter or voltage parameter adjusted based on a conversion margin, wherein the adjustment of the current parameter or the voltage parameter affects the speed at which the state of the bit is determined; and storing the bit in the set of storage circuits. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through reference to the detailed description taken in conjunction with the accompanying drawings, in which similar reference characters consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements.

[0007] Figure 1A It is a general block diagram depicting a network environment comprising one or more access points communicating with one or more devices or stations, according to one or more embodiments.

[0008] Figure 1B and 1C This is a general block diagram depicting a computing device that can be used in conjunction with the methods and systems described herein, according to one or more embodiments.

[0009] Figure 2 It is a general block diagram depicting a communication device according to one or more embodiments.

[0010] Figure 3A It is capable of being based on one or more embodiments Figure 2 The diagram illustrates the SAR ADC used in the communication device described herein.

[0011] Figure 3B This is a more detailed diagram of a portion of the SAR ADC illustrated in Figure 3 according to one or more embodiments.

[0012] Figure 4 It is according to one or more embodiments for Figure 3A The diagram illustrates the switching state circuit of the SAR ADC.

[0013] Figure 5 This demonstrates the invention based on one or more embodiments. Figure 4 The timing diagram of the transition state signal provided by the transition state circuit described herein.

[0014] Figure 6 According to one or more embodiments Figure 3A The diagram illustrates the current source circuit of the comparator used in the SAR ADC.

[0015] Figure 7 It is according to one or more embodiments for Figure 3A The diagram illustrates the comparator driver circuit of the SAR ADC.

[0016] Figure 8 It is according to one or more embodiments for Figure 3A The diagram illustrates the alternative comparator driver circuit for the SAR ADC.

[0017] Figure 9 This illustrates a method for using one or more embodiments. Figure 3A The process described herein is an adaptive operation procedure for optimizing the performance and power efficiency of the SAR ADC.

[0018] Figure 10 According to one or more embodiments Figure 3A A graph of the probability versus conversion margin of the SAR ADC.

[0019] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0020] For the purpose of reading the description of the various embodiments below, the following description of the sections of the specification and their corresponding contents may be helpful:

[0021] Section A describes the network and computing environments that can be used to practice the embodiments described herein; and

[0022] Section B describes embodiments of a system and method for an energy-efficient SAR ADC according to one or more embodiments.

[0023] The various embodiments disclosed herein relate to apparatuses for data communication. In some embodiments, the apparatus includes a SAR ADC used in physical layer products or the SAR ADC itself. In some embodiments, the SAR ADC is high-speed (e.g., resolution greater than 7 and operating speed of several hundred megasamples per second). In some embodiments, the SAR ADC is adaptively tuned for PVT operation to appropriately increase speed or reduce noise. In some embodiments, adaptive feedback techniques may adjust the comparator driver threshold to increase operating speed in the slow corner, while in the fast (FF) corner there is no common-mode voltage V. CM The correlation error or has a very small common-mode voltage V CM Related errors. Advantageously, the systems and methods described herein can provide large SAR ADC arrays with reduced latency, reduced area, reduced mismatch, and increased bandwidth.

[0024] In some embodiments, an optimized (e.g., for power consumption and performance) SARADC with adaptive current or voltage parameter adjustment is provided. The SAR DAC is configured to adjust the current or voltage parameters associated with the comparator to adjust the speed of comparator operation. In some embodiments, the system and method adjust the comparator bias current or threshold voltage to achieve a very high-speed comparator with low noise and reduced power consumption (10% or more reduction). In some embodiments, the current or voltage parameters are adjusted or adaptively tuned according to a conversion margin. In some embodiments, the conversion margin indicates the amount of unused time during the comparator operation available within a sampling cycle. In some embodiments, the conversion margin is determined using a time delay and a probability relationship. In some embodiments, the current or voltage parameters include a current bias for the comparator current source, a threshold voltage for the comparator driver, a current bias for the comparator driver, and / or a supply voltage (e.g., V for the comparator). DD (Or other voltages supplied by the regulator on the board or die). In some embodiments, the SAR ADC uses operating current to sense conditions to determine probabilistic relationships and adjust voltage and current parameters.

[0025] In some embodiments, the SAR ADC includes a data path configured to improve speed. The data path uses an enable signal (enable zero) to directly reset the capacitor-to-analog converter (CAPDAC) circuitry, which achieves faster reset and improved CAPDAC circuitry settling time. In some embodiments, the CAPDAC circuitry receives feedback signals directly from the ratio latches instead of a separate driver, thereby improving speed (e.g., by significantly reducing clock path delay) and reducing layout complexity. In some embodiments, the most significant bit (MSB) ratio latch is driven by a single comparator driver, while the remaining latches are driven by a single driver and another driver. In some embodiments, this driver configuration reduces the load on the single comparator driver, thereby reducing the MSB settling time and reducing layout complexity.

[0026] The various embodiments disclosed herein relate to an apparatus. The apparatus includes a CAPDAC circuit for sampling an input voltage to obtain a first sampled voltage, a comparator circuit coupled to the CAPDAC circuit, a set of storage circuitry coupled to the comparator circuit and the CAPDAC circuit, and control circuitry coupled to the comparator circuit. The control circuitry is configured to adjust the bias current used in the comparator circuit, the threshold voltage used in the comparator circuit, and / or the supply voltage used in the comparator circuit in response to a conversion margin. The set of storage circuitry is configured to store a plurality of bits corresponding to the input voltage.

[0027] In some embodiments, the conversion margin indicates the unused time during the comparison operation available within a sampling cycle. In some embodiments, control circuitry is configured to determine the conversion margin and periodically adjust the bias current, threshold voltage, and / or supply voltage. In some embodiments, control circuitry is configured to determine the conversion margin and adjust the bias current, threshold voltage, and / or supply voltage when the device is powered on. In some embodiments, control circuitry is configured to adjust the bias current and threshold voltage. In some embodiments, control circuitry is configured to adjust the bias current in response to the conversion margin, and the bias current is used for a current mirror or driver in the comparator circuitry. In some embodiments, control circuitry is configured to adjust the threshold voltage in response to the conversion margin, and the threshold voltage is used by a driver in the comparator circuitry. In some embodiments, control circuitry is configured to adjust the supply voltage in response to the conversion margin. In some embodiments, the device further includes a conversion state circuitry configured to provide a conversion state signal, and the conversion state circuitry includes a variable delay circuitry. In some embodiments, control circuitry adjusts the variable delay circuitry to determine the conversion margin.

[0028] The various embodiments disclosed herein relate to devices including receivers. These devices can be used in communication applications. The receiver includes analog-to-digital converter (ADC) circuitry comprising a comparator and a processor. The processor is configured to determine a conversion margin and use the conversion margin to adjust the current or voltage used in the comparator.

[0029] In some embodiments, the processor provides one or more selection signals to the multiplexer in the comparator to adjust the current or voltage. In some embodiments, the processor is configured to adjust the current and determine a probability that the conversion margin is greater than a first threshold. In some embodiments, the processor adjusts the current when the current is higher than a minimum current value and the probability is higher than a second threshold.

[0030] In some embodiments, the processor is configured to adjust the voltage and determine the probability that the conversion margin is greater than a first threshold. The processor adjusts the voltage when the voltage is higher than a minimum voltage value and the probability is higher than a second threshold. The voltage is a threshold voltage of the driver in the comparator. In some embodiments, the processor is configured to adjust the voltage and determine the probability that the conversion margin is greater than the first threshold. The processor adjusts the voltage when the current is higher than a minimum voltage value and the probability is higher than the second threshold. The voltage is a supply voltage of the driver in the comparator. In some embodiments, the comparator and processor are provided in an integrated circuit package. In some embodiments, the processor is on-chip integrated logic circuitry or an analog correction loop.

[0031] In some embodiments, the processor is configured to adjust the supply current such that the probability of a successful conversion is greater than a first threshold, and a successful conversion is defined when the conversion margin is greater than a second threshold. In some embodiments, the processor is configured to adjust the voltage such that the probability of a successful conversion is greater than the first threshold. In some embodiments, the processor is configured to adjust the voltage such that the probability of a successful conversion is greater than the first threshold. In some embodiments, the comparator and processor are provided in an integrated circuit package, and the processor is a microprocessor in the integrated circuit package, on-chip integrated logic circuitry, or an analog correction loop.

[0032] In some embodiments, the processor is configured to determine the probability that the conversion margin is greater than a first threshold and to terminate the adjustment when the current is higher than a minimum current value and the probability is just below or approximately equal to a second threshold. In some embodiments, the processor is configured to adjust the current and determine the probability that the conversion margin is greater than the first threshold. When the current is higher than the minimum current value and the probability is higher than the second threshold, the processor adjusts the current. In some embodiments, the processor is configured to adjust the voltage when the voltage is higher than a minimum voltage value and the probability is higher than the second threshold. In some embodiments, the second threshold is a percentage higher than 90%.

[0033] The various embodiments disclosed herein relate to a method. The method includes sampling an input voltage using a CAPDAC circuit to obtain a sampled voltage. The method further includes determining the state of a plurality of bits corresponding to the sampled voltage using a comparator coupled to a set of memory circuits. The comparator has a current parameter or voltage parameter adjusted based on a conversion margin. The adjustment of the current parameter or voltage parameter affects the speed at which the state of the bits is determined. The method further includes storing the bits in the set of memory circuits.

[0034] In some embodiments, the conversion margin is related to a delay value determined in response to a sampling clock and at least one enable signal of a memory circuit coupled to the comparator. In some embodiments, adjustment is made in response to the probability that the conversion margin is higher than a first threshold being higher than a percentage threshold.

[0035] A. Computing and Network Environment

[0036] Before discussing specific embodiments of this solution, it may be helpful to describe aspects of the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. References Figure 1A This describes an embodiment of a network environment. In a brief overview, the network environment includes a wireless communication system comprising one or more access points (APs) 106, one or more wireless communication devices 102, and network hardware components 192. The wireless communication devices 102 may include, for example, laptop computers, tablet computers, personal computers, and / or cellular telephone devices. Reference Figure 1B and 1CMore detailed descriptions are provided for embodiments of each wireless communication device 102 and / or AP or network device 106. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. Network device 106 or AP may be operatively coupled to network hardware 192 via a local area network (LAN) connection. Network hardware 192, which may include routers, gateways, switches, bridges, modems, system controllers, devices, etc., may provide LAN connectivity for the communication system. Each of network device 106 or AP may have an associated antenna or antenna array for communicating with wireless communication devices in its area. Wireless communication device 102 may register with a specific network device 106 or AP to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via an assigned channel and communication protocol. Some of the wireless communication devices 102 may be mobile or relatively static relative to network device 106 or AP.

[0037] In some embodiments, network device 106 or AP includes means or modules (comprising a combination of hardware and software) that allow wireless communication device 102 to connect to a wired network using Wi-Fi or other standards. Network device 106 or AP may sometimes be referred to as a wireless access point (WAP). Network device 106 or AP can be implemented (e.g., configured, designed, and / or built) for operation in a wireless local area network (WLAN). In some embodiments, network device 106 or AP can be connected as a standalone device to a router (e.g., via a wired network). In other embodiments, network device 106 or AP can be a component of a router. Network device 106 or AP can provide network access to multiple devices. Network device 106 or AP can, for example, connect to a wired Ethernet connection and provide wireless connectivity using a radio frequency link so that other devices 102 can utilize the wired connection. Network device 106 or AP can be implemented to support standards for transmitting and receiving data using one or more radio frequencies. These standards and the frequencies they use may be defined by IEEE (e.g., the IEEE 802.11 standard). Network device 106 or AP may be configured and / or used to support public Internet hotspots and / or to extend the Wi-Fi signal range of a network.

[0038] In some embodiments, access point 106 may be used (e.g., at home or in a building) for wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol and / or variations thereof). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. This wireless communication device 102 and / or access point 106 may operate according to various aspects of this disclosure as presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes such as servers) via one or more access points 106.

[0039] The network connection may include any type and / or form of network, and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may be any such network topology known to those skilled in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0040] The communication device 102 and access point 106 can be deployed as any type and form of computing device and / or executed on any type and form of computing device, such as a computer, network device or apparatus capable of communicating and performing the operations described herein on any type and form of network. Figure 1B and 1C A block diagram depicting a computing device 100 for implementing embodiments of wireless communication device 102 or network device 106. (As shown in...) Figure 1B and 1C As shown, each computing device 100 includes a processor 121 (e.g., a central processing unit) and a main memory unit 122. As illustrated in... Figure 1B As shown, the computing device 100 may include a storage device 128, a mounting device 116, a network interface 118, an I / O controller 123, display devices 124a to 124n, a keyboard 126, and a pointing device 127, such as a mouse. The storage device 128 may include an operating system and / or software. (As shown in...) Figure 1C As shown, each computing device 100 may also include additional optional elements that communicate with the central processing unit 121, such as memory port 103, bridge 170, one or more input / output devices 130a to 130n, and cache memory 140.

[0041] Central processing unit 121 is any logic circuit system that responds to and processes instructions fetched from main memory unit 122. In many embodiments, central processing unit 121 is provided by a microprocessor unit, such as a microprocessor unit manufactured by Intel Corporation of Santa Clara, California; a microprocessor unit manufactured by International Business Machines of White Plains, New York; or a microprocessor unit manufactured by Advanced Micro Devices of Sunnyvale, California. Computing device 100 may be based on any of these processors, or any other processor capable of operating as described herein.

[0042] Main memory unit 122 may be one or more memory chips capable of storing data and allowing microprocessor 121 to directly access any memory location, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash, NOR flash, and solid-state drive (SSD). Main memory 122 may be based on any of the memory chips described above, or any other available memory chip capable of operating as described herein. Figure 1B In the embodiment shown, the processor 121 communicates with the main memory 122 via the system bus 150 (described in more detail below). Figure 1C An embodiment of a computing device 100 in which the processor communicates directly with the main memory 122 via memory port 103 is depicted. For example, in Figure 1C In this context, the main memory 122 can be DRDRAM.

[0043] Figure 1C The depicted embodiment shows the main processor 121 communicating directly with the cache memory 140 via a secondary bus (sometimes referred to as a back-end bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using a system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1CIn the embodiments shown, processor 121 communicates with various I / O devices 130 via a local system bus 150. Various buses can be used to connect central processing unit 121 to any of the I / O devices 130, such as VESA VL bus, ISA bus, EISA bus, Micro Channel Architecture (MCA) bus, PCI bus, PCI-X bus, PCI-High Speed ​​bus, or NuBus. In embodiments where the I / O device is a video display 124, processor 121 may communicate with display 124 using an Advanced Graphics Port (AGP). Figure 1C An embodiment of computer 100 is depicted, wherein the main processor 121 can communicate directly with I / O device 130b, for example, via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technologies. Figure 1C An embodiment in which a hybrid local bus and direct communication is also depicted: the processor 121 communicates with I / O device 130a using the local interconnect bus, while simultaneously communicating directly with I / O device 130b.

[0044] Various I / O devices 130a to 130n may be present in the computing device 100. Input devices include keyboards, mice, trackpads, trackballs, microphones, dial pads, touchpads, touchscreens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye-to-sublimation printers. The I / O devices can be controlled by the I / O controller 123, as shown in... Figure 1B As shown, the I / O controller can control one or more I / O devices, such as a keyboard 126 and a pointing device 127, such as a mouse or light pen. Additionally, the I / O devices can provide storage and / or mounting media 116 for the computing device 100. In yet another embodiment, the computing device 100 may provide a USB connection (not shown) to receive a handheld USB storage device, such as a USB flash drive series manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0045] Refer again Figure 1BThe computing device 100 may support any suitable installation device 116, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash memory drive, tape drive of various formats, USB device, hard disk drive, network interface, or any other device suitable for installing software and programs. The computing device 100 may further include storage devices for storing the operating system and other related software, as well as for storing application software programs (e.g., any program or software 120 used for implementing (e.g., configuring and / or designing for) the systems and methods described herein), such as one or more hard disk drives or a redundant array of independent disks. Optionally, any of the installation devices 116 may also be used as storage devices. Additionally, the operating system and software may run from a bootable medium.

[0046] Furthermore, the computing device 100 may include a network interface 118 to interface with a network via various connections, including (but not limited to) standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), wireless connections, or any or a combination of the foregoing. Connections can be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and Direct Asynchronous Connection). In one embodiment, computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). Network interface 118 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other device suitable for interfacing computing device 100 to any type of network capable of communicating and performing the operations described herein.

[0047] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a to 124n. Therefore, any of the I / O devices 130a to 130n and / or I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide computing device 100 with connectivity to and use of display devices 124a to 124n. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to interface with, communicate with, connect to, or otherwise use display devices 124a to 124n. In one embodiment, a video adapter may include multiple connectors to interface with display devices 124a to 124n. In other embodiments, computing device 100 may include multiple video adapters, each connected to display devices 124a to 124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a to 124n. In another embodiment, I / O device 130 may be a bridge between system bus 150 and external communication bus (e.g., USB bus, Apple Desktop Bus, RS-232 serial connection, SCSI bus, FireWire bus, FireWire 800 bus, Ethernet bus, AppleTalk bus, Gigabit Ethernet bus, Asynchronous Transfer Mode bus, Fibre Channel bus, Fibre Bus, Serial Attached Small Computer System Interface Bus, USB connection, or HDMI bus).

[0048] Figure 1B and 1CThe computing device 100 of the type described herein can operate under the control of an operating system that controls task scheduling and access to system resources. The computing device 100 can run any operating system, such as any version of Microsoft Windows, different versions of Unix and Linux, any version of MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android, manufactured by Google Inc.; Windows 7, 8, and 10, manufactured by Microsoft Corporation of Redmond, Washington; macOS, manufactured by Apple Computer of Cupertino, California; WebOS, manufactured by Research In Motion (RIM); OS / 2, manufactured by International Business Machines of Armonk, New York; and Linux, a free operating system distributed by Caldera Corp. of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0049] Computer system 100 may be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunications, or media device capable of communication. In some embodiments, computing device 100 may have a different processor, operating system, and input device consistent with the device described herein. For example, in one embodiment, computing device 100 is a smartphone, mobile device, tablet computer, or personal digital assistant. Furthermore, computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0050] The aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein.

[0051] B.SAR ADC

[0052] The various embodiments disclosed herein relate to SAR ADCs, such as high-speed SAR ADCs or ultra-high-speed SAR ADCs. In some embodiments, the SAR ADC is relatively unaffected by PVT variations and is configured for 200G / 100G networking applications. In some embodiments, systems and methods described herein are for use in network integrated circuits (ICs) of, for example, 225Gbps PAM4 optical transceivers or other transceivers. In some embodiments, the systems and methods described herein provide speed advantages without significant power / area losses. SAR ADCs can be used with reference to the above. Figure 1A The SAR ADC can operate according to the principles described herein and uses the conversion structures and operations described in U.S. Patent No. 10,903,846, which has been assigned to the assignee of this application and whose entire contents are incorporated herein by reference. The SAR ADC can operate according to the principles described herein and uses the conversion structures and operations described in U.S. Patent Application No. 17 / 699,678 (106861 6097), filed concurrently with this application by Singh et al., and U.S. Patent Application No. 17 / 694225, filed March 14, 2022, both of which have been assigned to the assignee of this application and whose entire contents are incorporated herein by reference.

[0053] Figure 2 This is a block diagram depicting a communication device 200 according to one or more embodiments. In some embodiments, the communication device 200 is a system, apparatus, or device for network communication. For example, the communication device 200 is implemented as part of a network device 106, node or network hardware 192, device 102, or a network apparatus serving a network communicating with device 102. In some embodiments, device 200 includes a transmitter 210, a receiver 220, and a processor 280. These components may operate together to communicate with another communication device via a network cable (e.g., Ethernet, USB, FireWire, etc.) and / or via a wireless medium (e.g., Wi-Fi, Bluetooth, 60GHz link, cellular network, etc.). In some embodiments, the communication device 200 includes a... Figure 2 More, fewer, or different components are shown in the document.

[0054] Transmitter 210 is a circuit or component that receives transmission data TX Data from processor 280 and generates output signals Out+ and Out-. Transmitter 210 can receive N-bit digital data TX Data from processor 280 and generate output signals Out+ and Out- having a voltage or current corresponding to the digital data TX Data. Output signals Out+ and Out- can be differential signals. In some embodiments, transmitter 210 can generate single-ended signals or signals in different representations for output signals Out+ and Out-. In some embodiments, transmitter 210 transmits output signals Out+ and Out- via a network cable. In some embodiments, transmitter 210 provides output signals Out+ and Out- to a wireless transmitter (not shown), which can up-convert output signals Out+ and Out- to generate a radio frequency wireless transmission signal and transmit the wireless transmission signal through a wireless medium.

[0055] Receiver 220 is a circuit or component that receives input signals In+ and In- and generates received data RX data. In some embodiments, receiver 220 receives input signals In+ and In- via a network cable. Input signals In+ and In- may be differential signals. In some embodiments, receiver 220 may receive single-ended signals or signals in different representations of input signals In+ and In-. In some embodiments, receiver 220 receives input signals In+ and In- from a wireless receiver (not shown) that can receive wireless signals via a wireless medium and down-converts the wireless signals to generate input signals In+ and In- at a baseband frequency. In some embodiments, receiver 220 receives input signals In+ and In- and generates N-bit digital data RX data corresponding to the voltage or current of input signals In+ and In-. Receiver 220 may provide the digital data RX data to processor 280. In some embodiments, receiver 220 includes a SAR ADC 225 that converts input signals In+ and In- into N-bit digital data RX data.

[0056] Processor 280 is a circuit or component capable of performing logical calculations. In some embodiments, processor 280 is implemented as a field-programmable gate array, an application-specific integrated circuit (ASIC), or a state machine. Processor 280 is electrically coupled to transmitter 210 and receiver 220 via conductive traces or a bus connection. In this configuration, processor 280 can receive data RX from receiver 220 and perform logical calculations or execute various applications based on the state of the received data RX. Processor 280 can also generate data TXData and provide data TXData to transmitter 210.

[0057] refer to Figure 3A The SAR ADC 300 can be implemented as Figure 2The SAR ADC 225 is described in Figure 3. In some embodiments, the SAR ADC 300 includes a sampling capacitor and a digital-to-analog (CAP DAC) circuit 310, a comparator circuit 330, a transition state circuit 350, a first set of storage circuits 360A, a second set of storage circuits 360B, an enable circuit 370, a clock path circuit 380, a controller 382, ​​and a retimer circuit 400. These components can operate together to receive input signals In+, In- and perform successive approximation analog-to-digital conversion to produce L-bit data RX data corresponding to the voltages of the input signals In+, In-, where L is any integer. In some embodiments, the SAR ADC 300 includes more, fewer, or different components than those shown in Figure 3. Although in Figure 3A In the diagram, the CAPDAC circuit 310, comparator circuit 330, and memory circuits 360A and 360B are shown to generate and process differential signals, but some or all of these components can generate and process single-ended signals. Additional comparator and memory circuitry can be provided in a cascaded, pipelined, or serial manner (e.g., a dual comparator design for the SAR ADC 300). The SAR ADC 300 is an IC device integrated on a single substrate, provided in a multi-chip package, or in some embodiments, part of another IC device.

[0058] In some embodiments, the CAPDAC circuit 310 is a circuit or component that samples input signals In+ and In- and generates DAC output signals DAC Out+ and DAC Out-. In one embodiment, the CAPDAC circuit 310 is embodied as a capacitive DAC circuit. In some embodiments, the CAPDAC circuit 310 includes inputs 311 and 312 configured to receive input signals In+ and In-, feedback ports 313, 314, 315, and 316 configured to receive L-bit data RX, and output ports 331 and 332 configured to output DAC output signals DAC Out+ and DAC Out-. In some embodiments, N number of feedback ports 315 and 316 are coupled to N number of output ports of a first set of storage circuits 360A, and M number of feedback ports 314 and 314 are coupled to M number of output ports of a second set of storage circuits 360B, where M and N are any integers. In some instances, N can be 4, 6, 8, 9, 10, 16, or 32, and M can be 4, 6, 8, 9, 10, 16, or 31. In some embodiments, N and M can be equal and can be equal to L. In some embodiments, the first output port 331 of the CAPDAC circuit 310 is coupled to the first input port of the comparator circuit 330. The second output port 333 of the CAPDAC circuit 310 is coupled to the second input port of the comparator circuit 330. In some embodiments, the CAPDAC circuit 310 receives input signals In+ and In- at inputs 311 and 312 and receives L-bit data RX at feedback ports 313, 314, 315, and 316, and samples the input signals In+ and In-. The CAPDAC circuit 310 can perform DAC based on the L-bit data RX to generate DAC output signals DACOut+ and DACOut- at output ports 331 and 332. The CAPDAC circuit 310 can provide the DAC output signals DACOut+ and DACOut- to the comparator circuit 330. In one method, for the Xth bit of L-bit data RX, the DAC output signals DACOut+ and DACOut- indicate the voltages (e.g., Vin+ and Vin-) of the input signals In+ and In-, where the voltages correspond to LX MSBs of data RX. In another method, the CAPDAC circuit 310 generates the DAC output signals DACOut+ and DACOut- according to the following equation:

[0059]

[0060] Where V DAC Out + represents the voltage of the DAC Out+ signal, V. DAC Out- is the voltage of the DAC Out- signal, and V ref That is the reference voltage.

[0061] In some embodiments, comparator circuit 330 is a circuit or component that receives DAC output signals DACOut+ and DACOut- and determines the state of the corresponding bit of data RX based on the DAC output signals DACOut+ and DACOut-. In some embodiments, comparator circuit 330 includes a first output port 361 coupled to a first input port of a first group of storage circuits 360A via inverters 336 and 1132, a second output port 362 coupled to an input port of a second group of storage circuits 360B via inverters 338 and 1134, and a clock input 339 coupled to conductor 373.

[0062] Conductor 373 is coupled to the output of flip-flop 344 (e.g., a D flip-flop) of clock path circuit 380. Clock path 340 includes conductor 373, inverters 336 and 338, and clock path circuit 380 including logic device 342 and flip-flop 344. Data path 302 includes a first set of storage circuits 360A and a second set of storage circuits 360B, and extends between feedback ports 313, 314, 315, and 316 of CAPDAC circuit 310 and output ports 361 and 362 of comparator circuit 330. In some embodiments, the first output port 361 of comparator circuit 330 may be directly coupled to the first input port of storage circuit 360A, and the second output port 362 of comparator circuit 330 may be directly coupled to the input port of second storage circuit 360b.

[0063] Comparator circuit 330 can be enabled or disabled based on the clock signal CLK_SAR at clock input 339 from clock path circuit 380 on conductor 373. For example, comparator circuit 330 is enabled in response to the rising edge of clock signal CLK_SAR or logic state '1', and disabled in response to the falling edge of clock signal CLK_SAR or logic state '0'. When comparator circuit 330 is enabled, comparator circuit 330 can determine the bit state based on DAC output signals DACOut+ and DACOut-, and generate comparator outputs CompOut1+ and CompOut1- at output ports 361 and 362 indicating the determined bit state. For example, when comparator circuit 330 is enabled, in response to the voltage difference between DAC output signals DACOut+ and CompOut1- being higher than 0V or a reference voltage, comparator circuit 330 can generate comparator output CompOut1+ with logic state '1' and comparator output CompOut1- with logic state '0'. For example, when comparator circuit 330 is enabled, in response to the voltage difference between the DAC output signals DACOut+ and DACOut- being lower than 0V or the reference voltage, comparator circuit 330 can generate comparator output CompOut1+ with logic state '0' and comparator output CompOut1- with logic state '1'. When comparator circuit 330 is disabled, comparator circuit 330 can reset comparator outputs CompOut1+ and CompOut1- to logic state '0'. Comparator circuit 330 can provide comparator outputs CompOut1+ and CompOut1- to the first set of storage circuits 360A and the second set of storage circuits 360B. Comparator outputs CompOut1+ and CompOut1- can be differential signals.

[0064] refer to Figure 3B In some embodiments, the first set of storage circuits 360A is a group of components that stores N bits (e.g., 2, 4, 6, 8, 9, 16, 32 bits, etc.) of data. In one embodiment, the first set of storage circuits 360A is embodied as N number of flip-flops or latches. In some embodiments, the set of storage circuits 360A is a ratio set-reset (SR) latch. In some embodiments, the first input port of each storage circuit 360A, except for storage circuit 1102, is connected via inverters 336 and 1132 ( Figure 3B ) Coupled to the first output port 361 of comparator circuit 330 Figure 3AIn some embodiments, the enable port of each storage circuit 360A is coupled to the corresponding enable output port of the enable circuit 370, and the output port of each storage circuit 360A is coupled to the corresponding feedback ports 315 and 316 of the CAPDAC circuit 310. In some embodiments, the first input port of the storage circuit 1102 (e.g., corresponding to the most significant bit (MSB)) in a group of storage circuits 360A is coupled to the first output port 361 of the comparator circuit via an inverter 336. In this configuration, each storage circuit 360A can be enabled or disabled according to the corresponding bit of the enable signal EN on the enable bus 371. For example, in response to the enable signal EN being 00001 (enable zero signal EN0), the first storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 00010, the second storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 00100, the third storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 01000, the fourth storage circuit of storage circuit 360A is enabled; and in response to the enable signal EN being 10000, the fifth storage circuit of storage circuit 360A is enabled. In some embodiments, the enabling scheme follows the scheme described above for the remaining storage circuits 360A and 360B. For example, in response to the enable signal EN being 00000, all first group storage circuits 360A are disabled. When storage circuit 360A is enabled, storage circuit 360A can update the corresponding bits of data RX according to the comparator outputs CompOut1+ and CompOut1-. For example, if storage circuit 360A is enabled, then in response to comparator output CompOut1+ having logic state '1' and comparator output CompOut1- having logic state '0', storage circuit 360A can update the corresponding bit of data RX to '1'. Alternatively, if storage circuit 360A is enabled, then in response to comparator output CompOut1 having logic state '1' and comparator output CompOut1+ having logic state '0', storage circuit 360A can update the corresponding bit of data RX to '0'. If storage circuit 360A is disabled, then storage circuit can maintain or preserve the corresponding bit of data RX, regardless of the comparator outputs CompOut1+ and CompOut1- at the input port.

[0065] In some embodiments, the second set of storage circuits 360B is a set of components storing M bits of data. In one embodiment, the second set of storage circuits 360B is embodied as M number of flip-flops or latches. In some embodiments, the set of storage circuits 360B is a ratio set-reset (SR) latch. The ratio SR latch is an SR latch configured to drive the outputs of feedback ports 313, 314, 315, and 316 according to its bit position. In some embodiments, the first input port of each storage circuit 360B, except for storage circuit 1104, is coupled to the first output port 362 of comparator circuit 330 via inverters 338 and 1134. Figure 3A In some embodiments, the enable port of each storage circuit 360B is coupled to the corresponding enable output port of the enable circuit 370 via bus 371. In some embodiments, storage circuit 1104 in a group of storage circuits 360B ( Figure 3B (For example, the first input port corresponding to the most significant bit (MSB) is coupled to the first output port 362 of the comparator circuit 330 via an inverter 338. The output port of each storage circuit 360B is coupled to the corresponding feedback ports 313 and 314 of the CAPDAC circuit 310. In some embodiments, the operation of the storage circuit 360B is similar to that of the first group of storage circuits 360A, and the storage circuit 360B is enabled as described above using the enable signal EN on the bus 371. In some embodiments, the storage circuit 360A is used for the positive portion of the differential signal, and the storage circuit 360B is used for the negative portion of the differential signal.

[0066] By directly driving only a single memory element, memory circuit 1102, with a driver (e.g., inverter 336), and directly driving memory circuit 1104 with only a driver (e.g., inverter 338), the load on the comparator drivers (e.g., inverters 336 and 338) is reduced. This driving scheme also simplifies circuit layout. In some embodiments, the remaining memory circuits 360A to B are driven by different drivers (e.g., inverters 1132 and 1134, respectively). Data path 302 ( Figure 3A The delay in the memory circuit 360A-B can be reduced by directly driving the CAPDAC circuit 310 using an SR latch instead of using a ratio inverter between the memory circuits 360A-B and the CAPDAC circuit 310. (See reference) Figure 3B The enable 0 (EN0) signal on conductor 345 resets the CAPDAC circuit 310 by driving the gate of switch 1130 in the CAPDAC circuit 310. As described above, the memory circuits 360A and 360B are enabled by the enable signal EN provided on bus 371.

[0067] The retimer circuit 400 is a flip-flop or latch-based circuit that receives outputs from storage circuits 360A and 360B. In some embodiments, the retimer circuit 400 is aligned with the timing of downstream devices or components.

[0068] In some embodiments, the transition state circuit 350, the enable circuit 370, and the clock path circuit 380 cause the comparator circuit 330 and the storage circuits 360A and 360B to perform successive approximation analog-to-digital conversion. In some embodiments, the transition state circuit 350, the enable circuit 370, and the clock path circuit 380 are implemented as state machines and / or digital logic circuits. In some embodiments, the conductor 372 receives, for example, a T clock signal (T CLK) from a clock generator (not shown). The T clock signal is a sampling clock and has a period corresponding to a sampling cycle.

[0069] refer to Figure 3A Clock path circuit 380 provides a CLK_SAR signal on clock path 340 at conductor 373 for comparator circuit 330 and enable circuit 370 that provides an enable signal on bus 371. Flip-flop 344 is configured as a D-type flip-flop and includes an input coupled to conductor 345 that receives an enable 0 (EN0) signal from enable circuit 370. Flip-flop 344 includes a clock input coupled to logic device 342, which may be configured as a NAND gate. Logic device 342 receives signals from inverters 336 and 338. Inverters 336, 338, 332, and 334 are configured as comparator drivers. In some embodiments, the CLK_SAR signal is an internally generated clock signal provided by flip-flop 344, logic device 342, inverters 336 and 338, and comparator circuit 330. In some embodiments, the CLK_SAR signal is generated from comparator transitions and enable 0 (EN0) signals.

[0070] Enable circuit 370 is a timing circuit based on latches or flip-flops (e.g., D flip-flops) that provides an enable EN signal on bus 371 in response to a clock signal on conductor 373. Each flip-flop or latch in enable circuit 370 is driven at the clock input via a CLK_SAR signal on conductor 373 and provides one bit of enable EN signal on bus 371. An enable 0 (EN0) signal from enable circuit 370 is provided on conductor 345 for use by flip-flops 344 of transition state circuit 350 and clock path circuit 380. The enable 0 (EN0) signal, serving as an indicator of the start of the previous transition cycle, is used to force an early reset via conductor 345 (e.g., using transistor 1130). Figure 3BTransistor 303 can be used to reset the CAP DAC circuit 310 using the Enable 0 (EN0) signal or other reset signals. A delay can be provided in the reset path associated with the Enable 0 (EN0) signal to ensure that the previous conversion is not affected.

[0071] The transition state circuit 350 includes an inverter 352, a transition margin indicator circuit 354, and a transition state output 356. The inverter 352 receives a clock signal T at conductor 372 and provides a CLK_RT signal to the transition margin indicator circuit 354. The transition margin indicator circuit 354 receives an enable 0 (EN0) signal at conductor 345 and a CLK_SAR signal at conductor 372. The transition state circuit 350 provides a transition state signal indicating the transition operation at output 356. The transition margin indicator circuit 354 provides a signal at conductor 372 for determining the transition margin using the CLK_RT signal, the enable 0 (EN0) signal, and the CLK_SAR signal.

[0072] In some embodiments, controller 382 is an on-chip controller configured to determine conversion margin and adjust current and voltage parameters for faster operation or less noise. Advantageously, in some embodiments, controller 382 implements the systems and methods described herein for determining conversion margin and adjusting voltage and current parameters. Controller 382 may be a hardware implementation or software (e.g., firmware implementation) integrated with SAR ADC 300 (e.g., provided as part of conversion state circuitry 350 or other parts of SAR ADC 300). In some embodiments, the processor or controller 382 determines the probability of a successful conversion greater than a first threshold and defines a successful conversion when the conversion margin is greater than a second threshold. In some embodiments, controller 382 is a processor, microcontroller, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or logic device, or any other type and form of dedicated semiconductor logic or processing circuitry system capable of processing or supporting the operations described herein. In some embodiments, all or part of the operation associated with controller 382 is handled by processor 280 ( Figure 2 )implement.

[0073] refer to Figure 4The conversion margin indicator circuit 354 includes a D flip-flop 402, a variable time delay circuit 404, and a D flip-flop 406. In some embodiments, the variable time delay circuit 404 is a programmable or configurable circuit that provides a selectable delay. The D flip-flop 402 includes a reset input coupled to conductor 353 for receiving the CLK_RT signal from the inverter 352 (FIG. 3), and the D flip-flop 406 includes a clock input coupled to conductor 353 for receiving the CLK_RT signal from the inverter 352. The D input of the flip-flop 402 is coupled to conductor 345 to receive an enable 0 (EN0) signal. The output of the D flip-flop 402 is coupled to the input of the delay circuit 404. The clock input of the D flip-flop 402 is coupled to conductor 372 to receive the CLK_SAR signal. The D input of the flip-flop 406 is coupled to receive a conversion completion signal from the variable time delay circuit 404.

[0074] In some embodiments, the conversion completion signal indicates when the conversion of the analog signals at inputs 311 and 312 to their digital representations in storage circuits 360A to 360B is complete. In some embodiments, the conversion status signal indicates that the conversion has occurred before the end of the sampling cycle. In some embodiments, the conversion margin may be represented by or proportional to the difference between the leading edges of the conversion completion signal and the conversion status signal. In some embodiments, the conversion status circuit 350 provides the conversion status signal at output 356. The SAR ADC 300 (e.g., microcontroller 382) may apply adaptive feedback techniques using the conversion margin determined based on the status signal and the conversion completion signal or other parameters associated therewith. Adaptive feedback can advantageously compensate for noise from the comparator circuit 330 and process dependencies associated with the drivers of the comparator circuit 330 (e.g., inverters 336 and 338). In some embodiments, the conversion margin indicator circuit 354 is configured such that an approximation of the conversion margin using the conversion status signal can be derived.

[0075] refer to Figure 5 Waveform 502 is the CLK_RT signal at conductor 353. Waveform 504 is a conversion completion signal indicating that the conversion is complete, and is provided to the D input of flip-flop 406 by time delay circuit 404. Waveform 506 is the conversion status signal at output 356. Waveform 508 is a signal with a time delay of T. D1 The conversion completion signal is provided by the time delay circuit 404. Waveform 510 is the signal generated when the time period T... M Greater than time delay T D1 The transition status signal at position 356 is output at any time. Time period T M Proportional to the conversion margin. Waveform 512 has a time delay of T. D2 The conversion completion signal is provided by the time delay circuit 404. Waveform 514 is the signal generated when the time period T...M Less than time delay T D2 The transition status signal at output 356 is used. A destructive measurement of the transition status signal at output 356 is used to determine the time period T. M For example, changing the value T D This continues until the transition status signal at output 356 flips from 1 to 0, causing a time delay T. D The value corresponds to the time period T M (See waveform 514). Time delay T D Provided by the variable time delay circuit 404. Generally, the time period T... M Therefore, the conversion margin varies with the input of the SAR ADC 300, system noise, and metastable events.

[0076] In some embodiments, the SAR ADC 300 employs a collection time period T M Monitoring schemes that measure the value or other representation of the conversion margin. Values ​​are collected over time. In some embodiments, values ​​are collected as the time delay changes. The time period T can be calculated for various time delays. M The probability of being greater than a certain value. When the time period T... M Greater than time delay T D When, probability and time period T M The curve flattens out, thereby indicating the minimum conversion margin value at the said delay. The delay can be used as the minimum conversion margin value, which can be used to provide adaptive feedback for the SAR ADC 300, as described below.

[0077] refer to Figure 6 In some embodiments, comparator circuit 330 includes adjustable current source circuit 700. Current source circuit 700 includes transistor 702, current source 704, multiplexer 706, transistor 710 and transistor 712 as adjustable current sources configured as transistors 714, 716, 718 and 720 of comparator circuit 330. In some embodiments, transistor 712 is driven by a CLK_SAR signal. In some embodiments, transistors 714, 716, 718 and 720 are the first stage of comparator circuit 330, receiving signals at output ports 331 and 332 (FIG. 3), and may be part of a high-speed comparator. Transistor 710 is configured to provide I... max and I min Current I within the range bias Current I biasThe value is controlled by multiplexer 706, which selects either a ground signal or a signal from between transistor 702 and current source 704 based on a selection signal provided to its selection input. In some embodiments, the selection signal is provided by controller 382. Multiplexer 706 drives transistor 710 according to the selection. In some embodiments, for low speed angles (SS), the current source value is adjusted to I for high speeds. max In some embodiments, for the high-speed angle (FF), the current source value is adjusted to I for low speed. min Selecting the signal and time period T M Relatedly, a larger conversion margin indication should be provided by transistor 710 with a lower Ig. bias ,vice versa.

[0078] refer to Figure 7 The comparator circuit 330 includes an adjustable driver circuit 800. The adjustable driver circuit 800 includes a transistor 804, a multiplexer 806, a current source 820, transistors 814, 824, 826, 828, and 830. In some embodiments, the adjustable driver circuit 800 is an adjustable comparator driver for a high-speed comparator and can be used at outputs 361 and 362 (…). Figure 3A Provided at ) location. Current I biasi The value is controlled by multiplexer 806, which selects either a ground signal or a signal from the node between transistor 804 and current source 820 to drive the current I of transistors 824, 828, 826, and 830. biasi The selection signal at the selection input of the multiplexer 806 is used to adaptively tune the current I. biasi The selection signal is based on the conversion margin and can be provided by the controller 382 (FIG. 3). In some embodiments, the current I through transistor 814 is adjusted. biasi To change the current I without significantly affecting the speed biasi Selecting the signal and time period T M Relatedly, a larger conversion margin indication should be provided by transistor 814 with a lower Ig. biasi ,vice versa.

[0079] refer to Figure 8The comparator circuit 330 may include an adjustable driver circuit 900. The adjustable driver circuit 900 includes an input 902, transistors 904, 906, 908, 912, and 914, a multiplexer 916, transistors 920, 922, and 924, and an output 930. In some embodiments, the adjustable driver circuit 900 is configured as an adjustable comparator driver for a high-speed comparator and may be provided at outputs 361 and 362. The driver threshold voltage V... th The value is controlled by multiplexers 916 and 922, which select the voltage signal V respectively. DD Alternatively, a clock signal (e.g., CLK_SAR) can be used to drive transistors 914 and 924. The select signals at the select inputs of multiplexers 916 and 922 are used to adaptively tune the driver threshold voltage V. th The selection signal is based on the conversion margin and can be provided by the controller 382 (Figure 3). The selection signal is related to the time period T. M Relatedly, the larger conversion margin indication should be provided by transistors 914 and 924, which provide a lower threshold voltage V. th In some embodiments, the time period T M Used to set V DD A larger conversion margin indication should provide a lower voltage V. DD ,vice versa.

[0080] refer to Figure 9 The SAR ADC 300 can execute procedure 1000 to measure and convert state signals (e.g., waveform 506). Figure 5 The associated statistical data or value. Execution process 1000 estimates the transition state signal as 1 (e.g., with...). Figure 5 The probability P(CS) is the probability of a successful conversion (the opposite of waveform 510 in waveform 514). In some embodiments, the probability P(CS) can be determined by comparing a conversion margin to a certain value. This value can be a fixed value, a percentage of the sampling cycle, etc. The probability is the probability of a successful conversion, and in some embodiments, a successful conversion is defined when the conversion margin is greater than a threshold. The probability can be represented by curves 1106, 1108, and 1110 on an X-axis representing the conversion margin in time and a Y-axis representing the probability. Curves 1106, 1108, and 1110 are each for a specific time delay (100 picoseconds (ps), 200 ps, ​​300 ps). According to some embodiments, execution flow 1000 causes the SAR ADC 300 to be activated for a given delay T. DOperating at the intersection of the linear and flat portions of curves 1106, 1108, and 1110 provides a better trade-off between power, noise, and bit error rate (BER). Generally, the flat portions of curves 1106, 1108, and 1110 offer a conversion margin greater than the time delay T. D It begins at that time.

[0081] Process 1000 includes adjusting current I bias ( Figure 7 Operation 1002. If the current I bias Greater than I min Then, in operation 1004, the probability is estimated. If the probability is higher than a threshold (e.g., higher than 90% (e.g., 0.95)), then process 1000 returns to operation 1002. If the probability is lower than the threshold (e.g., higher than 90% (e.g., 0.95 or 1.0)), then process 1000 ends the adjustment in operation 1006. If the current I... bias ( Figure 7 Less than I min (Minimum value of the adjustable bias current of comparator circuit 330), then in operation 1010, the voltage threshold V is adjusted. th ( Figure 9 or current I biasi ( Figure 8 In some embodiments, the voltage threshold V is adjusted in operation 1010. th or current I biasi To increase speed. If the current I biasi Greater than I mini Or voltage threshold V th Greater than V min (This depends on the implementation plan, see [link]) Figure 8 and 9 If the probability is higher than a threshold (e.g., above 90% (e.g., 0.95 or 1.0)), then process 1000 returns to operation 1008. If the probability is just below or approximately equal to the threshold (e.g., above 90% (e.g., 0.95 or 1.0)), then process 1000 ends the adjustment in operation 1016. If the current I... biasi Less than I mini (Minimum of the adjustable bias current of the comparator driver) or voltage threshold V th Less than V min (For example, the maximum NMOS adjustable code of the comparator driver), then in operation 1020, the voltage signal V is adjusted (e.g., reduced). DD If the voltage signal V DD Greater than V DDminIf the minimum supply voltage of the SAR ADC 300 is given, then the probability is estimated in operation 1022. If the probability is higher than a threshold (e.g., higher than 90% (e.g., 0.95 or 1.0)), then process 1000 returns to operation 1020. If the probability is just below or approximately equal to the threshold (e.g., higher than 90% (e.g., 0.95 or 1.0)), then process 1000 ends the adjustment in operation 1026. Process 1000 can be performed together or sequentially for the threshold voltage V. th and current I biasi Both operations are 1010, 1012, and 1016. In some embodiments, the order of branches of operations 1002, 1004, and 1006, branches of operations 1010, 1012, and 1016, and branches of operations 1020, 1022, and 1026 can be switched.

[0082] Process 1000 can be executed in controller 382. Process 1000 may include fewer operations, such as operations 1002, 1004, and 1006, or operations 1010, 1012, and 1016, or operations 1020, 1022, and 1026. Process 1000 may be combined with other operations. Process 1000 may be implemented in hardware implementations or software (e.g., firmware implementations) (e.g., provided as part of transition state circuitry 350 or other parts of SAR ADC 300). In some embodiments, controller 382 is any type and form of dedicated semiconductor logic or processing circuitry system capable of processing or supporting process 1000. Process 1000 may include software instructions provided on a non-transitory medium and can be implemented by executing the instructions on controller 382. Process 1000 may be executed periodically during chip initialization, power-on, and during operation. Conversion margins may be periodically calculated to determine whether adjustments are needed during SAR ADC 300 operation (e.g., heating). Process 1000 can be executed periodically over millisecond time periods (e.g., every 4 milliseconds at startup and every 100 to 400 milliseconds during operation). In some embodiments, historical values ​​of the conversion margin are determined and stored. Larger differences between values ​​can be used to initiate process 1000. In some embodiments, the conversion margin indicates the amount of unused time prior to a bit error occurring within a sampling cycle.

[0083] It should be noted that certain paragraphs of this disclosure may be used in conjunction with device or operational references, such as the terms "first" and "second," for the purpose of identifying or distinguishing one another or for other purposes. These terms are not intended to relate entities (e.g., first device and second device) temporally or sequentially, although in some cases these entities may imply such a relationship. These terms also do not limit the number of possible entities operable within the system or environment. It should be understood that the system described above may provide any or more of the components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. Furthermore, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture. In addition, some components may be coupled with intermediary components provided between them.

[0084] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the particular embodiments, methods, and examples described herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An electronic device comprising: Digital-to-analog converter (DAC) circuit; A comparator circuit, which is coupled to the DAC circuit; A set of storage circuits coupled to the comparator circuit and the DAC circuit, the set of storage circuits being configured to store a plurality of bits corresponding to the input voltage; as well as A control circuit coupled to the comparator circuit is configured to adjust a bias current, a threshold voltage, or a supply voltage used in the comparator circuit in response to a conversion margin, wherein the adjustment of the bias current, the threshold voltage, or the supply voltage is in response to a determined probability of successful conversion, wherein the control circuit is configured to terminate the adjustment when the current is higher than a minimum current value and the probability is lower than or equal to a first threshold, when the threshold voltage is higher than a minimum threshold voltage and the probability is lower than or equal to the first threshold, or when the supply voltage is higher than a minimum supply voltage and the probability is lower than or equal to the first threshold.

2. The electronic device of claim 1, wherein the conversion margin indicates the amount of unused time prior to a bit error occurring within the sampling cycle.

3. The electronic device of claim 1, wherein the control circuitry is configured to determine the conversion margin and periodically adjust the bias current, the threshold voltage, or the supply voltage.

4. The electronic device of claim 1, wherein the control circuitry is configured to determine a conversion margin and adjust the bias current, the threshold voltage, or the supply voltage when the device is powered on.

5. The electronic device of claim 1, wherein the control circuitry is configured to adjust the bias current and the threshold voltage.

6. The electronic device of claim 1, wherein the control circuitry is configured to adjust the bias current in response to the conversion margin, and the bias current is used for a current mirror or driver in the comparator circuitry.

7. The electronic device of claim 1, wherein the control circuitry is configured to adjust the threshold voltage in response to the conversion margin, and the threshold voltage is used by a driver in the comparator circuitry.

8. The electronic device of claim 1, wherein the control circuitry is configured to adjust the supply voltage in response to the conversion margin.

9. The electronic device of claim 1, further comprising a transition state circuit configured to provide a transition state signal, wherein the transition state circuit includes a variable delay circuit, wherein the control circuit adjusts the variable delay circuit to determine the transition margin.

10. An electronic device comprising: Receiver, comprising: Analog-to-digital converter (ADC) circuit, which includes: Comparator; and A processor configured to determine a conversion margin and use the conversion margin to adjust the current or voltage used in the comparator, wherein the current or voltage is adjusted in response to a determined probability of a successful conversion, wherein a successful conversion is defined when the conversion margin is greater than a second threshold, wherein the processor is configured to adjust the current when the current is above a minimum current value and the probability is above a first threshold, or wherein the processor is configured to adjust the voltage when the voltage is above a minimum voltage value and the probability is above the first threshold.

11. The electronic device of claim 10, wherein the processor provides one or more selection signals to the multiplexer in the comparator to adjust the current or the voltage.

12. The electronic device of claim 10, wherein the processor is configured to adjust the current when the determined probability of the successful conversion is greater than the first threshold.

13. The electronic device of claim 10, wherein the processor is configured to adjust the voltage when the determined probability of the successful conversion is greater than the first threshold.

14. The electronic device of claim 10, wherein the processor is configured to adjust the voltage when the determined probability of the successful conversion is greater than the first threshold, wherein the voltage is the supply voltage of the driver in the comparator.

15. The electronic device of claim 10, wherein the comparator and the processor are provided in an integrated circuit package, and the processor is a microprocessor in the integrated circuit package, on-chip integrated logic circuitry, or analog correction loop.

16. An electronic device comprising: Receiver, comprising: Analog-to-digital converter (ADC) circuit, which includes: Comparator; and A processor configured to determine a conversion margin and use the conversion margin to adjust the current or voltage used in the comparator, wherein the processor is configured to determine a probability of successful conversion and to terminate the adjustment when the current is above a minimum current value and the probability is below or equal to a first threshold.

17. The electronic device of claim 16, wherein a successful conversion is defined when the conversion margin is greater than a second threshold, and the processor is configured to adjust the current when the current is higher than the minimum current value and the probability is higher than the first threshold, or the processor is configured to adjust the voltage when the voltage is higher than the minimum voltage value and the probability is higher than the first threshold.

18. The electronic device of claim 16, wherein a successful conversion is defined when the conversion margin is greater than a second threshold.

19. A method performed by an electronic device, comprising: The input voltage is sampled by a comparator coupled to the digital-to-analog converter; The states of multiple bits corresponding to the input voltage are determined by comparators coupled to a set of storage circuits, wherein the comparators have current or voltage parameters adjusted based on a transition margin, wherein the adjustment of the current or voltage parameters affects the speed at which the states of the bits are determined, wherein the current or voltage parameters are adjusted in response to a determined probability of a successful transition, wherein a successful transition is defined when the transition margin is greater than a second threshold, wherein the current parameter is adjusted when the current parameter is higher than a minimum current value and the probability is higher than a first threshold, or wherein the voltage parameter is adjusted when the voltage parameter is higher than a minimum voltage value and the probability is higher than the first threshold; and The bit is stored in the set of the memory circuits.

20. The method of claim 19, wherein the conversion margin is related to a delay value determined in response to a sampling clock and at least one enable signal for the storage circuitry coupled to the comparator.

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