Reduced complexity maximum likelihood sequence detector adapted for m-ary signaling

Abstract

Reduced complexity maximum likelihood sequence detectors (rMLSDs) for detecting multi-bit symbols, such as symbols found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points, are disclosed. One illustrative digital communication receiver includes an initial equalizer that derives an initial sequence of symbol decisions from a filtered received signal, each symbol decision in the initial sequence having a second possible symbol decision, and an rMLSD that derives a final sequence of symbol decisions by evaluating a state metric for only each symbol decision in the initial sequence and its second possible symbol decision.

Description

Technical Field

[0001] This disclosure relates to digital communication receivers, and more specifically, to equalizers suitable for use with high-rate signaling and large signal constellations. Background Technology

[0002] With the continued demand for ever-lower latency and ever-increasing transmission rates, data communication standards are specifying increases in the number of data channels, the channel symbol rate in each channel, and the number of bits per channel symbol. Channel symbols are attenuated and dispersed during propagation, resulting in inter-symbol interference (ISI) at the receiver. When attempting to detect channel symbols, the receiver must cope with this ISI in addition to the channel noise that contaminates the received signal.

[0003] Due to their relatively low complexity, linear equalizers and decision feedback equalizers (DFEs) are generally preferred for facilitating channel symbol detection without excessive noise enhancement. However, as data rates approach channel capacity, these equalizers may fail to provide sufficiently low bit error rates. When configured to detect multi-bit symbols, the maximum likelihood sequence detector (MLSD) employs a symbol detection strategy that is optimal from a bit error rate perspective, but is generally prohibited from a complexity and power consumption standpoint. Summary of the Invention

[0004] Therefore, this paper discloses a reduced-complexity maximum likelihood sequence detector (rMLSD) for detecting multi-bit symbols, such as symbols found in pulse amplitude modulation (PAM), phase shift keying (PSK), and QAM (quadrature amplitude modulation) signal constellations with more than two constellation points.

[0005] An illustrative digital communication receiver includes: an initial equalizer that derives an initial sequence of symbol decisions from a filtered received signal, each symbol decision in the initial sequence having a second possible symbol decision; and an rMLSD that derives a final sequence of symbol decisions by evaluating a state metric used only for each symbol decision in the initial sequence and its second possible symbol decision.

[0006] An illustrative receiving method includes: deriving an initial sequence of symbol decisions from a filtered received signal, each symbol decision in the initial sequence having a second possible symbol decision; and deriving a final sequence of symbol decisions using rMLSD by evaluating a state metric used only for each symbol decision in the initial sequence and its second possible symbol decision.

[0007] An illustrative semiconductor intellectual property core for generating a circuit system for implementing the reception and methods described above.

[0008] Each of the aforementioned receiver, method, and core can be embodied individually or in combination, and can be combined with any one or more of the following optional features: 1. The initial equalizer is a decision feedback equalizer (DFE), comprising: an adder that combines a feedback signal with the filtered received signal to generate an equalized signal; a limiter that derives the initial sequence of symbol decisions from the equalized signal; and a feedback filter that derives the feedback signal from the initial sequence of symbol decisions. 2. The limiter further derives a second possible symbol decision for each symbol decision in the initial sequence. 3. The initial equalizer is a DFE, comprising: a pre-compensation unit that derives a provisional symbol decision from the filtered received signal; and a multiplexer that selects from the provisional symbol decisions based on previous symbol decisions in the initial sequence. 4. An error calculation circuit that combines the filtered received signal with the initial sequence of symbol decisions to determine an initial equalization error. 5. A contention-based decision circuit that determines the second possible symbol decision based on the initial sequence of equalization errors and symbol decisions. 6. The rMLSD includes: a branch metric calculation circuit system that combines the initial equalization error or the filtered received signal with symbol decisions from the initial sequence and with the associated second possible symbol decisions to determine a corresponding equalization error, and adds each equalization error to each previous state metric to obtain a branch metric; and a comparator that determines the minimum branch metric for each symbol decision and each second possible symbol decision in the initial sequence. 7. The rMLSD includes a copy-shift register pair that, in response to the output of the comparator, assembles the most probable symbol decision sequence ending with the symbol decision and the second possible symbol decision. 8. The rMLSD further includes a state metric comparator that selects the most probable symbol decision sequence, using symbol decisions preceding the sequence as symbol decisions for the final sequence. Attached Figure Description

[0009] Figure 1 An illustrative network is shown.

[0010] Figure 2 This is a block diagram illustrating a switch.

[0011] Figure 3 This is an illustrative PAM4 eye diagram.

[0012] Figure 4 This is a block diagram of a single-tap DFE.

[0013] Figure 5This is a schematic diagram of a Viterbi trellis level PAM4.

[0014] Figure 6 This is an illustrative diagram of the rMLSD mesh level.

[0015] Figure 7 This is a block diagram of an illustrative rMSLD with an initial DFE level.

[0016] Figure 8 It is shown Figure 7 A schematic diagram showing additional details of the receiver.

[0017] Figures 9A-9B This is a graph of BER versus channel SNR. Detailed Implementation

[0018] Although specific embodiments are given in the accompanying drawings and the following description, please remember that they do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications that fall within the scope of the appended claims.

[0019] In terms of context, Figure 1 An illustrative network, such as that found in a data processing center, is shown, in which multiple server racks 102-106 each contain multiple servers 110 and at least one "top-of-rack" (TOR) switch 112. The TOR switch 112 is connected to an aggregator switch 114 for interconnection and connection to a local area network and the Internet. (As used herein, the term "switch" includes not only conventional network switches but also routers, bridges, hubs, and other devices that forward network communication packets between ports.) Each of the servers 110 is connected to the TOR switch 112 via a network cable 120, which can transmit signals at a sufficiently high symbol rate to encourage the use of a maximum likelihood sequence detector (MLSD).

[0020] Figure 2 An illustrative switch 112 with an application-specific integrated circuit (ASIC) 202 is shown, which implements packet switching functionality coupled to a port connector 204 for a pluggable retimer module 206. The pluggable retimer module 206 is coupled between the port connector 204 and a cable connector 208 to improve communication performance through equalization and optional format conversion (e.g., conversion between electrical and optical signals). The pluggable retimer module 206 can conform to any of a variety of pluggable retimer module standards, including SFP, SFP-DD, QSFP, QSFP-DD, and OSFP.

[0021] Each of the pluggable retimer modules 206 may include a retimer chip 210 and a microcontroller chip 212. The microcontroller chip 212 controls the operation of the retimer chip 210 according to firmware and parameters that can be stored in non-volatile memory 214. The operating mode and parameters of the pluggable retimer module 206 can be set via a two-wire bus (such as I2C or MDIO) that connects the microcontroller chip 212 to a host device (e.g., switch 112). The microcontroller chip 212 responds to queries and commands received via the two-wire bus and accordingly retrieves information from and saves the information to the control register 218 of the retimer chip 210.

[0022] The retimer chip 210 includes a host-side transceiver 220 coupled to the line-side transceiver 222 via a first-in-first-out (FIFO) buffer 224. Figure 2 Optional photoelectric transmitter (PE) and photodetector (PD) modules are shown for switching between optical line-side signals and host-side signals. Although only a single channel is shown in the figure, the transceiver can support multiple channels transmitted via multiple corresponding optical fibers or electrical conductors. Controller 226 coordinates the operation of the transceiver according to the contents of the control register and can provide multiple communication phases according to communication standards, such as the Fiber Channel standard published by the National Institute of Information Technology Standards Certification Standards (INCITS), which provides phases for link speed negotiation (LSN), equalizer training, and normal operation.

[0023] Figure 3 It has three decision thresholds T 0 / 1 T 1 / 2 T 2 / 3 Illustrative PAM4 eye diagram, three decision thresholds T 0 / 1 T 1 / 2 T 2 / 3 Used to distinguish four possible symbols 0, 1, 2, and 3 with corresponding target levels L0=-A, L1=-A / 3, L2=A / 3, and L3=A. The decision thresholds are nominally set to 0 and ±2A / 3. Noise, interference, and other channel effects cause signal variations, extend the signal path, and reduce eye size, thereby increasing the probability of symbol detection errors.

[0024] Figure 4 A single-tap DFE is shown. The analog-to-digital converter (ADC) 402 converts the analog received signal r(t) into a digital received signal x. k The digital receiver signal x k The received signal y can be filtered by a forward equalizer (FFE) 404 to produce a filtered signal with minimal pre-symbol interference (ISI). kThe FFE 404 can further shape the signal spectrum to limit the post-ISI to a single symbol. In other words, the filtered received signal can be expressed as:

[0025] (1)

[0026] Where d k ∈{0,1,2,3} represents the transmitted PAM4 symbol, L(d k ) is a mapping from PAM4 symbols to their corresponding signal levels, and n k This indicates noise plus some other losses.

[0027] Adder 406 combines the filtered received signal with the feedback signal Combining to produce an equalized signal s with reduced post-ISI. k Thus (in the absence of significant channel noise) it has properties such as Figure 3 The open decision eye is shown. Limiter 408 compares the equalization signal with the decision threshold to determine the symbol decision. The delay element 410 latches the symbol decision for one symbol interval. This allows it to be used for decision-making in the preceding symbol during the next symbol interval. Symbol mapper 412 converts symbols to their target level. The multiplier 414 passes through the feedback filter coefficients. The symbol mapper output is scaled to produce a feedback signal f for adder 406. k .

[0028] Instead of DFE, conventional MLSD can be applied to filtered received signals. When the post-ISI is confined to a PAM4 symbol interval, conventional MLSD will employ, as follows: Figure 5 The four-state grid shown is for the FFE output sequence Find the likelihood Maximized PAM4 sequence .

[0029] Each level of the grid has 4 states. , 0≤j<4, represents the four possible PAM4 symbols of the k-th symbol interval. From the previous symbol d k-1 up to the current code element d k There are 16 possible transformations; each transformation has an associated branch metric. Where the exponents 0≤i<4 and 0≤j<4 represent the four possible PAM4 symbols of the previous and current symbol intervals, respectively. The branch metric is calculated as follows:

[0030] (2)

[0031] Each state has an associated state metric. It indicates from the beginning to The cumulative branch metric of the maximum likelihood path for a state. The state metric is calculated as follows:

[0032] (3)

[0033] Based on the above equation, MLSD finds the maximum likelihood path from the beginning to the end of the sequence, and the maximum likelihood decision sequence is the decision sequence associated with the branches that constitute the maximum likelihood path.

[0034] A typical MLSD for PAM4 with a symbol interval after ISI requires sixteen branch metric computation units and four 4-way Add Compare Select (ACS) units in the critical timing path of each symbol interval. For data center applications, the power consumption of such components will be excessive at data rates exceeding 50 Gbaud.

[0035] To achieve a reduced-complexity MLSD (rMLSD), we now introduce the concept of "race decision." If the DFE's symbol decision... It is given and The most likely transmitted symbol is then used for contention symbol decision. This is the second possible transmitted symbol. The error calculation circuit can calculate the equalization error signal e. k Equalization error signal e k Limited to:

[0036] (4)

[0037] This enables the contention symbol decision circuit to determine the contention symbol decision. Competition codeword decision for PAM4 yes:

[0038]

[0039] We observed that, under actual operating conditions, the transmitted symbols It is very likely equal to or equal to Therefore, the MLSD mesh can be simplified to considering only the possible symbol decisions with minimal performance loss.

[0040] From a mathematical perspective, let ,in The proposed low-complexity MLSD finds the maximum likelihood sequence that satisfies the following conditions:

[0041] (5)

[0042] Now, let "0" represent The state, and "1" represents The proposed low-complexity MLSD is in a state of flux. Figure 6 The operation is performed on a two-state grid as shown. Each level in the grid has only two states. , 0≤j<2, and has a branching metric There are four branches, where 0 ≤ i < 2 and 0 ≤ j < 2. The branch metric is calculated as follows:

[0043] (6)

[0044] Where given for:

[0045] (7)

[0046] In equation (7), and They are respectively and The complementary value. For example, if , ;if , State measurement The calculation for 0≤j<2 is as follows:

[0047] (8)

[0048] Each state has a path memory of predefined length to store the decisions of the branches of the survival path that constitutes that state, which is the maximum likelihood path from the start of the grid to the current state. The decision for each branch is the same as the ending state of the branch. Compared to a regular MLSD where the decision for each branch has 2 bits, the proposed low-complexity MLSD has only 1 bit for the decision for each branch. Unlike a regular MLSD with complexity that grows quadratically with constellation size, rMLSD does not require any complexity increase beyond that required by the DFE equalizer.

[0049] Figure 7 An illustrative receiver implementation is shown, featuring a decision feedback equalizer (DFE) that provides initial symbol decisions to the rMLSD 720. Limiter 408 ( Figure 4The equalization signal is replaced here by a limiter 708, which compares the equalization signal with a decision threshold to determine the initial symbol decision. Furthermore, it compares the equalization signal with the target level to determine the contention symbol decision. Alternatively, contention symbol decisions can be determined based on the initial symbol decision and the equalization error symbol. The rMLSD 720 processes the filtered received signal y k Initial code element decision And optional competing codeword decisions Perform the operation to derive a refined or "final" symbol decision sequence d. k .

[0050] Figure 7 The DFE employs a feedback filter. As described elsewhere (e.g., U.S. Patent 9,071,479, "High-speed parallel decision feedback equalizer"), a pre-compensation unit can be used to "expand" the feedback filter to generate provisional symbol decisions from which the initial symbol decision can be selected by the multiplexer.

[0051] Figure 8 Additional implementation details for the limiter 708 and rMLSD 720 are provided. The limiter 708 includes a limiter for the equalization signal s k With the decision threshold T 0 / 1 T 1 / 2 T 2 / 3 And a set of comparators that compare the target levels L1 and L2, thereby generating an initial symbol decision that can be easily converted by logic gates for use in a branch metric calculation circuit system (components 412~414 and 812~826). and competing code word judgment The binary representation of a set of comparator outputs. Delay elements 410 and 810 latch these decisions for a symbol interval and provide them to the copy-shift register pair 811 and the symbol mappers 412 and 812.

[0052] Symbol mappers 412 and 812 convert the binary symbol representation into its corresponding target level. Multipliers 414 and 814 then pass the ISI coefficients. The scaling mapper outputs are multiplied and their respective products are provided to delay elements 816, 818. A separate delay element 819 latches the filtered received signal for one symbol interval. A set of adders 820 combines the outputs of the symbol mappers 412, 812 and the delay elements 816, 818, 819 to calculate different branch errors, which are squared by the amplitude element 821 to provide various branch metrics in equation (6). In other words, the branch metric calculation circuit combines the filtered received signal with symbol decisions from the initial sequence (mapped to their respective target levels by mapper 412) and with associated competing symbol decisions (mapped to their respective target levels by mapper 812) to determine the corresponding branch metrics.

[0053] The Add, Compare, Select (ACS) circuitry 822 combines the appropriate branch metric with the previous state metric from latches 823, 824 to obtain the path metric for the current symbol interval. The path metrics are compared according to equation (8) and the minimum is selected. Multiplexers 825, 826 forward the selected metric to state metric latches 823, 824. The comparator result is provided to copy-shift register pair 811 to forward the initial symbol decision and contention symbol decision to a series of latches in a manner that assembles the most probable sequence of symbol decisions for each grid state. State metric comparator 827 can use output multiplexer 828 to compare latched state metrics to select a symbol decision from the preceding sequence determined to be the most probable assembly sequence.

[0054] Figure 9A This is a chart comparing the performance of DFE with that of the DFE+rMLSD combination and the FFE+MLSD combination (assuming the post-ISI coefficient is 0.5). Figure 9B The same comparison is provided with the assumption that the ISI coefficient is 0.625. rMLSD performance is almost indistinguishable from regular MLSD performance, and compared to DFE alone, each exhibits a performance gain of over 1 dB. Figure 9A ) and a performance gain of 1.5dB.

[0055] Once fully understanding the above disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, the disclosed principles apply not only to PAM, QAM, and PSK modulation, but also to larger signal constellations including 8-PSK, 16-PAM, etc. Although a post-ISI interval has been described above, the disclosed principles also apply to longer post-ISI intervals, albeit with an increased number of grid states. The claims are intended to be interpreted as covering all such alternatives, equivalents, and modifications included within the scope of the appended claims.

Claims

1. A receiver, comprising: A decision feedback equalizer derives an initial sequence of symbol decisions from a filtered received signal, each symbol decision in the initial sequence having a second possible symbol decision. as well as The reduced-complexity maximum likelihood sequence detector (rMLSD) derives the final sequence of symbol decisions by evaluating a state metric used only for each symbol decision in the initial sequence and its second possible symbol decision.

2. The receiver as described in claim 1, characterized in that, The decision feedback equalizer includes: An adder that combines the feedback signal with the filtered received signal to generate an equalized signal; A limiter, the limiter deriving the initial sequence for symbol decisions from the equalization signal; and A feedback filter that derives the feedback signal from the initial sequence of symbol decisions.

3. The receiver as described in claim 2, characterized in that, The limiter further derives a second possible symbol decision for each symbol decision in the initial sequence.

4. The receiver as described in claim 1, characterized in that, The decision feedback equalizer includes: A pre-compensation unit, which derives a provisional symbol decision from the filtered received signal; and A multiplexer that selects from the provisional symbol decisions based on previous symbol decisions in the initial sequence.

5. The receiver of claim 4, further comprising: An error calculation circuit, which determines the equalization error based on the initial sequence combination of symbol decisions; as well as A contention-based symbol decision circuit that determines the second possible symbol decision based on the equalization error and the initial sequence of symbol decisions.

6. The receiver as claimed in claim 1, characterized in that, The rMLSD includes: A branch metric calculation circuit system that combines the filtered received signal with symbol decisions from the initial sequence and with associated second possible symbol decisions to determine the corresponding branch metric, and adds each branch metric to each previous state metric to obtain a path metric; A comparator that determines the minimum path metric for each symbol decision and each second possible symbol decision in the initial sequence; and A copy-shift register pair, which, in response to the comparator's output, assembles the most probable sequence of symbol decisions ending with the symbol decision and the second possible symbol decision.

7. The receiver as claimed in claim 6, characterized in that, The rMLSD further includes a state metric comparator that selects the most likely symbol decision sequence and uses symbol decisions from preceding sequences as symbol decisions for the final sequence.

8. A receiving method, comprising: An initial sequence of symbol decisions is derived from the filtered received signal, and each symbol decision in the initial sequence has a second possible symbol decision; as well as The final sequence of symbol decisions is derived using a reduced-complexity maximum likelihood sequence detector (rMLSD) by evaluating a state metric used only for each symbol decision in the initial sequence and its second possible symbol decision.

9. The receiving method as described in claim 8, characterized in that, As part of the final sequence of derived symbol decisions, the rMLSD: The filtered received signal or initial equalization error signal is combined with the symbol decision from the initial sequence and with the associated second possible symbol decision to determine the corresponding equalization error; Each equilibrium error is summed with each previous state metric to obtain the branch metric; Determine the minimum path metric for each symbol decision and each second possible symbol decision in the initial sequence; The assembly ends with the symbol decision from the initial sequence; and The assembly ends with the second sequence that is associated with the second possible codeword decision.

10. The receiving method as described in claim 9, characterized in that, As part of the final sequence of derived symbol decisions, the rMLSD further: Compare the state metrics used for the first sequence and the second sequence; as well as The symbol decision is provided from the beginning of the selected sequence from the first sequence and the second sequence as the symbol decision for the final sequence.

11. The receiving method as described in claim 8, characterized in that, The initial sequence for the symbol decision is derived by the following: The feedback signal is combined with the filtered received signal to generate an equalized signal; The equalization signal is compared with a set of thresholds to obtain the initial sequence for symbol decision; as well as The initial sequence of code element decisions is converted into a feedback signal.

12. The receiving method of claim 11, further comprising comparing the equalization signal with a set of target symbol levels to derive a second possible symbol decision for each symbol decision in the initial sequence.

13. The receiving method as described in claim 8, characterized in that, The initial sequence for deriving the symbol decision includes: The filtered received signal is converted into provisional symbol decision using a pre-compensation unit; The provisional symbol decision is selected from the previous symbol decision in the initial sequence.

14. The receiving method as described in claim 13, further comprising: The filtered received signal or initial equalization error signal is combined with the initial sequence of symbol decision to determine the equalization error; as well as The second possible symbol decision is determined based on the initial sequence of the initial equalization error and the symbol decision.

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